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Acked-by: Krzysztof Kozlowski Signed-off-by: Thomas Perrot (Schneider Electric) --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a74560a4f687fe7a2070ca21b0752..0f84ee93b3a8473719ee92f8c04= 6e350c4a20825 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -32,6 +32,8 @@ patternProperties: description: 8devices, UAB "^9tripod,.*": description: Shenzhen 9Tripod Innovation and Development CO., LTD. + "^aaeon,.*": + description: AAEON "^abb,.*": description: ABB "^abilis,.*": --=20 2.53.0 From nobody Thu Apr 2 03:24:27 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 407CA303CA0; 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This microcontroller is found on AAEON embedded boards, it is connected via I2C and and provides a GPIO control and watchdog timer. Reviewed-by: Conor Dooley Signed-off-by: Thomas Perrot (Schneider Electric) --- .../bindings/mfd/aaeon,srg-imx8p-mcu.yaml | 67 ++++++++++++++++++= ++++ MAINTAINERS | 6 ++ 2 files changed, 73 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml= b/Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4895028e72eb3ac2376b61ed9c0= 6549b42da66d3 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/aaeon,srg-imx8p-mcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AAEON Embedded Controller + +maintainers: + - J=C3=A9r=C3=A9mie Dautheribes + - Thomas Perrot + +description: + AAEON embeds a microcontroller on Standard RISC Gateway with ARM i.MX8M = Plus + Quad-Core boards providing GPIO control and watchdog timer. + + This MCU is connected via I2C bus. + + Its GPIO controller provides 7 GPOs and 12 GPIOs. + + Its watchdog has a fixed maximum hardware heartbeat of 25 seconds and su= pports + a timeout of 240 seconds through automatic pinging. + The timeout is not programmable and cannot be changed via device tree pr= operties. + +properties: + compatible: + const: aaeon,srg-imx8p-mcu + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-line-names: + minItems: 1 + maxItems: 19 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + embedded-controller@62 { + compatible =3D "aaeon,srg-imx8p-mcu"; + reg =3D <0x62>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "gpo-1", "gpo-2", "gpo-3", "gpo-4", + "gpo-5", "gpo-6", "gpo-7", + "gpio-1", "gpio-2", "gpio-3", "gpio-4", + "gpio-5", "gpio-6", "gpio-7", "gpio-8", + "gpio-9", "gpio-10", "gpio-11", "gpio-12"; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index c9e416ba74c64e90629c0b7d7941f879c9ac589e..ea9d55f76f3509c7f6ba6d1bc86= ca2e2e71aa954 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -186,6 +186,12 @@ W: http://www.adaptec.com/ F: Documentation/scsi/aacraid.rst F: drivers/scsi/aacraid/ =20 +AAEON SRG-IMX8P CONTROLLER MFD DRIVER +M: Thomas Perrot +R: J=C3=A9r=C3=A9mie Dautheribes +S: Maintained +F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml + AAEON UPBOARD FPGA MFD DRIVER M: Thomas Richard S: Maintained --=20 2.53.0 From nobody Thu Apr 2 03:24:27 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 221DA2C0F84; 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bh=UGL1FngKXWCgRtQ6FWCBPJEK7tWFqJr3/YLfN6h8aC8=; b=ninpLKDaCQwZrqbu9aEhtg8IHrPbrK0GfIfkzp9MC0qBIvAVyhr/H5vKeRcp/GhMFBTNtQ r0DN+W6sn49U2TUwy7JRMQZ2W8aOhCiAYkqeXMEXNYdEv6XvpkyxvQaJmj4XTREXkfdlul V/XON+22A0M5rlzWRLpNClFeU0b/VMxRBxaPr/eQQ4a44K3Dfi5BmPsLFcB1/5Gq+9jQn1 8XFnEngw+NLTg3gY8nMj5xN0MwaDb3xWVuUdVwqb8d5pCbMU/Sb3TjQ8xGvxPx1jvvWALt ZC/LHtJo59URMY3Jlj/m6jQTFUnsc2CauLV91a86hHpYsWsi2lCyvacazdqXNQ== From: "Thomas Perrot (Schneider Electric)" Date: Tue, 24 Mar 2026 20:24:29 +0100 Subject: [PATCH v4 3/5] mfd: aaeon: Add SRG-IMX8P MCU driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260324-dev-b4-aaeon-mcu-driver-v4-3-afb011df4794@bootlin.com> References: <20260324-dev-b4-aaeon-mcu-driver-v4-0-afb011df4794@bootlin.com> In-Reply-To: <20260324-dev-b4-aaeon-mcu-driver-v4-0-afb011df4794@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?utf-8?q?J=C3=A9r=C3=A9mie_Dautheribes?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni , Miquel Raynal , "Thomas Perrot (Schneider Electric)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8495; i=thomas.perrot@bootlin.com; h=from:subject:message-id; bh=d+BkQJpdUUbVfiWpGXEH+iAN3nggRjJsqUblHTPBDXI=; b=owEB7QES/pANAwAKAZ/ACwVx/grtAcsmYgBpwuT29nCclVo5UcagNOTSFbhpzSvAHxpmSAOXI dmrLjIZLmqJAbMEAAEKAB0WIQSHQHfGpqMKIwOoEiGfwAsFcf4K7QUCacLk9gAKCRCfwAsFcf4K 7fnWC/0Wblk1hquJN3CTe5tAQOz9fowxysDxw/rU7ZG01TUlpCQZNCQBH0Ln9Dju07ca7bimzpL sEYEpsfBsUU2dbSn6FBjWvXDCdX/TIfxKdLE82t9ufFvO14sPo80aLaiyiNPRpzE6DzjtnOowOP 1vt85pj0xKx/D6OCb2sE8A4ln6pye4oYgA0St21GXSze73Q4fMQZdpTSk/fKapTlQytxmYQwSf0 2fx5WKYgooi39/o7cIhAFhcsaBvmLBG7uzzud93Z2PTIm9+HdKgVqvPrS+XtODKsEoAYJw8+Eb1 OL/E0+K4iMgZXQX1V3Pd8k076ywF0zlHAEAjDAElEXRArpmeINiGNK8mCbmAi4LRcJxZAS2fLt2 19BVlfRAG6B4Fklef22FHi0q2xftGpB/u1Fs7+XA+eTmHdy1VsBEljeUwFlm1mpGxHtkQEJYxMQ d5F+IrTiqGgIpocnTtBKnLA0JkcV9YzodV5YyijDcFU8HpVJw0kRHtTLRYYBEu7Bgo+vc= X-Developer-Key: i=thomas.perrot@bootlin.com; a=openpgp; fpr=874077C6A6A30A2303A812219FC00B0571FE0AED X-Last-TLS-Session-Version: TLSv1.3 Add Multi-Function Device (MFD) driver for the Aaeon SRG-IMX8P embedded controller. This driver provides the core I2C communication interface and registers child devices (GPIO and watchdog controllers). The driver implements a custom regmap bus over I2C to match the MCU's fixed 3-byte command format [opcode, arg, value]. Register addresses are encoded as 16-bit values (opcode << 8 | arg) using the AAEON_MCU_REG() macro defined in the shared header. The regmap instance is shared with child drivers via dev_get_regmap(). Concurrent I2C accesses from child drivers are serialized by regmap's built-in locking. Co-developed-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: Thomas Perrot (Schneider Electric) --- MAINTAINERS | 2 + drivers/mfd/Kconfig | 10 +++ drivers/mfd/Makefile | 1 + drivers/mfd/aaeon-mcu.c | 155 ++++++++++++++++++++++++++++++++++++++= ++++ include/linux/mfd/aaeon-mcu.h | 20 ++++++ 5 files changed, 188 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ea9d55f76f3509c7f6ba6d1bc86ca2e2e71aa954..f91b6a1826d04bef8a0f88221f6= c8e8a3652cd77 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -191,6 +191,8 @@ M: Thomas Perrot R: J=C3=A9r=C3=A9mie Dautheribes S: Maintained F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml +F: drivers/mfd/aaeon-mcu.c +F: include/linux/mfd/aaeon-mcu.h =20 AAEON UPBOARD FPGA MFD DRIVER M: Thomas Richard diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index aace5766b38aa5e46e32a8a7b42eea238159fbcf..7a1ceedece899faad7a03a1fe7b= 1c91b72253c05 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1574,6 +1574,16 @@ config AB8500_CORE the irq_chip parts for handling the Mixed Signal chip events. This chip embeds various other multimedia functionalities as well. =20 +config MFD_AAEON_MCU + tristate "Aaeon SRG-IMX8P MCU Driver" + depends on I2C || COMPILE_TEST + select MFD_CORE + help + Select this option to enable support for the Aaeon SRG-IMX8P + onboard microcontroller (MCU). This driver provides the core + functionality to communicate with the MCU over I2C. The MCU + provides GPIO and watchdog functionality. + config MFD_DB8500_PRCMU bool "ST-Ericsson DB8500 Power Reset Control Management Unit" depends on UX500_SOC_DB8500 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e75e8045c28afae975ac61d282b3b85af5440119..34db5b033584368b7a269b1eef1= 2528a74baf8f5 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X) +=3D 88pm860x.o obj-$(CONFIG_MFD_88PM800) +=3D 88pm800.o 88pm80x.o obj-$(CONFIG_MFD_88PM805) +=3D 88pm805.o 88pm80x.o obj-$(CONFIG_MFD_88PM886_PMIC) +=3D 88pm886.o +obj-$(CONFIG_MFD_AAEON_MCU) +=3D aaeon-mcu.o obj-$(CONFIG_MFD_ACT8945A) +=3D act8945a.o obj-$(CONFIG_MFD_SM501) +=3D sm501.o obj-$(CONFIG_ARCH_BCM2835) +=3D bcm2835-pm.o diff --git a/drivers/mfd/aaeon-mcu.c b/drivers/mfd/aaeon-mcu.c new file mode 100644 index 0000000000000000000000000000000000000000..5a969890d201c027eb25c324b4d= 4d89b1f8c563e --- /dev/null +++ b/drivers/mfd/aaeon-mcu.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aaeon MCU driver + * + * Copyright (C) 2025 Bootlin + * Author: J=C3=A9r=C3=A9mie Dautheribes + * Author: Thomas Perrot + */ + +#include +#include +#include +#include +#include + +static const struct mfd_cell aaeon_mcu_devs[] =3D { + { + .name =3D "aaeon-mcu-wdt", + }, + { + .name =3D "aaeon-mcu-gpio", + }, +}; + +/* + * Custom regmap bus for the Aaeon MCU I2C protocol. + * + * The MCU uses a fixed 3-byte command format [opcode, arg, value] followed + * by a 1-byte response. It requires a STOP condition between the command + * write and the response read, so two separate i2c_transfer() calls are + * issued. The regmap lock serialises concurrent accesses from the GPIO + * and watchdog child drivers. + * + * Register addresses are encoded as a 16-bit big-endian value where the + * high byte is the opcode and the low byte is the argument, matching the + * wire layout produced by regmap for reg_bits=3D16. + */ + +static int aaeon_mcu_regmap_write(void *context, const void *data, size_t = count) +{ + struct i2c_client *client =3D context; + /* data =3D [opcode, arg, value] as formatted by regmap */ + struct i2c_msg write_msg =3D { + .addr =3D client->addr, + .flags =3D 0, + .buf =3D (u8 *)data, + .len =3D count, + }; + u8 rsp; + /* The MCU always sends a response byte after each command; discard it. */ + struct i2c_msg rsp_msg =3D { + .addr =3D client->addr, + .flags =3D I2C_M_RD, + .buf =3D &rsp, + .len =3D 1, + }; + int ret; + + ret =3D i2c_transfer(client->adapter, &write_msg, 1); + if (ret < 0) + return ret; + if (ret !=3D 1) + return -EIO; + + ret =3D i2c_transfer(client->adapter, &rsp_msg, 1); + if (ret < 0) + return ret; + if (ret !=3D 1) + return -EIO; + + return 0; +} + +static int aaeon_mcu_regmap_read(void *context, const void *reg_buf, + size_t reg_size, void *val_buf, size_t val_size) +{ + struct i2c_client *client =3D context; + /* + * reg_buf holds the 2-byte big-endian register address [opcode, arg]. + * Append a trailing 0x00 to form the full 3-byte MCU command. + */ + u8 cmd[3] =3D { ((u8 *)reg_buf)[0], ((u8 *)reg_buf)[1], 0x00 }; + struct i2c_msg write_msg =3D { + .addr =3D client->addr, + .flags =3D 0, + .buf =3D cmd, + .len =3D sizeof(cmd), + }; + struct i2c_msg read_msg =3D { + .addr =3D client->addr, + .flags =3D I2C_M_RD, + .buf =3D val_buf, + .len =3D val_size, + }; + int ret; + + ret =3D i2c_transfer(client->adapter, &write_msg, 1); + if (ret < 0) + return ret; + if (ret !=3D 1) + return -EIO; + + ret =3D i2c_transfer(client->adapter, &read_msg, 1); + if (ret < 0) + return ret; + if (ret !=3D 1) + return -EIO; + + return 0; +} + +static const struct regmap_bus aaeon_mcu_regmap_bus =3D { + .write =3D aaeon_mcu_regmap_write, + .read =3D aaeon_mcu_regmap_read, +}; + +static const struct regmap_config aaeon_mcu_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .reg_format_endian =3D REGMAP_ENDIAN_BIG, + .cache_type =3D REGCACHE_NONE, +}; + +static int aaeon_mcu_probe(struct i2c_client *client) +{ + struct regmap *regmap; + + regmap =3D devm_regmap_init(&client->dev, &aaeon_mcu_regmap_bus, + client, &aaeon_mcu_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE, + aaeon_mcu_devs, ARRAY_SIZE(aaeon_mcu_devs), + NULL, 0, NULL); +} + +static const struct of_device_id aaeon_mcu_of_match[] =3D { + { .compatible =3D "aaeon,srg-imx8p-mcu" }, + {}, +}; +MODULE_DEVICE_TABLE(of, aaeon_mcu_of_match); + +static struct i2c_driver aaeon_mcu_driver =3D { + .driver =3D { + .name =3D "aaeon_mcu", + .of_match_table =3D aaeon_mcu_of_match, + }, + .probe =3D aaeon_mcu_probe, +}; +module_i2c_driver(aaeon_mcu_driver); + +MODULE_DESCRIPTION("Aaeon MCU Driver"); +MODULE_AUTHOR("J=C3=A9r=C3=A9mie Dautheribes "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/aaeon-mcu.h b/include/linux/mfd/aaeon-mcu.h new file mode 100644 index 0000000000000000000000000000000000000000..861003f6dfd20424c3785008bd2= cf89aaa1715b9 --- /dev/null +++ b/include/linux/mfd/aaeon-mcu.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Aaeon MCU driver definitions + * + * Copyright (C) 2025 Bootlin + * Author: J=C3=A9r=C3=A9mie Dautheribes + * Author: Thomas Perrot + */ + +#ifndef __LINUX_MFD_AAEON_MCU_H +#define __LINUX_MFD_AAEON_MCU_H + +/* + * MCU register address: the high byte is the command opcode, the low + * byte is the argument. This matches the 3-byte wire format + * [opcode, arg, value] used by the MCU I2C protocol. + */ +#define AAEON_MCU_REG(op, arg) (((op) << 8) | (arg)) + +#endif /* __LINUX_MFD_AAEON_MCU_H */ --=20 2.53.0 From nobody Thu Apr 2 03:24:27 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE11D30F7F2; Tue, 24 Mar 2026 19:24:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774380299; cv=none; b=PFZ4VmoPqC3Q8VKpPSol8Rn4qIuF7j4c9tZ/nzfykRn7ohGS/54PZC6qZ1oBiNackiAHM4uYiUaWI6jdILmB1cJyC/Qk7/Gtmk6rp0lcrNf2IAjGq8RmhGBw1a3e/SeZJCiP15C9fsLgsmQ8ZgNqvw8A6V/hrchRWC2H6ytsNkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774380299; c=relaxed/simple; bh=eFqla8qPpbYDWPfac3s+lPB3ga1v1YuIUFaJz8wk9x8=; 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a=openpgp; fpr=874077C6A6A30A2303A812219FC00B0571FE0AED X-Last-TLS-Session-Version: TLSv1.3 Add GPIO driver for the Aaeon SRG-IMX8P embedded controller. This driver supports 7 GPO (General Purpose Output) pins and 12 GPIO pins that can be configured as inputs or outputs. The driver implements proper state management for GPO pins (which are output-only) and full direction control for GPIO pins. During probe, all pins are reset to a known state (GPOs low, GPIOs as inputs) to prevent undefined behavior across system reboots, as the MCU does not reset GPIO states on soft reboot. Co-developed-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Thomas Perrot (Schneider Electric) --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-aaeon-mcu.c | 221 ++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 233 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f91b6a1826d04bef8a0f88221f6c8e8a3652cd77..2538f8c4bc1482b139e18243a68= f0a21b9be3704 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -191,6 +191,7 @@ M: Thomas Perrot R: J=C3=A9r=C3=A9mie Dautheribes S: Maintained F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml +F: drivers/gpio/gpio-aaeon-mcu.c F: drivers/mfd/aaeon-mcu.c F: include/linux/mfd/aaeon-mcu.h =20 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c74da29253e810b51540684b1186e8f274066b69..04285dc77430a5dbdb2d6e03e51= bca64a432bf1a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -157,6 +157,16 @@ config GPIO_74XX_MMIO 8 bits: 74244 (Input), 74273 (Output) 16 bits: 741624 (Input), 7416374 (Output) =20 +config GPIO_AAEON_MCU + tristate "Aaeon MCU GPIO support" + depends on MFD_AAEON_MCU + select GPIO_GENERIC + help + Select this option to enable GPIO support for the Aaeon SRG-IMX8P + onboard MCU. This driver provides access to GPIO pins and GPO + (General Purpose Output) pins controlled by the microcontroller. + The driver handles both input and output configuration. + config GPIO_ALTERA tristate "Altera GPIO" select GPIOLIB_IRQCHIP diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 2421a8fd3733e0b06c2581262aaa9cd629f66c7d..1ba6318bc558743fbe5910966c2= c8fc3f792efe9 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_104_IDI_48) +=3D gpio-104-idi-48.o obj-$(CONFIG_GPIO_104_IDIO_16) +=3D gpio-104-idio-16.o obj-$(CONFIG_GPIO_74X164) +=3D gpio-74x164.o obj-$(CONFIG_GPIO_74XX_MMIO) +=3D gpio-74xx-mmio.o +obj-$(CONFIG_GPIO_AAEON_MCU) +=3D gpio-aaeon-mcu.o obj-$(CONFIG_GPIO_ADNP) +=3D gpio-adnp.o obj-$(CONFIG_GPIO_ADP5520) +=3D gpio-adp5520.o obj-$(CONFIG_GPIO_ADP5585) +=3D gpio-adp5585.o diff --git a/drivers/gpio/gpio-aaeon-mcu.c b/drivers/gpio/gpio-aaeon-mcu.c new file mode 100644 index 0000000000000000000000000000000000000000..3b679259a6c66e3113cadc083dc= 7b4152d070ed5 --- /dev/null +++ b/drivers/gpio/gpio-aaeon-mcu.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aaeon MCU GPIO driver + * + * Copyright (C) 2025 Bootlin + * Author: J=C3=A9r=C3=A9mie Dautheribes + * Author: Thomas Perrot + */ + +#include +#include +#include +#include +#include +#include +#include + +#define AAEON_MCU_CONFIG_GPIO_INPUT 0x69 +#define AAEON_MCU_CONFIG_GPIO_OUTPUT 0x6F +#define AAEON_MCU_READ_GPIO 0x72 +#define AAEON_MCU_WRITE_GPIO 0x77 + +#define AAEON_MCU_CONTROL_GPO 0x6C + +#define MAX_GPIOS 12 +#define MAX_GPOS 7 + +struct aaeon_mcu_gpio { + struct gpio_chip gc; + struct regmap *regmap; + DECLARE_BITMAP(dir_in, MAX_GPOS + MAX_GPIOS); + DECLARE_BITMAP(gpo_state, MAX_GPOS); +}; + +static int aaeon_mcu_gpio_config_input_cmd(struct aaeon_mcu_gpio *data, + unsigned int offset) +{ + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONFIG_GPIO_INPUT, offset - 7), + 0); +} + +static int aaeon_mcu_gpio_direction_input(struct gpio_chip *gc, unsigned i= nt offset) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + int ret; + + if (offset < MAX_GPOS) { + dev_err(gc->parent, "GPIO offset (%d) must be an output GPO\n", offset); + return -EOPNOTSUPP; + } + + ret =3D aaeon_mcu_gpio_config_input_cmd(data, offset); + if (ret < 0) + return ret; + + __set_bit(offset, data->dir_in); + + return 0; +} + +static int aaeon_mcu_gpio_config_output_cmd(struct aaeon_mcu_gpio *data, + unsigned int offset, + int value) +{ + int ret; + + ret =3D regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONFIG_GPIO_OUTPUT, offset - 7), + 0); + if (ret < 0) + return ret; + + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_WRITE_GPIO, offset - 7), + !!value); +} + +static int aaeon_mcu_gpio_direction_output(struct gpio_chip *gc, unsigned = int offset, int value) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + int ret; + + if (offset < MAX_GPOS) + return 0; + + ret =3D aaeon_mcu_gpio_config_output_cmd(data, offset, value); + if (ret < 0) + return ret; + + __clear_bit(offset, data->dir_in); + + return 0; +} + +static int aaeon_mcu_gpio_get_direction(struct gpio_chip *gc, unsigned int= offset) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + + return test_bit(offset, data->dir_in) ? + GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; +} + +static int aaeon_mcu_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + unsigned int rsp; + int ret; + + if (offset < MAX_GPOS) + return test_bit(offset, data->gpo_state); + + ret =3D regmap_read(data->regmap, + AAEON_MCU_REG(AAEON_MCU_READ_GPIO, offset - 7), + &rsp); + if (ret < 0) + return ret; + + return rsp; +} + +static int aaeon_mcu_gpo_set_cmd(struct aaeon_mcu_gpio *data, unsigned int= offset, int value) +{ + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONTROL_GPO, offset + 1), + !!value); +} + +static int aaeon_mcu_gpio_set_cmd(struct aaeon_mcu_gpio *data, unsigned in= t offset, int value) +{ + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_WRITE_GPIO, offset - 7), + !!value); +} + +static int aaeon_mcu_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + + if (offset >=3D MAX_GPOS) + return aaeon_mcu_gpio_set_cmd(data, offset, value); + + if (aaeon_mcu_gpo_set_cmd(data, offset, value) =3D=3D 0) + __assign_bit(offset, data->gpo_state, value); + + return 0; +} + +static const struct gpio_chip aaeon_mcu_chip =3D { + .label =3D "gpio-aaeon-mcu", + .owner =3D THIS_MODULE, + .get_direction =3D aaeon_mcu_gpio_get_direction, + .direction_input =3D aaeon_mcu_gpio_direction_input, + .direction_output =3D aaeon_mcu_gpio_direction_output, + .get =3D aaeon_mcu_gpio_get, + .set =3D aaeon_mcu_gpio_set, + .base =3D -1, + .ngpio =3D MAX_GPOS + MAX_GPIOS, + .can_sleep =3D true, +}; + +static void aaeon_mcu_gpio_reset(struct aaeon_mcu_gpio *data, struct devic= e *dev) +{ + unsigned int i; + int ret; + + /* Reset all GPOs */ + for (i =3D 0; i < MAX_GPOS; i++) { + ret =3D aaeon_mcu_gpo_set_cmd(data, i, 0); + if (ret < 0) + dev_warn(dev, "Failed to reset GPO %u state: %d\n", i, ret); + __clear_bit(i, data->dir_in); + } + + /* Reset all GPIOs */ + for (i =3D MAX_GPOS; i < MAX_GPOS + MAX_GPIOS; i++) { + ret =3D aaeon_mcu_gpio_config_input_cmd(data, i); + if (ret < 0) + dev_warn(dev, "Failed to reset GPIO %u state: %d\n", i, ret); + __set_bit(i, data->dir_in); + } +} + +static int aaeon_mcu_gpio_probe(struct platform_device *pdev) +{ + struct aaeon_mcu_gpio *data; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); + if (!data->regmap) + return -ENODEV; + + data->gc =3D aaeon_mcu_chip; + data->gc.parent =3D pdev->dev.parent; + + /* + * Reset all GPIO states to a known configuration. The MCU does not + * reset GPIO state on soft reboot, only on power cycle (hard reboot). + * Without this reset, GPIOs would retain their previous state across + * reboots, which could lead to unexpected behavior. + */ + aaeon_mcu_gpio_reset(data, &pdev->dev); + + return devm_gpiochip_add_data(&pdev->dev, &data->gc, data); +} + +static struct platform_driver aaeon_mcu_gpio_driver =3D { + .driver =3D { + .name =3D "aaeon-mcu-gpio", + }, + .probe =3D aaeon_mcu_gpio_probe, +}; +module_platform_driver(aaeon_mcu_gpio_driver); + +MODULE_DESCRIPTION("GPIO interface for Aaeon MCU"); +MODULE_AUTHOR("J=C3=A9r=C3=A9mie Dautheribes "); +MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Thu Apr 2 03:24:27 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2408F312819; Tue, 24 Mar 2026 19:24:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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b=P9lL39LBq8Hpic2d2kTOq1A50ORaO2tfnv4QJtnyolkztW8KFPRi6TAB7le3ipL7mzoYtR 05MzCY9tvSoH6XuteTaMIaWBOh+htIYzUoYR12OKpvrGoOTGH1ssxVRL6i8Bp9KLj95crJ x/JvXtdU1/89Ls5oQ75ldw+YVmXmwKUKN9iZw85XgTa/6n5mk9Zu8hZYarYPmafvoQW7cc IK/B3T5JPu3yTLE/qOX2gwxYpn3svLJr5jWBbcY1OMqts5vnHo973XCY3v+xHti0R3H6hl tuqJxrLuQAagaXIUg4JGEBD7wgS6pLx6SjFs05HbwG/x/Yx+YUjK8YYw0UAsYA== From: "Thomas Perrot (Schneider Electric)" Date: Tue, 24 Mar 2026 20:24:31 +0100 Subject: [PATCH v4 5/5] watchdog: aaeon: Add watchdog driver for SRG-IMX8P MCU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260324-dev-b4-aaeon-mcu-driver-v4-5-afb011df4794@bootlin.com> References: <20260324-dev-b4-aaeon-mcu-driver-v4-0-afb011df4794@bootlin.com> In-Reply-To: <20260324-dev-b4-aaeon-mcu-driver-v4-0-afb011df4794@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?utf-8?q?J=C3=A9r=C3=A9mie_Dautheribes?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni , Miquel Raynal , "Thomas Perrot (Schneider Electric)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This driver provides system monitoring and recovery capabilities through the MCU's watchdog timer. The watchdog supports start, stop, and ping operations with a maximum hardware heartbeat of 25 seconds and a default timeout of 240 seconds. Co-developed-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: Thomas Perrot (Schneider Electric) --- MAINTAINERS | 1 + drivers/watchdog/Kconfig | 10 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/aaeon_mcu_wdt.c | 134 +++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 146 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2538f8c4bc1482b139e18243a68f0a21b9be3704..7b92af42c9fdc17a69a4e7a2fe5= 0f9e199c8b144 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -193,6 +193,7 @@ S: Maintained F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml F: drivers/gpio/gpio-aaeon-mcu.c F: drivers/mfd/aaeon-mcu.c +F: drivers/watchdog/aaeon_mcu_wdt.c F: include/linux/mfd/aaeon-mcu.h =20 AAEON UPBOARD FPGA MFD DRIVER diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d3b9df7d466b0b7215ee87b3040811d44ee53d2a..da54e6a641d7af343e4f0ae84f9= 6f150979f8348 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -168,6 +168,16 @@ config SOFT_WATCHDOG_PRETIMEOUT watchdog. Be aware that governors might affect the watchdog because it is purely software, e.g. the panic governor will stall it! =20 +config AAEON_MCU_WATCHDOG + tristate "Aaeon MCU Watchdog" + depends on MFD_AAEON_MCU + select WATCHDOG_CORE + help + Select this option to enable watchdog timer support for the Aaeon + SRG-IMX8P onboard microcontroller (MCU). This driver provides + watchdog functionality through the MCU, allowing system monitoring + and automatic recovery from system hangs. + config BD957XMUF_WATCHDOG tristate "ROHM BD9576MUF and BD9573MUF PMIC Watchdog" depends on MFD_ROHM_BD957XMUF diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index ba52099b125398a32f80dad23317e223cc4af028..2deec425d3eafb6b208e061fda9= f216f4baa8ecc 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_USBPCWATCHDOG) +=3D pcwd_usb.o # ALPHA Architecture =20 # ARM Architecture +obj-$(CONFIG_AAEON_MCU_WATCHDOG) +=3D aaeon_mcu_wdt.o obj-$(CONFIG_ARM_SP805_WATCHDOG) +=3D sp805_wdt.o obj-$(CONFIG_ARM_SBSA_WATCHDOG) +=3D sbsa_gwdt.o obj-$(CONFIG_ARMADA_37XX_WATCHDOG) +=3D armada_37xx_wdt.o diff --git a/drivers/watchdog/aaeon_mcu_wdt.c b/drivers/watchdog/aaeon_mcu_= wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..f01571cf0036d252f9bebd3a9d6= a1c2e7a83e42c --- /dev/null +++ b/drivers/watchdog/aaeon_mcu_wdt.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aaeon MCU Watchdog driver + * + * Copyright (C) 2025 Bootlin + * Author: J=C3=A9r=C3=A9mie Dautheribes + * Author: Thomas Perrot + */ + +#include +#include +#include +#include +#include + +#define AAEON_MCU_CONTROL_WDT 0x63 +#define AAEON_MCU_PING_WDT 0x73 + +#define AAEON_MCU_WDT_TIMEOUT 240 +#define AAEON_MCU_WDT_HEARTBEAT_MS 25000 + +struct aaeon_mcu_wdt { + struct watchdog_device wdt; + struct regmap *regmap; +}; + +static int aaeon_mcu_wdt_cmd(struct aaeon_mcu_wdt *data, u8 opcode, u8 arg) +{ + /* The MCU always sends a response byte after each command; discard it. */ + return regmap_write(data->regmap, AAEON_MCU_REG(opcode, arg), 0); +} + +static int aaeon_mcu_wdt_start(struct watchdog_device *wdt) +{ + struct aaeon_mcu_wdt *data =3D watchdog_get_drvdata(wdt); + + return aaeon_mcu_wdt_cmd(data, AAEON_MCU_CONTROL_WDT, 0x01); +} + +static int aaeon_mcu_wdt_status(struct watchdog_device *wdt, bool *enabled) +{ + struct aaeon_mcu_wdt *data =3D watchdog_get_drvdata(wdt); + unsigned int rsp; + int ret; + + ret =3D regmap_read(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONTROL_WDT, 0x02), + &rsp); + if (ret) + return ret; + + *enabled =3D rsp =3D=3D 0x01; + return 0; +} + +static int aaeon_mcu_wdt_stop(struct watchdog_device *wdt) +{ + struct aaeon_mcu_wdt *data =3D watchdog_get_drvdata(wdt); + + return aaeon_mcu_wdt_cmd(data, AAEON_MCU_CONTROL_WDT, 0x00); +} + +static int aaeon_mcu_wdt_ping(struct watchdog_device *wdt) +{ + struct aaeon_mcu_wdt *data =3D watchdog_get_drvdata(wdt); + + return aaeon_mcu_wdt_cmd(data, AAEON_MCU_PING_WDT, 0x00); +} + +static const struct watchdog_info aaeon_mcu_wdt_info =3D { + .identity =3D "Aaeon MCU Watchdog", + .options =3D WDIOF_KEEPALIVEPING +}; + +static const struct watchdog_ops aaeon_mcu_wdt_ops =3D { + .owner =3D THIS_MODULE, + .start =3D aaeon_mcu_wdt_start, + .stop =3D aaeon_mcu_wdt_stop, + .ping =3D aaeon_mcu_wdt_ping, +}; + +static int aaeon_mcu_wdt_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct watchdog_device *wdt; + struct aaeon_mcu_wdt *data; + bool enabled; + int ret; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regmap =3D dev_get_regmap(dev->parent, NULL); + if (!data->regmap) + return -ENODEV; + + wdt =3D &data->wdt; + wdt->parent =3D dev; + wdt->info =3D &aaeon_mcu_wdt_info; + wdt->ops =3D &aaeon_mcu_wdt_ops; + /* + * The MCU firmware has a fixed hardware timeout of 25 seconds that + * cannot be changed. The watchdog core will handle automatic pinging + * to support longer timeouts. The software timeout of 240 seconds is + * chosen arbitrarily as a reasonable value and is not user-configurable. + */ + wdt->timeout =3D AAEON_MCU_WDT_TIMEOUT; + wdt->max_hw_heartbeat_ms =3D AAEON_MCU_WDT_HEARTBEAT_MS; + + watchdog_set_drvdata(wdt, data); + + ret =3D aaeon_mcu_wdt_status(wdt, &enabled); + if (ret) + return ret; + + if (enabled) + set_bit(WDOG_HW_RUNNING, &wdt->status); + + return devm_watchdog_register_device(dev, wdt); +} + +static struct platform_driver aaeon_mcu_wdt_driver =3D { + .driver =3D { + .name =3D "aaeon-mcu-wdt", + }, + .probe =3D aaeon_mcu_wdt_probe, +}; + +module_platform_driver(aaeon_mcu_wdt_driver); + +MODULE_DESCRIPTION("Aaeon MCU Watchdog Driver"); +MODULE_AUTHOR("J=C3=A9r=C3=A9mie Dautheribes "); +MODULE_LICENSE("GPL"); --=20 2.53.0