From nobody Sun Apr 5 16:27:54 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71A3436B076; Mon, 23 Mar 2026 22:03:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774303415; cv=none; b=CvdILwEJY0BNPUPkqODBiFx/9xhn9axEtRVdZYu8JbT09xVyzr7B/L0czVB2clrYn1ax8w7tTymXCY3D5SAz9woIoxC7q4qfNff9qb1sLLpq8tA7inbjDsUHW43JJH0wqYwVK66Hqh0apMqXIGKIaOshhNiS9NCHqpYcBcSQlbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774303415; c=relaxed/simple; bh=zK70z78hvfYzmL1ZSSd4XVv1IObYxslhdrOlu+be608=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=i0DmIz/XvzCXzgKoO2zL3yzBkJ5pL3jH0/6+k3h32Pu+GxwkO+d33ejeDtPc2RYRzLwyShZLM/1BnQxgOdh3Bqo+gnkTWpWfgKC3qeva1IE02PaZ5DBeebSrNV8mjlLfKjy3d91O7Ng3Or8FClXKPyy2jw0tpd7YjbdTYP4iBIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=UAB2gtuY; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="UAB2gtuY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1774303414; x=1805839414; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zK70z78hvfYzmL1ZSSd4XVv1IObYxslhdrOlu+be608=; b=UAB2gtuYrM05spiMpgrIRzlUnUw7SndSGMUG2O3NXaJ5ZXQA+fu84kg2 EysjEvzlfqlTatgCA7p6WjZS5IrbrS7YhBMWn6T8D9lWJuv32SO3BXLs1 4dicetnJl2IW7OYiVkqJ6GYU4ZArnZPaZID7Y0UYnUqKgdt/P1UQHQhss 0KalXZMDX0PswSDDSHRp/i8ntkpq0x04RBKkSunIoWZMCP7pb3HYP+ilH T5iT9IT9oOodKpFdh+nPKITNnFriAjn8z7+GX3MZ4zlamNQg5Yc0kC0eY +W2i5WHhkBpzzR7uDbM/oI1DYYCaH9FG6lhqUYgwajAynpujPQkCJqa9y A==; X-CSE-ConnectionGUID: sn68fJ6gSty0fdZcGeqDMQ== X-CSE-MsgGUID: l7F8d5J2RHqC5U0KKtZDLg== X-IronPort-AV: E=Sophos;i="6.23,138,1770620400"; d="scan'208";a="222348044" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 15:03:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Mon, 23 Mar 2026 15:03:07 -0700 Received: from bby-cbu-swbuild03.eng.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 23 Mar 2026 15:03:07 -0700 From: Charles Perry To: CC: Charles Perry , Andrew Lunn , "David S. Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , , Subject: [PATCH net-next v2 1/2] dt-bindings: net: document Microchip PIC64-HPSC/HX MDIO controller Date: Mon, 23 Mar 2026 15:02:53 -0700 Message-ID: <20260323220254.3822444-2-charles.perry@microchip.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260323220254.3822444-1-charles.perry@microchip.com> References: <20260323220254.3822444-1-charles.perry@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This MDIO hardware is based on a Microsemi design supported in Linux by mdio-mscc-miim.c. However, The register interface is completely different with pic64hpsc, hence the need for separate documentation. The hardware supports C22 and C45. The documentation recommends an input clock of 156.25MHz and a prescaler of 39, which yields an MDIO clock of 1.95MHz. The hardware supports an interrupt pin to signal transaction completion which is not strictly needed as the software can also poll a "TRIGGER" bit for this. Signed-off-by: Charles Perry --- Notes: Changes in v2: - Make "clocks" and "interrupts" required (Andrew) - Add a default value to "clock-frequency" (Andrew) .../net/microchip,pic64hpsc-mdio.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/microchip,pic64hp= sc-mdio.yaml diff --git a/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio= .yaml b/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml new file mode 100644 index 000000000000..d690afe3d3cf --- /dev/null +++ b/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/microchip,pic64hpsc-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC64-HPSC/HX MDIO controller + +maintainers: + - Charles Perry + +description: | + Microchip PIC64-HPSC/HX SoCs have two MDIO bus controller. This MDIO bus + controller supports C22 and C45 register access. It is named "MDIO Initi= ator" + in the documentation. + +allOf: + - $ref: mdio.yaml# + +properties: + compatible: + oneOf: + - const: microchip,pic64hpsc-mdio + - items: + - const: microchip,pic64hx-mdio + - const: microchip,pic64hpsc-mdio + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + default: 2500000 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + mdio@4000C21E000 { + compatible =3D "microchip,pic64hpsc-mdio"; + reg =3D <0x400 0x0C21E000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&svc_clk>; + interrupt-parent =3D <&saplic0>; + interrupts =3D <168 IRQ_TYPE_LEVEL_HIGH>; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; + }; --=20 2.47.3 From nobody Sun Apr 5 16:27:54 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB14A38229A; Mon, 23 Mar 2026 22:03:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774303417; cv=none; b=WWMSe582GhfbPm6sWrE2nbtbDgYXVLeMgUWsC/2cuLkt+beRFkSZGb5cSbKTulGOOhCpAar/AP1CIMO2WfHjrMcLKzoXozwjBjRk2004iPinChu9n/2x3mjWxQZQfUQI4yMy61nnYtUtaIy8b1BY63v2kY4H5nDILST+VLtXQqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774303417; c=relaxed/simple; bh=UZjeVFStTf/acSEHei47GjGfs3cX+oD/NFp0EeNBCM8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=c0tlo09jorjA/lE2E54wPfe3teZYO/knJ8pbSnUL43NgxDGE1QdjsgBGySYCoFQkzB+Lc1hAs+aKHWm+25nM2qsX91Y9zbA99mb15t4+QJzSGljIdlCq758C0KbJ7p09WMpyGKVdfgQXi4YO+FVamGo+BrzpbYBwHDtjewCzVgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=P0mJSMDS; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="P0mJSMDS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1774303414; x=1805839414; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UZjeVFStTf/acSEHei47GjGfs3cX+oD/NFp0EeNBCM8=; b=P0mJSMDScqNDLBWSuJRsmeUOBS5ENZJY+Vjd7iKv7jOqt/xjXfiK15w3 C4/tfMIjUh8SuUwL7ufMM0kg5c1lT1OpWvMdFhapz5hCtY3wKdF6zr7K1 Zk08gKW7DDNcLeXlOHb6YJNI0eb4ovKEskuInXvoATsSWwrfmlosVKsif NN0NOLTmjYqarOn7CsaM0ikj+jtG4Tj6ajCe6dPaOEGwn2Cc+lhydrq2B q7CjPa3xWq+DTDguLlJzWTefbgTq1yllZCzFKcOlUUNIIo1AiuiHKDyBd ajhg8KrpQmG7XboexN/U5hvV9FVDmkuHSs4SsSP3rQo5nhf0g16UmzXBM Q==; X-CSE-ConnectionGUID: sn68fJ6gSty0fdZcGeqDMQ== X-CSE-MsgGUID: 4O6L8eGfR16+4O0pwi7Q0g== X-IronPort-AV: E=Sophos;i="6.23,138,1770620400"; d="scan'208";a="222348045" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 15:03:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Mon, 23 Mar 2026 15:03:13 -0700 Received: from bby-cbu-swbuild03.eng.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 23 Mar 2026 15:03:12 -0700 From: Charles Perry To: CC: Charles Perry , Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , , Subject: [PATCH net-next v2 2/2] net: mdio: add a driver for PIC64-HPSC/HX MDIO controller Date: Mon, 23 Mar 2026 15:02:54 -0700 Message-ID: <20260323220254.3822444-3-charles.perry@microchip.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260323220254.3822444-1-charles.perry@microchip.com> References: <20260323220254.3822444-1-charles.perry@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds an MDIO driver for PIC64-HPSC/HX. The hardware supports C22 and C45 but only C22 is implemented in this commit. This MDIO hardware is based on a Microsemi design supported in Linux by mdio-mscc-miim.c. However, The register interface is completely different with pic64hpsc, hence the need for a separate driver. The documentation recommends an input clock of 156.25MHz and a prescaler of 39, which yields an MDIO clock of 1.95MHz. The hardware supports an interrupt pin or a "TRIGGER" bit that can be polled to signal transaction completion. This commit uses polling. This was tested on Microchip HB1301 evalkit with a VSC8574 and a VSC8541. Signed-off-by: Charles Perry Reviewed-by: Maxime Chevallier --- Notes: Changes in v2: - Remove #define for unused registers (Maxime) - Add "c22" to clause 22 read/write ops (Maxime) - Remove the call to platform_set_drvdata() (Andrew) - Make the clock mandatory (Andrew) - Use 2.5MHz if no clock-frequency was specified (Andrew) - Change the error message for bad clock-frequency (Andrew) - Fix a use without initialization on bus_freq (Andrew) drivers/net/mdio/Kconfig | 7 ++ drivers/net/mdio/Makefile | 1 + drivers/net/mdio/mdio-pic64hpsc.c | 192 ++++++++++++++++++++++++++++++ 3 files changed, 200 insertions(+) create mode 100644 drivers/net/mdio/mdio-pic64hpsc.c diff --git a/drivers/net/mdio/Kconfig b/drivers/net/mdio/Kconfig index 44380378911b..7bdba8c3ddef 100644 --- a/drivers/net/mdio/Kconfig +++ b/drivers/net/mdio/Kconfig @@ -146,6 +146,13 @@ config MDIO_OCTEON buses. It is required by the Octeon and ThunderX ethernet device drivers on some systems. =20 +config MDIO_PIC64HPSC + tristate "PIC64-HPSC/HX MDIO interface support" + depends on HAS_IOMEM && OF_MDIO + help + This driver supports the MDIO interface found on the PIC64-HPSC/HX + SoCs. + config MDIO_IPQ4019 tristate "Qualcomm IPQ4019 MDIO interface support" depends on HAS_IOMEM && OF_MDIO diff --git a/drivers/net/mdio/Makefile b/drivers/net/mdio/Makefile index fbec636700e7..048586746026 100644 --- a/drivers/net/mdio/Makefile +++ b/drivers/net/mdio/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_MDIO_MOXART) +=3D mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) +=3D mdio-mscc-miim.o obj-$(CONFIG_MDIO_MVUSB) +=3D mdio-mvusb.o obj-$(CONFIG_MDIO_OCTEON) +=3D mdio-octeon.o +obj-$(CONFIG_MDIO_PIC64HPSC) +=3D mdio-pic64hpsc.o obj-$(CONFIG_MDIO_REALTEK_RTL9300) +=3D mdio-realtek-rtl9300.o obj-$(CONFIG_MDIO_REGMAP) +=3D mdio-regmap.o obj-$(CONFIG_MDIO_SUN4I) +=3D mdio-sun4i.o diff --git a/drivers/net/mdio/mdio-pic64hpsc.c b/drivers/net/mdio/mdio-pic6= 4hpsc.c new file mode 100644 index 000000000000..0ca6f5af5396 --- /dev/null +++ b/drivers/net/mdio/mdio-pic64hpsc.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Microchip PIC64-HPSC/HX MDIO controller driver + * + * Copyright (c) 2026 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MDIO_REG_PRESCALER 0x20 +#define MDIO_CFG_PRESCALE_MASK GENMASK(7, 0) + +#define MDIO_REG_FRAME_CFG_1 0x24 +#define MDIO_WDATA_MASK GENMASK(15, 0) + +#define MDIO_REG_FRAME_CFG_2 0x28 +#define MDIO_TRIGGER_BIT BIT(31) +#define MDIO_REG_DEV_ADDR_MASK GENMASK(20, 16) +#define MDIO_PHY_PRT_ADDR_MASK GENMASK(8, 4) +#define MDIO_OPERATION_MASK GENMASK(3, 2) +#define MDIO_START_OF_FRAME_MASK GENMASK(1, 0) + +/* Possible value of MDIO_OPERATION_MASK */ +#define MDIO_OPERATION_WRITE BIT(0) +#define MDIO_OPERATION_READ BIT(1) + +#define MDIO_REG_FRAME_STATUS 0x2C +#define MDIO_READOK_BIT BIT(24) +#define MDIO_RDATA_MASK GENMASK(15, 0) + +struct pic64hpsc_mdio_dev { + void __iomem *regs; +}; + +static int pic64hpsc_mdio_wait_trigger(struct mii_bus *bus) +{ + struct pic64hpsc_mdio_dev *priv =3D bus->priv; + u32 val; + int ret; + + /* The MDIO_TRIGGER bit returns 0 when a transaction has completed. */ + ret =3D readl_poll_timeout(priv->regs + MDIO_REG_FRAME_CFG_2, val, + !(val & MDIO_TRIGGER_BIT), 50, 10000); + + if (ret < 0) + dev_dbg(&bus->dev, "TRIGGER bit timeout: %x\n", val); + + return ret; +} + +static int pic64hpsc_mdio_c22_read(struct mii_bus *bus, int mii_id, int re= gnum) +{ + struct pic64hpsc_mdio_dev *priv =3D bus->priv; + u32 val; + int ret; + + ret =3D pic64hpsc_mdio_wait_trigger(bus); + if (ret) + return ret; + + writel(MDIO_TRIGGER_BIT | FIELD_PREP(MDIO_REG_DEV_ADDR_MASK, regnum) | + FIELD_PREP(MDIO_PHY_PRT_ADDR_MASK, mii_id) | + FIELD_PREP(MDIO_OPERATION_MASK, MDIO_OPERATION_READ) | + FIELD_PREP(MDIO_START_OF_FRAME_MASK, 1), + priv->regs + MDIO_REG_FRAME_CFG_2); + + ret =3D pic64hpsc_mdio_wait_trigger(bus); + if (ret) + return ret; + + val =3D readl(priv->regs + MDIO_REG_FRAME_STATUS); + + /* The MDIO_READOK is a 1-bit value reflecting the inverse of the MDIO + * bus value captured during the 2nd TA cycle. A PHY/Port should drive + * the MDIO bus with a logic 0 on the 2nd TA cycle, however, the + * PHY/Port could optionally drive a logic 1, to communicate a read + * failure. This feature is optional, not defined by the 802.3 standard + * and not supported in standard external PHYs. + */ + if (!(bus->phy_ignore_ta_mask & 1 << mii_id) && + !FIELD_GET(MDIO_READOK_BIT, val)) { + dev_dbg(&bus->dev, "READOK bit cleared\n"); + return -EIO; + } + + ret =3D FIELD_GET(MDIO_RDATA_MASK, val); + + return ret; +} + +static int pic64hpsc_mdio_c22_write(struct mii_bus *bus, int mii_id, int r= egnum, + u16 value) +{ + struct pic64hpsc_mdio_dev *priv =3D bus->priv; + int ret; + + ret =3D pic64hpsc_mdio_wait_trigger(bus); + if (ret < 0) + return ret; + + writel(FIELD_PREP(MDIO_WDATA_MASK, value), + priv->regs + MDIO_REG_FRAME_CFG_1); + + writel(MDIO_TRIGGER_BIT | FIELD_PREP(MDIO_REG_DEV_ADDR_MASK, regnum) | + FIELD_PREP(MDIO_PHY_PRT_ADDR_MASK, mii_id) | + FIELD_PREP(MDIO_OPERATION_MASK, MDIO_OPERATION_WRITE) | + FIELD_PREP(MDIO_START_OF_FRAME_MASK, 1), + priv->regs + MDIO_REG_FRAME_CFG_2); + + return 0; +} + +static int pic64hpsc_mdio_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct pic64hpsc_mdio_dev *priv; + struct mii_bus *bus; + unsigned long rate; + struct clk *clk; + u32 bus_freq; + u32 div; + int ret; + + bus =3D devm_mdiobus_alloc_size(dev, sizeof(*priv)); + if (!bus) + return -ENOMEM; + + priv =3D bus->priv; + + priv->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + bus->name =3D KBUILD_MODNAME; + bus->read =3D pic64hpsc_mdio_c22_read; + bus->write =3D pic64hpsc_mdio_c22_write; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); + bus->parent =3D dev; + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + if (of_property_read_u32(np, "clock-frequency", &bus_freq)) + bus_freq =3D 2500000; + + rate =3D clk_get_rate(clk); + + div =3D DIV_ROUND_UP(rate, 2 * bus_freq) - 1; + if (div =3D=3D 0 || div & ~MDIO_CFG_PRESCALE_MASK) { + dev_err(dev, "MDIO clock-frequency out of range\n"); + return -EINVAL; + } + + dev_dbg(dev, "rate=3D%lu bus_freq=3D%u real_bus_freq=3D%lu div=3D%u\n", r= ate, + bus_freq, rate / (2 * (1 + div)), div); + writel(div, priv->regs + MDIO_REG_PRESCALER); + + ret =3D devm_of_mdiobus_register(dev, bus, np); + if (ret) { + dev_err(dev, "Cannot register MDIO bus (%d)\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id pic64hpsc_mdio_match[] =3D { + { .compatible =3D "microchip,pic64hpsc-mdio" }, + {} +}; +MODULE_DEVICE_TABLE(of, pic64hpsc_mdio_match); + +static struct platform_driver pic64hpsc_mdio_driver =3D { + .probe =3D pic64hpsc_mdio_probe, + .driver =3D { + .name =3D KBUILD_MODNAME, + .of_match_table =3D pic64hpsc_mdio_match, + }, +}; +module_platform_driver(pic64hpsc_mdio_driver); + +MODULE_AUTHOR("Charles Perry "); +MODULE_DESCRIPTION("Microchip PIC64-HPSC/HX MDIO driver"); +MODULE_LICENSE("GPL"); --=20 2.47.3