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charset="utf-8" From: Nick Hawkins Add the HPE GSC ARM64 BMC SoC compatibles to the existing hpe,gxp.yaml binding. The initial board compatible is hpe,gsc-dl340gen12 for the DL340 Gen12 server platform. Signed-off-by: Nick Hawkins --- Documentation/devicetree/bindings/arm/hpe,gxp.yaml | 7 ++++++- MAINTAINERS | 7 +++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml b/Documenta= tion/devicetree/bindings/arm/hpe,gxp.yaml index 224bbcb93f95..6f057cd58571 100644 --- a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml +++ b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/hpe,gxp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: HPE BMC GXP platforms +title: HPE BMC GXP and GSC platforms =20 maintainers: - Nick Hawkins @@ -18,6 +18,11 @@ properties: - enum: - hpe,gxp-dl360gen10 - const: hpe,gxp + - description: GSC Based Boards + items: + - enum: + - hpe,gsc-dl340gen12 + - const: hpe,gsc =20 required: - compatible diff --git a/MAINTAINERS b/MAINTAINERS index 2265e2c9bfbe..33e4357f9011 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2859,6 +2859,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git= /kristoffer/linux-hpc.git F: arch/arm/mach-sa1100/include/mach/jornada720.h F: arch/arm/mach-sa1100/jornada720.c =20 +ARM64/HPE GSC ARCHITECTURE +M: Nick Hawkins +S: Maintained +F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml +F: arch/arm64/Kconfig.platforms +F: arch/arm64/boot/dts/hpe/ + ARM/HPE GXP ARCHITECTURE M: Jean-Marie Verdun M: Nick Hawkins --=20 2.34.1 From nobody Sun Apr 5 16:22:54 2026 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6909B34250E; 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charset="utf-8" From: Nick Hawkins Add the ARCH_HPE menuconfig group and ARCH_HPE_GSC config for the HPE GSC ARM64 BMC SoC. Signed-off-by: Nick Hawkins --- arch/arm64/Kconfig.platforms | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 54eb1d7fd419..4bbc27bb9b7b 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -168,6 +168,29 @@ config ARCH_HISI help This enables support for Hisilicon ARMv8 SoC family =20 + +menuconfig ARCH_HPE + bool "HPE SoC Support" + help + This enables support for HPE ARM-based SoC chips used + on HPE servers. HPE SoCs serve as the Baseboard + Management Controller (BMC) providing out-of-band server + management. + +if ARCH_HPE + +config ARCH_HPE_GSC + bool "HPE GSC SoC" + select PINCTRL + select GENERIC_IRQ_CHIP + select CLKSRC_MMIO + help + Support for the HPE GSC ARM64 BMC SoC used on HPE servers. + The GSC provides hardware management, power control, remote + access, and server health monitoring capabilities for HPE + Gen12 and later server platforms. + +endif config ARCH_KEEMBAY bool "Keem Bay SoC" help --=20 2.34.1 From nobody Sun Apr 5 16:22:54 2026 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D11B32D6E64; Mon, 23 Mar 2026 19:42:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.143.35 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" From: Nick Hawkins Add SoC-level DTSI for the HPE GSC ARM64 BMC SoC, covering the CPU cluster, GIC v3 interrupt controller, ARM64 generic timer, and console UART. Add the board-level DTS for the HPE DL340 Gen12, which includes gsc.dtsi and adds memory and chosen nodes. Signed-off-by: Nick Hawkins --- arch/arm64/boot/dts/hpe/Makefile | 2 + arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts | 18 ++++ arch/arm64/boot/dts/hpe/gsc.dtsi | 106 +++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 arch/arm64/boot/dts/hpe/Makefile create mode 100644 arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts create mode 100644 arch/arm64/boot/dts/hpe/gsc.dtsi diff --git a/arch/arm64/boot/dts/hpe/Makefile b/arch/arm64/boot/dts/hpe/Mak= efile new file mode 100644 index 000000000000..804f7c54e9b6 --- /dev/null +++ b/arch/arm64/boot/dts/hpe/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_HPE_GSC) +=3D gsc-dl340gen12.dtb diff --git a/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts b/arch/arm64/boot/d= ts/hpe/gsc-dl340gen12.dts new file mode 100644 index 000000000000..42cfeac99029 --- /dev/null +++ b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "gsc.dtsi" + +/ { + compatible =3D "hpe,gsc-dl340gen12", "hpe,gsc"; + model =3D "HPE ProLiant DL340 Gen12"; + + chosen { + stdout-path =3D &uartc; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x00000000 0x40000000>; + }; +}; diff --git a/arch/arm64/boot/dts/hpe/gsc.dtsi b/arch/arm64/boot/dts/hpe/gsc= .dtsi new file mode 100644 index 000000000000..3433c4a18512 --- /dev/null +++ b/arch/arm64/boot/dts/hpe/gsc.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE GSC + */ + +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0xa0008048>; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <1>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0xa0008048>; + }; + }; + + clocks { + osc: osc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "osc"; + clock-frequency =3D <33333333>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + interrupt-parent =3D <&gic>; + }; + + ahb: ahb@80000000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0x80000000 0x80000000>; + ranges; + + gic: gic@ce000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + redistributor-stride =3D <0x0 0x20000>; + #redistributor-regions =3D <1>; + reg =3D <0xce000000 0x10000>, + <0xce060000 0x40000>, + <0xce200000 0x40000>; + }; + + uartc: serial@c00000f0 { + compatible =3D "ns16550a"; + reg =3D <0xc00000f0 0x8>; + interrupts =3D <0 19 4>; + interrupt-parent =3D <&gic>; + clock-frequency =3D <1846153>; + reg-shift =3D <0>; + }; + + uarta: serial@c00000e0 { + compatible =3D "ns16550a"; + reg =3D <0xc00000e0 0x8>; + interrupts =3D <0 17 4>; + interrupt-parent =3D <&gic>; + clock-frequency =3D <1846153>; + reg-shift =3D <0>; + }; + + uartb: serial@c00000e8 { + compatible =3D "ns16550a"; + reg =3D <0xc00000e8 0x8>; + interrupts =3D <0 18 4>; + interrupt-parent =3D <&gic>; + clock-frequency =3D <1846153>; + reg-shift =3D <0>; + }; + + uarte: serial@c00003e0 { + compatible =3D "ns16550a"; + reg =3D <0xc00003e0 0x8>; + interrupts =3D <0 12 4>; + interrupt-parent =3D <&gic>; + clock-frequency =3D <1846153>; + reg-shift =3D <0>; + }; + }; +}; --=20 2.34.1