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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 397204126F88; Mon, 23 Mar 2026 19:48:23 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com, Frank.Li@kernel.org Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, Jun Guo Subject: [PATCH v4 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies Date: Mon, 23 Mar 2026 19:48:20 +0800 Message-Id: <20260323114822.1925869-2-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260323114822.1925869-1-jun.guo@cixtech.com> References: <20260323114822.1925869-1-jun.guo@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB87:EE_|TY2PPF7E205D1F6:EE_ X-MS-Office365-Filtering-Correlation-Id: 158d76f5-c817-4f4d-6a3b-08de88d217ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700016|1800799024|82310400026|56012099003|22082099003|18002099003|921020; X-Microsoft-Antispam-Message-Info: +4vQmSNEUsJpwjQkVw/da556zt7xu3bAylvwb9SV4ch34XKXATKkPudvLmJf0agaK+F4YlvIEXdDnBCRTTmBmG28O/gBDAzz4D+MieUNRNdK6OfcFi2m0Zcz3oeQwBp6Q/AbAAMzFCVof06bxjZBVmW8zrThSu6gMT9AN+QOoiwIi+xCxdiQlp8sV+uQrKOmAdUnnqU1EUzRztR5NYemEZGnp2CdrNCHuizEG5H+IAtPs62uUt4OpXfsN1NR4cIjC8C5qKKTbd+LZJ8NPZgpk8W1pYv7jGhu/9Xs8xwjNtyonbgFapqwifyejgqS6tutOg7C7xfFNYUYEee8mhJwBYIT226LuKxjGco7KflDEguw6musNUtOtAQRkLQhbd1gzh4Wdk3hThYlMrwCGFCMBenLVkxNehNiFYCO8y2PTLCCb3WxMSBifYOHKTxV1cNkc0NyJujpPcT/qZmx2t7AOsoEV/xAM31BFhuL8eI5eLM7oy4c/s6ivci/TSGKqmRHBlshqbDG98cORHV27WRYeYYyT73GyvYKMvRn8fg+JRZUnLwHfObEB5M4yQ4FmJ4K8rxtoisti727QrtZFRvZiqVIM5n5/bKRVjpUV27Fdp22eBYBsWMtYM2PV6G/YN5gPx8U9+0F4qUionS56kSSJlQlxlQMXmXvfqA2OVClvhbm6vfEVfPQn4I0ipfyQXqwlKmc0g72jJ3PvrnK13oV5OHr1xMAR7xUr32femJ5y4dT++ZUGBesmsI+8GtdwAFw/PRR2ZBr9s4zt4KHwAfRtUep2/oJ1nVtOQv88WqbSUTcFEdSXnOX1UW9SuYmyFbH X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700016)(1800799024)(82310400026)(56012099003)(22082099003)(18002099003)(921020);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lzsl7ugjDZ293ozU2gm8WHR7aXgNip/RKR47Ep489oFvv6IkiAe6f2+JI1fwJ14bmXqX9qOIA5f6ZeedpJmj/ZGLdINz2ocmvzp0e7NOukjWfzE/pgUoxzNEEf3aFjewsk3Q02GxFag6GsfD2btN1dzde/uWbwPhEpXPGysjUes25aTamIrPP19iE68C1+AqY3lll8jPPmucSDHxrnDpyCqeZomMtNNscjQMuQNUFAsqSAohn5za9KEeEA8lUmj4m7ipwwz/Rq3Nd5sKDmNKhdfD7gJw7bJM0KdPXfyz4bS5f7qen8H2KUOhYupkK89ZdAqaShdfA9E4jeqP/tsUp94bP9BwTwdshcXWgdmyf15Tie0iMj1nmLFInLJcrJ8eH7aFKTGfP0LiJMlSsrjRlcwkmt06d8Gnevho/khSItEOVzUQpPXcxm7CcxgkL6eb X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2026 11:48:25.2284 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 158d76f5-c817-4f4d-6a3b-08de88d217ac X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB87.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY2PPF7E205D1F6 Content-Type: text/plain; charset="utf-8" Update the DMA-350 DT binding to match the current driver behavior. Allow both: - "arm,dma-350" as the generic compatible, and - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage. Also document interrupt topology variants supported by hardware integration: - one combined interrupt for all channels, or - one interrupt per channel (up to 8 channels). Assisted-by: Cursor: GPT-5.3-Codex Signed-off-by: Jun Guo --- .../devicetree/bindings/dma/arm,dma-350.yaml | 34 +++++++++++++------ 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Docum= entation/devicetree/bindings/dma/arm,dma-350.yaml index 429f682f15d8..47091614d1b4 100644 --- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml +++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml @@ -14,7 +14,14 @@ allOf: =20 properties: compatible: - const: arm,dma-350 + description: + Use "arm,dma-350" for generic integration. A SoC-specific + compatible may be listed first, followed by "arm,dma-350". + oneOf: + - const: arm,dma-350 + - items: + - const: cix,sky1-dma-350 + - const: arm,dma-350 =20 reg: items: @@ -22,15 +29,22 @@ properties: =20 interrupts: minItems: 1 - items: - - description: Channel 0 interrupt - - description: Channel 1 interrupt - - description: Channel 2 interrupt - - description: Channel 3 interrupt - - description: Channel 4 interrupt - - description: Channel 5 interrupt - - description: Channel 6 interrupt - - description: Channel 7 interrupt + maxItems: 8 + description: + Either one interrupt per channel (8 interrupts), or one + combined interrupt for all channels. + oneOf: + - items: + - description: Channel 0 interrupt + - description: Channel 1 interrupt + - description: Channel 2 interrupt + - description: Channel 3 interrupt + - description: Channel 4 interrupt + - description: Channel 5 interrupt + - description: Channel 6 interrupt + - description: Channel 7 interrupt + - items: + - description: Combined interrupt shared by all channels =20 "#dma-cells": const: 1 --=20 2.34.1 From nobody Fri Apr 3 20:53:04 2026 Received: from OS8PR02CU002.outbound.protection.outlook.com (mail-japanwestazon11022128.outbound.protection.outlook.com [40.107.75.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDE4239A05D; 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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id B62BC4126F95; Mon, 23 Mar 2026 19:48:23 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com, Frank.Li@kernel.org Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, Jun Guo Subject: [PATCH v4 2/3] dma: arm-dma350: support combined IRQ mode with runtime IRQ topology detection Date: Mon, 23 Mar 2026 19:48:21 +0800 Message-Id: <20260323114822.1925869-3-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260323114822.1925869-1-jun.guo@cixtech.com> References: <20260323114822.1925869-1-jun.guo@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB89:EE_|TYSPR06MB6795:EE_ X-MS-Office365-Filtering-Correlation-Id: dff63033-a2d1-4271-fa76-08de88d217a9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700016|82310400026|1800799024|921020|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: dIKTxkL/w9BJOHfzdl/G7Q92ztBiu1Y1KcaD6OdesTKdPTBKQpiA/H7Vek3eQNq6oEahypSsQmOkTVjfRFlTvaJJCTBm5tTrZGFQIwo5zvkZcdvih4oSgIIwiHbLPRQR7WOPZ/+Xl0io3HJDA+IY8Lg91VhJdRObczMP9j0ekofttqPpOcFVwEjE2JG0IznpPyCjHngJxG8FDP6LxrWgZbbgIiXjPCwa6EgJf8n4bpP/td0IRFGp7bi7pEWEQXjm6n1yDNqq3KW4IVHfez21y8Rcz/tM7hFiU9dRlka+KKF4G2Hsr/f4cbmCYY5l4DeoF0hunkvBl7bNLLixqjVuknBmYskRFQMMgN7BeMZWcEIksZlrGaGUX7BmHwsAO3hnv0vDuccEAB02A+5jUMBIRkmJGonzI6K6+nRlz+xBDs8zpsX9s5fF6SKtWgCbwATkmniOMXCUI4Vov2qauN3tTN7+QzCCgu1P8hd31jGLK8lYQZDvNuJCMS0tLG+FUjkEOE+/2xoQz4DuV1sFC/HReob6yqmVsC8RxMpeGqqmnDhrA4Q+y7Q3Tb2eKIuERGR4I4Zd1RdK6oN6A7geBjdbV4NqM4Jy648PSKAhvlXRa3XEhWUV5vVmejz6ij/gUSjGhGew0xdLj14ooA+rggbK9r1xFQKgIok2wPSeoJ49f8RIorsb5344xZybJcOcu0kZUIfXKVHYnSA/bz0DxILIRpP9aPt7FVj533nhqSNssx/geS//w0eVmkb57yH6H/o9LcNU1Nt0ojyd7byWoCDHBwpiwOHYJxz++dqkES+MfJ7iBXFsVmLjp3hCqj8rk8wV X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700016)(82310400026)(1800799024)(921020)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: irxcDUwL30J4flLBn+Pk4ACc8kA7RSE1Qbb/SNWH4BGWdEHzA7/a23W0G8s24KlJ68eSQehr4IWzR5f/luc2V7EpVYx0WafcXDhImNtE4wzZF+aOCvgEyUavjr/cXv4UaLPdJVuvWEzUc9SzFiRtSQiudDdVMZhFqmV2sje1uev05DNwGIhqZKHTOxb/4tpREAe0pqehAoESU5oB68gG2l+NRjlkp28/APcMici7iuL43WTCZwCMG9L4d5XXlLjV63EmJCT7xHg+iyx5df5o5QlSPjDb0BIrN+YNqQqd3oCspGw6Q0pZXvzW5wpmx2dnEqYFGN31m55rWU0DiIAciJbU4HR8bijbJJx7XLJHiQxmP2nMnRj+Lo2AHkSMDP7X6RTKbSJopAXyoqcCbCJbidlf3RfIvIsbQ+DbCaDO1q5f8eCjrOZSd0epnH/v5Tn9 X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2026 11:48:25.2268 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dff63033-a2d1-4271-fa76-08de88d217a9 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB89.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB6795 Content-Type: text/plain; charset="utf-8" DMA-350 can be integrated with either per-channel IRQ lines or a single combined IRQ line. Add support for both layouts in a unified way. Detect IRQ topology at probe time via platform_irq_count(), then: - request one global IRQ and enable DMANSECCTRL.INTREN_ANYCHINTR for combined mode, or - request per-channel IRQs for channel mode. Refactor IRQ completion/error handling into a shared channel handler used by both global and per-channel IRQ paths, and guard against IRQs arriving without an active descriptor. Assisted-by: Cursor: GPT-5.3-Codex Signed-off-by: Jun Guo --- drivers/dma/arm-dma350.c | 165 +++++++++++++++++++++++++++++++++------ 1 file changed, 139 insertions(+), 26 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 84220fa83029..2cf6f783b44f 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -14,6 +14,7 @@ #include "virt-dma.h" =20 #define DMAINFO 0x0f00 +#define DRIVER_NAME "arm-dma350" =20 #define DMA_BUILDCFG0 0xb0 #define DMA_CFG_DATA_WIDTH GENMASK(18, 16) @@ -142,6 +143,9 @@ #define LINK_LINKADDR BIT(30) #define LINK_LINKADDRHI BIT(31) =20 +/* DMA NONSECURE CONTROL REGISTER */ +#define DMANSECCTRL 0x20c +#define INTREN_ANYCHINTR_EN BIT(0) =20 enum ch_ctrl_donetype { CH_CTRL_DONETYPE_NONE =3D 0, @@ -192,6 +196,7 @@ struct d350_chan { =20 struct d350 { struct dma_device dma; + void __iomem *base; int nchan; int nreq; struct d350_chan channels[] __counted_by(nchan); @@ -461,18 +466,40 @@ static void d350_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&dch->vc.lock, flags); } =20 -static irqreturn_t d350_irq(int irq, void *data) +static void d350_handle_chan_irq(struct d350_chan *dch, struct device *dev, + int chan_id, u32 ch_status) { - struct d350_chan *dch =3D data; - struct device *dev =3D dch->vc.chan.device->dev; - struct virt_dma_desc *vd =3D &dch->desc->vd; - u32 ch_status; + struct virt_dma_desc *vd; + bool intr_done =3D ch_status & CH_STAT_INTR_DONE; + bool intr_err =3D ch_status & CH_STAT_INTR_ERR; =20 - ch_status =3D readl(dch->base + CH_STATUS); - if (!ch_status) - return IRQ_NONE; + if (!intr_done && !intr_err) { + if (chan_id >=3D 0) + dev_warn(dev, "Channel %d unexpected IRQ: 0x%08x\n", + chan_id, ch_status); + else + dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status); + writel_relaxed(ch_status, dch->base + CH_STATUS); + return; + } + + writel_relaxed(ch_status, dch->base + CH_STATUS); + + spin_lock(&dch->vc.lock); + if (!dch->desc) { + if (chan_id >=3D 0) + dev_warn(dev, + "Channel %d IRQ without active descriptor: 0x%08x\n", + chan_id, ch_status); + else + dev_warn(dev, "IRQ without active descriptor: 0x%08x\n", + ch_status); + spin_unlock(&dch->vc.lock); + return; + } =20 - if (ch_status & CH_STAT_INTR_ERR) { + vd =3D &dch->desc->vd; + if (intr_err) { u32 errinfo =3D readl_relaxed(dch->base + CH_ERRINFO); =20 if (errinfo & (CH_ERRINFO_AXIRDPOISERR | CH_ERRINFO_AXIRDRESPERR)) @@ -483,14 +510,10 @@ static irqreturn_t d350_irq(int irq, void *data) vd->tx_result.result =3D DMA_TRANS_ABORTED; =20 vd->tx_result.residue =3D d350_get_residue(dch); - } else if (!(ch_status & CH_STAT_INTR_DONE)) { - dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status); } - writel_relaxed(ch_status, dch->base + CH_STATUS); =20 - spin_lock(&dch->vc.lock); vchan_cookie_complete(vd); - if (ch_status & CH_STAT_INTR_DONE) { + if (intr_done) { dch->status =3D DMA_COMPLETE; dch->residue =3D 0; d350_start_next(dch); @@ -499,6 +522,44 @@ static irqreturn_t d350_irq(int irq, void *data) dch->residue =3D vd->tx_result.residue; } spin_unlock(&dch->vc.lock); +} + +static irqreturn_t d350_global_irq(int irq, void *data) +{ + struct d350 *dmac =3D (struct d350 *)data; + irqreturn_t ret =3D IRQ_NONE; + int i; + + (void)irq; + + for (i =3D 0; i < dmac->nchan; i++) { + struct d350_chan *dch =3D &dmac->channels[i]; + u32 ch_status; + + ch_status =3D readl(dch->base + CH_STATUS); + if (!ch_status) + continue; + + ret =3D IRQ_HANDLED; + d350_handle_chan_irq(dch, dmac->dma.dev, i, ch_status); + } + + return ret; +} + +static irqreturn_t d350_channel_irq(int irq, void *data) +{ + struct d350_chan *dch =3D data; + struct device *dev =3D dch->vc.chan.device->dev; + u32 ch_status; + + (void)irq; + + ch_status =3D readl(dch->base + CH_STATUS); + if (!ch_status) + return IRQ_NONE; + + d350_handle_chan_irq(dch, dev, -1, ch_status); =20 return IRQ_HANDLED; } @@ -506,10 +567,18 @@ static irqreturn_t d350_irq(int irq, void *data) static int d350_alloc_chan_resources(struct dma_chan *chan) { struct d350_chan *dch =3D to_d350_chan(chan); - int ret =3D request_irq(dch->irq, d350_irq, IRQF_SHARED, - dev_name(&dch->vc.chan.dev->device), dch); - if (!ret) - writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN); + int ret =3D 0; + + if (dch->irq >=3D 0) { + ret =3D request_irq(dch->irq, d350_channel_irq, IRQF_SHARED, + dev_name(&dch->vc.chan.dev->device), dch); + if (ret) { + dev_err(chan->device->dev, "Failed to request IRQ %d\n", dch->irq); + return ret; + } + } + + writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN); =20 return ret; } @@ -519,18 +588,21 @@ static void d350_free_chan_resources(struct dma_chan = *chan) struct d350_chan *dch =3D to_d350_chan(chan); =20 writel_relaxed(0, dch->base + CH_INTREN); - free_irq(dch->irq, dch); + if (dch->irq >=3D 0) { + free_irq(dch->irq, dch); + dch->irq =3D -EINVAL; + } vchan_free_chan_resources(&dch->vc); } =20 static int d350_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct d350 *dmac; + struct d350 *dmac =3D NULL; void __iomem *base; u32 reg; - int ret, nchan, dw, aw, r, p; - bool coherent, memset; + int ret, nchan, dw, aw, r, p, irq_count; + bool coherent, memset, combined_irq; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -556,6 +628,7 @@ static int d350_probe(struct platform_device *pdev) return -ENOMEM; =20 dmac->nchan =3D nchan; + dmac->base =3D base; =20 reg =3D readl_relaxed(base + DMAINFO + DMA_BUILDCFG1); dmac->nreq =3D FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg); @@ -582,12 +655,46 @@ static int d350_probe(struct platform_device *pdev) dmac->dma.device_issue_pending =3D d350_issue_pending; INIT_LIST_HEAD(&dmac->dma.channels); =20 + irq_count =3D platform_irq_count(pdev); + if (irq_count < 0) + return dev_err_probe(dev, irq_count, + "Failed to count interrupts\n"); + + if (irq_count =3D=3D 1) { + combined_irq =3D true; + } else if (irq_count >=3D nchan) { + combined_irq =3D false; + } else { + return dev_err_probe(dev, -EINVAL, + "Invalid IRQ count %d for %d channels\n", + irq_count, nchan); + } + + if (combined_irq) { + int host_irq =3D platform_get_irq(pdev, 0); + + if (host_irq < 0) + return dev_err_probe(dev, host_irq, + "Failed to get IRQ\n"); + + ret =3D devm_request_irq(&pdev->dev, host_irq, d350_global_irq, + IRQF_SHARED, DRIVER_NAME, dmac); + if (ret) + return dev_err_probe( + dev, ret, + "Failed to request the combined IRQ %d\n", + host_irq); + /* Combined Non-Secure Channel Interrupt Enable */ + writel_relaxed(INTREN_ANYCHINTR_EN, dmac->base + DMANSECCTRL); + } + /* Would be nice to have per-channel caps for this... */ memset =3D true; for (int i =3D 0; i < nchan; i++) { struct d350_chan *dch =3D &dmac->channels[i]; =20 dch->base =3D base + DMACH(i); + dch->irq =3D -EINVAL; writel_relaxed(CH_CMD_CLEAR, dch->base + CH_CMD); =20 reg =3D readl_relaxed(dch->base + CH_BUILDCFG1); @@ -595,10 +702,15 @@ static int d350_probe(struct platform_device *pdev) dev_warn(dev, "No command link support on channel %d\n", i); continue; } - dch->irq =3D platform_get_irq(pdev, i); - if (dch->irq < 0) - return dev_err_probe(dev, dch->irq, - "Failed to get IRQ for channel %d\n", i); + + if (!combined_irq) { + dch->irq =3D platform_get_irq(pdev, i); + if (dch->irq < 0) + return dev_err_probe( + dev, dch->irq, + "Failed to get IRQ for channel %d\n", + i); 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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 3DDC34126F96; Mon, 23 Mar 2026 19:48:24 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com, Frank.Li@kernel.org Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, Jun Guo Subject: [PATCH v4 3/3] arm64: dts: cix: add DT nodes for DMA Date: Mon, 23 Mar 2026 19:48:22 +0800 Message-Id: <20260323114822.1925869-4-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260323114822.1925869-1-jun.guo@cixtech.com> References: <20260323114822.1925869-1-jun.guo@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CA:EE_|PS1PPF77E02AF72:EE_ X-MS-Office365-Filtering-Correlation-Id: d939c5c7-7c54-4496-c8d8-08de88d21846 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|7416014|376014|921020|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: tfhsB0zPyWZXb/xsulKcB443iEVVMGr6pIat4QvXH0XBAfylIRLS2QZjv2ro5ol7Sez5SVSUAwRsczg5oDhLQTQWndzbARXHScRO53q5T8UFEwstB8tOFQP8bFDJpy15exMIqxG4AyENBkDu4DpAuw32IaMK/pfXiVfiSaWuV2ePVU6y5ZMo+PZI/IBREdvUJXRy3HfG5AddHg/uocKSmfRSQa9c1xqOg9GMpxYbnhwrgA8gdURys19V6ggX/kRdWeSLNo+LJQPwYT0MW/TiNom+EuXBD4FFS0Vjdcx778/c2GpsUAaHjNXO2BhmCGhmQpe1UkdBBDTXCZcFVP0/f+ISwzZr74dJcgUOBUPQm7NfICaX0Ul7RTHIfzPbprr25AuELXloGZ27bSd3OboHsALUAfZLiiKoBUFwG4X1VMrGmlDP92yOaDw962aeHS57nDvxiDnVPcto4gjMh2vyghq3HAF2UMoQ9gt+oXhXGq7qf+T03Fczco+e/iwhYgc3bQRejbRpdBbycFy+dnCBKSIPmKRtVevS9KWF6X1/hPoHpn6ZVUVXmOd6AS9yYYMnHzGZPPdUzaoOqMhL2jWdb+n347Heum8IuK0LvdW6MouPxa5DmWqw/HZbfOm71IkEVnlZtuE0c77Rq0WlRc7UmuKhkowdgr9+4X/MJsJAJ+H85ZHw7igm40XM99zV8RA150fs9ESWdaSWYm5AaGw1XEXBMnW3s0x7qAedBpjcDIluSJ76+SYiVl2J00fjehkTlfZlcTu4rHo2RPjUek/aSgzHILEztv1HLgHJZUkg7KzE8kDw4jpoMuAWr3Tz3Jjr X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(7416014)(376014)(921020)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tQn6pb33BV+ONzL1M4q+RrKc86iCZTnKb3PPiF7pZhe16wi7V9tikxybNQqzYH3/djKST+pSKGQYihhn2F5o2luUtLvVt38QIIYsTbWdYuh52zRn20wNCbHIedgZ7jJaQnfWpgqomEbDOPkxLsp/Ehn5mfy6QIVXMhFQb24tPf4KvAk2MS1UAHSVTwl7A/UQLX9LkXP2KvfXvc75GXxpKXcy5p4uYVNySMG/DdoyvJ4K+LKQ7yS/a9ZBlQuyXZ1UlfbQj4n2vXLWZQJ1UThR2MYwd4tNjOwWKqLiKpLOG5IVfxHj0u7CK8dB/RQrevSwyBFoVUjYv5eTVJWupbFQEwLyJEgbGkPc/EC00XxLT/pAm/M0ROtJ8jXsBeGDMVJM52ve5wG7Ecjnw+PCd0ZI7AP8rWxHYCnmMF3Wt7XoE376cBLELBHf0KcTCt54TJ2u X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2026 11:48:26.2477 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d939c5c7-7c54-4496-c8d8-08de88d21846 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CA.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PS1PPF77E02AF72 Content-Type: text/plain; charset="utf-8" Add the device tree node for the dma controller of the CIX SKY1 SoC. Signed-off-by: Jun Guo --- arch/arm64/boot/dts/cix/sky1.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 210739beac6d..1185c99d8d9d 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -480,6 +480,13 @@ iomuxc: pinctrl@4170000 { reg =3D <0x0 0x04170000 0x0 0x1000>; }; =20 + fch_dmac: dma-controller@4190000 { + compatible =3D "cix,sky1-dma-350", "arm,dma-350"; + reg =3D <0x0 0x4190000 0x0 0x10000>; + interrupts =3D ; + #dma-cells =3D <1>; + }; + mbox_ap2se: mailbox@5060000 { compatible =3D "cix,sky1-mbox"; reg =3D <0x0 0x05060000 0x0 0x10000>; --=20 2.34.1