From nobody Fri Apr 3 22:19:44 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ED07A396B7F; Mon, 23 Mar 2026 11:02:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263727; cv=none; b=PvpDKFOyHEhymusCKePCvPYXJPZ0Ab0geXzfW/xgyhI8khCyeWHROG3O1Qc0NhgAMEYrnXUKBdllPkzzx+NsMU0nay0pII12+6VgBXlHlSDkewWKT4QdamhF9FzwlRE2LAj4k0SNFz9LBj5bKtqtAHgviu8UW2xosqdiuWEo/Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263727; c=relaxed/simple; bh=6LQoW6kQOfbEsfzMM/F1yWmTZlzQ6I3tofZzfSVmVy0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VBR3PQHGmzmZFRIQzXkywM2XqouCg010FzZz+opZcEEPb2uV2oqL6+Wr6gaVq1VlIh9WdbM6YKaF68D1GQ3r5tgkM78MZts+/CbspFb6ktUBwh9hBljcoktdtuchSErBpGQxy4Pp73Rt5xrRqJaJZIqxJUAERvKjqGUUE5gcXG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 67EE31688; Mon, 23 Mar 2026 04:01:59 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C69DD3F73B; Mon, 23 Mar 2026 04:02:02 -0700 (PDT) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Michal Piekos , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] pinctrl: sunxi: Remove unneeded IRQ remuxing for some SoCs Date: Mon, 23 Mar 2026 12:01:48 +0100 Message-ID: <20260323110151.2352832-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260323110151.2352832-1-andre.przywara@arm.com> References: <20260323110151.2352832-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when that line is muxed for IRQ triggering (muxval 6), but only if it's explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this behaviour, so we added a optional workaround, triggered by a quirk bit, which triggers remuxing the pin when it's configured for IRQ, while we need to read its value. For some reasons this quirk flag was copied over to newer SoCs, even though they don't show this behaviour, and the GPIO data register reflects the true GPIO state even with a pin configured to muxval 6 (IRQ). The workaround is just more costly, but doesn't break otherwise, so this was probably never noticed by anyone. Experiments confirm that the H5, H6, H616 and A523 do not need this workaround, they show the GPIO line value with both muxval 0 and 6. Remove the unneeded quirk from those SoC's pinctrl driver description. This should have no obvious effect on the H5, H6, H616 (other than being more efficient), but the workaround is broken for the A523, so it fixes (one part of the) interrupt operation there. Signed-off-by: Andre Przywara Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A523 GP= IO ports") Acked-by: Chen-Yu Tsai --- drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 2 -- drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c | 1 - 5 files changed, 6 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/su= nxi/pinctrl-sun50i-h5.c index 669793c6578e..56ce0f78d4ba 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -533,7 +533,6 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctr= l_data_broken =3D { .pins =3D sun50i_h5_pins, .npins =3D ARRAY_SIZE(sun50i_h5_pins), .irq_banks =3D 2, - .irq_read_needs_mux =3D true, .disable_strict_mode =3D true, }; =20 @@ -541,7 +540,6 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctr= l_data =3D { .pins =3D sun50i_h5_pins, .npins =3D ARRAY_SIZE(sun50i_h5_pins), .irq_banks =3D 3, - .irq_read_needs_mux =3D true, .disable_strict_mode =3D true, }; =20 diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/su= nxi/pinctrl-sun50i-h6.c index 517118341316..22f3d3875316 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c @@ -589,7 +589,6 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = =3D { .npins =3D ARRAY_SIZE(h6_pins), .irq_banks =3D 4, .irq_bank_map =3D h6_irq_bank_map, - .irq_read_needs_mux =3D true, .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; =20 diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/= sunxi/pinctrl-sun50i-h616.c index ecf6d2438e21..48cf114505e0 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c @@ -875,7 +875,6 @@ static const struct sunxi_pinctrl_desc h616_pinctrl_dat= a =3D { .npins =3D ARRAY_SIZE(h616_pins), .irq_banks =3D ARRAY_SIZE(h616_irq_bank_map), .irq_bank_map =3D h616_irq_bank_map, - .irq_read_needs_mux =3D true, .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_CTL, }; =20 diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctr= l/sunxi/pinctrl-sun55i-a523-r.c index 69cd2b4ebd7d..462aa1c4a5fa 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -26,7 +26,6 @@ static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_B= ANKS] =3D static struct sunxi_pinctrl_desc a523_r_pinctrl_data =3D { .irq_banks =3D ARRAY_SIZE(a523_r_irq_bank_map), .irq_bank_map =3D a523_r_irq_bank_map, - .irq_read_needs_mux =3D true, .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_SEL, .pin_base =3D PL_BASE, }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/= sunxi/pinctrl-sun55i-a523.c index 7d2308c37d29..b6f78f1f30ac 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c @@ -26,7 +26,6 @@ static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BAN= KS] =3D static struct sunxi_pinctrl_desc a523_pinctrl_data =3D { .irq_banks =3D ARRAY_SIZE(a523_irq_bank_map), .irq_bank_map =3D a523_irq_bank_map, - .irq_read_needs_mux =3D true, .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; =20 --=20 2.43.0