From nobody Fri Apr 3 20:53:01 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E5CD6395DA5; Mon, 23 Mar 2026 11:02:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263724; cv=none; b=biyyg71h6zbw8DEciMfnvEVdI5xxRjGM/UIu0vkP+qSp7iWBiZBP2R6RYPgJTe+PHqEP8h9ljL3iJJkcOmcds3zGdNEL5iP/CZjHhP24JjN+CWTWKGwdDF66/tNJRe3bZC2OmfAY/losbcx3zjSRJhv6WJ9WM2n+MRcASz/jZr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263724; c=relaxed/simple; bh=bU23sLftWdUpqhSjt0sz7i0aaJt0OgbStG2HA8zA6LU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fWlnu251YU3jhtc2tHyl7Bbdrsq3LsfBR9kJtoq0tf2aiO3KSGNGflVGBYfX64SJOBQ5T8J6Y4I44E+fxx+fO4wJ8PiNa4yKyvYTns1xcadhoUoDx+4ZZqSHr711QW/i9bcfxHRlnYAmB3vmGVGDXqYuyRhx+AC8tiFwdhwS+rs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6E15D1684; Mon, 23 Mar 2026 04:01:56 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C9AD63F73B; Mon, 23 Mar 2026 04:01:59 -0700 (PDT) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Michal Piekos , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] pinctrl: sunxi: Rework IRQ remuxing to avoid fixed mux value Date: Mon, 23 Mar 2026 12:01:47 +0100 Message-ID: <20260323110151.2352832-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260323110151.2352832-1-andre.przywara@arm.com> References: <20260323110151.2352832-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Allwinner SoCs cannot read the state of a GPIO line when the pin is muxed to the IRQ function. To access that state anyway, we temporarily mux that pin back to GPIO input, then return it to the IRQ mux afterwards. This code assumes that the IRQ mux value is 0x6, even though newer SoCs (D1/T113/A523/...) encode the IRQ mux with 0xe. Avoid hardcoding the different IRQ mux values by saving the programmed value before switching to GPIO input, then restoring the saved value afterwards. This makes the code robust against future changes of the IRQ mux value. This also avoids calling the sunxi_pmx_set() function twice, each of which does a read/modify/write operation, fenced in by the pctl lock. The new code takes the lock around the whole operation, which is also safer since it avoids (probably theoretical) races against other code touching the mux register meanwhile. Signed-off-by: Andre Przywara Reviewed-by: Chen-Yu Tsai --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 23 ++++++++++++++++------- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 - 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/= pinctrl-sunxi.c index d3042e0c9712..6a86b7989b25 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -997,18 +997,27 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *c= hip, unsigned offset) struct sunxi_pinctrl *pctl =3D gpiochip_get_data(chip); bool set_mux =3D pctl->desc->irq_read_needs_mux && gpiochip_line_is_irq(chip, offset); - u32 pin =3D offset + chip->base; + u32 mreg, mshift, mmask, mval; u32 reg, shift, mask, val; + unsigned long flags; =20 sunxi_data_reg(pctl, offset, ®, &shift, &mask); + if (!set_mux) + return (readl(pctl->membase + reg) & mask) >> shift; =20 - if (set_mux) - sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); - + /* + * Some SoCs don't read the GPIO value registers correctly + * when the pinmux is not set to GPIO_INPUT. Temporarily switch + * to that mux, to read the correct value. + */ + sunxi_mux_reg(pctl, offset, &mreg, &mshift, &mmask); + raw_spin_lock_irqsave(&pctl->lock, flags); + mval =3D readl(pctl->membase + mreg); + writel((mval & ~mmask) | SUN4I_FUNC_INPUT << mshift, + pctl->membase + mreg); val =3D (readl(pctl->membase + reg) & mask) >> shift; - - if (set_mux) - sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); + writel(mval, pctl->membase + mreg); + raw_spin_unlock_irqrestore(&pctl->lock, flags); =20 return val; } diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/= pinctrl-sunxi.h index 0daf7600e2fb..ec7c977655b5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -85,7 +85,6 @@ #define IO_BIAS_MASK GENMASK(3, 0) =20 #define SUN4I_FUNC_INPUT 0 -#define SUN4I_FUNC_IRQ 6 #define SUN4I_FUNC_DISABLED_OLD 7 #define SUN4I_FUNC_DISABLED_NEW 15 =20 --=20 2.43.0 From nobody Fri Apr 3 20:53:01 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ED07A396B7F; Mon, 23 Mar 2026 11:02:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263727; cv=none; b=PvpDKFOyHEhymusCKePCvPYXJPZ0Ab0geXzfW/xgyhI8khCyeWHROG3O1Qc0NhgAMEYrnXUKBdllPkzzx+NsMU0nay0pII12+6VgBXlHlSDkewWKT4QdamhF9FzwlRE2LAj4k0SNFz9LBj5bKtqtAHgviu8UW2xosqdiuWEo/Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263727; c=relaxed/simple; bh=6LQoW6kQOfbEsfzMM/F1yWmTZlzQ6I3tofZzfSVmVy0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VBR3PQHGmzmZFRIQzXkywM2XqouCg010FzZz+opZcEEPb2uV2oqL6+Wr6gaVq1VlIh9WdbM6YKaF68D1GQ3r5tgkM78MZts+/CbspFb6ktUBwh9hBljcoktdtuchSErBpGQxy4Pp73Rt5xrRqJaJZIqxJUAERvKjqGUUE5gcXG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 67EE31688; Mon, 23 Mar 2026 04:01:59 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C69DD3F73B; Mon, 23 Mar 2026 04:02:02 -0700 (PDT) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Michal Piekos , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] pinctrl: sunxi: Remove unneeded IRQ remuxing for some SoCs Date: Mon, 23 Mar 2026 12:01:48 +0100 Message-ID: <20260323110151.2352832-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260323110151.2352832-1-andre.przywara@arm.com> References: <20260323110151.2352832-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when that line is muxed for IRQ triggering (muxval 6), but only if it's explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this behaviour, so we added a optional workaround, triggered by a quirk bit, which triggers remuxing the pin when it's configured for IRQ, while we need to read its value. For some reasons this quirk flag was copied over to newer SoCs, even though they don't show this behaviour, and the GPIO data register reflects the true GPIO state even with a pin configured to muxval 6 (IRQ). The workaround is just more costly, but doesn't break otherwise, so this was probably never noticed by anyone. Experiments confirm that the H5, H6, H616 and A523 do not need this workaround, they show the GPIO line value with both muxval 0 and 6. Remove the unneeded quirk from those SoC's pinctrl driver description. This should have no obvious effect on the H5, H6, H616 (other than being more efficient), but the workaround is broken for the A523, so it fixes (one part of the) interrupt operation there. Signed-off-by: Andre Przywara Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A523 GP= IO ports") Acked-by: Chen-Yu Tsai --- drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 2 -- drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 1 - drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c | 1 - 5 files changed, 6 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/su= nxi/pinctrl-sun50i-h5.c index 669793c6578e..56ce0f78d4ba 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -533,7 +533,6 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctr= l_data_broken =3D { .pins =3D sun50i_h5_pins, .npins =3D ARRAY_SIZE(sun50i_h5_pins), .irq_banks =3D 2, - .irq_read_needs_mux =3D true, .disable_strict_mode =3D true, }; =20 @@ -541,7 +540,6 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctr= l_data =3D { .pins =3D sun50i_h5_pins, .npins =3D ARRAY_SIZE(sun50i_h5_pins), .irq_banks =3D 3, - .irq_read_needs_mux =3D true, .disable_strict_mode =3D true, }; =20 diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/su= nxi/pinctrl-sun50i-h6.c index 517118341316..22f3d3875316 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c @@ -589,7 +589,6 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = =3D { .npins =3D ARRAY_SIZE(h6_pins), .irq_banks =3D 4, .irq_bank_map =3D h6_irq_bank_map, - .irq_read_needs_mux =3D true, .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; =20 diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/= sunxi/pinctrl-sun50i-h616.c index ecf6d2438e21..48cf114505e0 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c @@ -875,7 +875,6 @@ static const struct sunxi_pinctrl_desc h616_pinctrl_dat= a =3D { .npins =3D ARRAY_SIZE(h616_pins), .irq_banks =3D ARRAY_SIZE(h616_irq_bank_map), .irq_bank_map =3D h616_irq_bank_map, - .irq_read_needs_mux =3D true, .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_CTL, }; =20 diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctr= l/sunxi/pinctrl-sun55i-a523-r.c index 69cd2b4ebd7d..462aa1c4a5fa 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -26,7 +26,6 @@ static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_B= ANKS] =3D static struct sunxi_pinctrl_desc a523_r_pinctrl_data =3D { .irq_banks =3D ARRAY_SIZE(a523_r_irq_bank_map), .irq_bank_map =3D a523_r_irq_bank_map, - .irq_read_needs_mux =3D true, .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_SEL, .pin_base =3D PL_BASE, }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/= sunxi/pinctrl-sun55i-a523.c index 7d2308c37d29..b6f78f1f30ac 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c @@ -26,7 +26,6 @@ static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BAN= KS] =3D static struct sunxi_pinctrl_desc a523_pinctrl_data =3D { .irq_banks =3D ARRAY_SIZE(a523_irq_bank_map), .irq_bank_map =3D a523_irq_bank_map, - .irq_read_needs_mux =3D true, .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; =20 --=20 2.43.0 From nobody Fri Apr 3 20:53:01 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EA68E3976A2; Mon, 23 Mar 2026 11:02:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263730; cv=none; b=NkQ1yovAn/jBS9iWOgmOslhRIpUnPoi6BYPZSLir1nOiyHXW5g6K+Axt1yTSYbA0Va8XBlxvDppraYGEhxOS9CJTuPaddDL52kvtzirznNzUEnEmxR3TjQSupRPemF8ygFqEoYcEGH6NaUtyZDq2DdphD9/DOb6xnUQUnrp+g6U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263730; c=relaxed/simple; bh=g52Al9YWCGtwUmdi2nk9qV8gQKZV5m7STqJ7l17xicE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CHhpU7hv8XmWP7ihZ0m2ZChjFUjw4E1WkqNzPkL7cbHHjM6AzamFCT6Fy+/+PU/IuisDAc1RRVInXh7Tp9wQpfDkN4m8HXeGH1gwKSTujDGw2erqPtLY3Mgcss+IT9K5mNmWJzqoU3jZMPgPbfpy/F8WE+jQBLvlUiJfsVUuAFw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 665FF1692; Mon, 23 Mar 2026 04:02:02 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C37453F73B; Mon, 23 Mar 2026 04:02:05 -0700 (PDT) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Michal Piekos , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] dt-bindings: pinctrl: sun55i-a523: increase IRQ bank number Date: Mon, 23 Mar 2026 12:01:49 +0100 Message-ID: <20260323110151.2352832-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260323110151.2352832-1-andre.przywara@arm.com> References: <20260323110151.2352832-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A523 SoC implements 10 GPIO banks in the first pinctrl instance, but it skips the first bank (PortA), so their index goes from 1 to 10. The same is actually true for the IRQ banks: there are registers for 11 banks, though the first bank is not implemented (RAZ/WI). In contrast to previous SoCs, the count of the IRQ banks starts with this first unimplemented bank, so we need to provide an interrupt for it. And indeed the A523 user manual lists an interrupt number for PortA, so we need to increase the maximum number of interrupts per pin controller to 11, to be able to assign the correct interrupt number for each bank. Signed-off-by: Andre Przywara Reviewed-by: Chen-Yu Tsai --- .../bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a52= 3-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i= -a523-pinctrl.yaml index 154e03da8ce9..f87b8274cc37 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinct= rl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinct= rl.yaml @@ -34,7 +34,7 @@ properties: =20 interrupts: minItems: 2 - maxItems: 10 + maxItems: 11 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. @@ -61,7 +61,7 @@ properties: bank found in the controller $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 - maxItems: 10 + maxItems: 11 =20 patternProperties: # It's pretty scary, but the basic idea is that: @@ -130,8 +130,8 @@ allOf: then: properties: interrupts: - minItems: 10 - maxItems: 10 + minItems: 11 + maxItems: 11 =20 - if: properties: --=20 2.43.0 From nobody Fri Apr 3 20:53:01 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E9CFE3932D1; Mon, 23 Mar 2026 11:02:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263733; cv=none; b=Rix5osQhw/cnvodD+KKVfPn2wcGkgZ6pIDl/4oSHUZ/+i8WWyM6gfz3cfmB6AV5Gd6NmLoikMq4bAoNzRLY1jC0L8uf+tVFaAGeJY09ngFnMpa23M4W1lau6I2Nj6nQZ+ZHqGHXJbYCsibKG+8cmMHFwnynci+wwl14b9REVc/I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263733; c=relaxed/simple; bh=lWhME2tkbRcxfTvqm6yLaBA+b8VpP5Ehcr7ZN2IZKfA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GeQdSIN5iQEfaC6a9NG0bCBlXClSOK7eRZIQayEX/x+jrf27L9LHj+ixe4c8h12PFd7t5t/37enMh3MJ6CAwXhRHmtnG1P86G2Ljh9BnVugjHTWRlagW/a7XyNUjJG3cxsFVdQAXBNDKS7qgBgv3T/H00jB/3VdDL3XivplSuB8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 68F04169C; Mon, 23 Mar 2026 04:02:05 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BF1E93F73B; Mon, 23 Mar 2026 04:02:08 -0700 (PDT) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Michal Piekos , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] arm64: dts: allwinner: a523: Add missing GPIO interrupt Date: Mon, 23 Mar 2026 12:01:50 +0100 Message-ID: <20260323110151.2352832-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260323110151.2352832-1-andre.przywara@arm.com> References: <20260323110151.2352832-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Even though the Allwinner A523 SoC implements 10 GPIO banks, it has actually registers for 11 IRQ banks, and even an interrupt assigned to the first, non-implemented IRQ bank. Add that first interrupt to the list of GPIO interrupts, to correct the association between IRQs and GPIO banks. This fixes GPIO IRQ operation on boards with A523 SoCs, as seen by broken SD card detect functionality, for instance. Signed-off-by: Andre Przywara Fixes: 35ac96f79664 ("arm64: dts: allwinner: Add Allwinner A523 .dtsi file") Reviewed-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 9335977751e2..cea5b166c00f 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -128,7 +128,8 @@ gpu: gpu@1800000 { pio: pinctrl@2000000 { compatible =3D "allwinner,sun55i-a523-pinctrl"; reg =3D <0x2000000 0x800>; - interrupts =3D , + interrupts =3D , + , , , , --=20 2.43.0 From nobody Fri Apr 3 20:53:01 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2D0F338838A; Mon, 23 Mar 2026 11:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263737; cv=none; b=RN6q2m5yB0xUDOfMKi1viU/cXc+5amvQfwFbyJ+N6hznSmTLdsdc5BDBH01fN8ZPYRF/449nOvhAZLPUJtxnYPwPxCszpN3M5sOO1laBsT2aU7LrZGtuIUVWAhXm9GHViJJAtPEruip4Ay9bp3+6dlZuwKgONSgxKIziox7BU5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774263737; c=relaxed/simple; bh=BdcEra9FbAB3SE5ZyznxdSUBQYhHbt1CSIJp0DdTRCo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MON7eXG8tG0y33k4kINdSplsr1mHYy0SiSBpnMZLEVvKTT38bf9fwYX28jHWHqcnrmw2bcgea9M0ePLMe7rVSOE5WGd+XDV57LRgmSi6nRajwef/NCk1NSQyAWEDTLbeYZu/XvbmfiXNJAltrzsYNpv3pwBv5uEhbEehJVd+gJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A37F6169E; Mon, 23 Mar 2026 04:02:08 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C4FD23F73B; Mon, 23 Mar 2026 04:02:11 -0700 (PDT) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Michal Piekos , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] pinctrl: sunxi: a523: add missing IRQ bank (plus old DT workaround) Date: Mon, 23 Mar 2026 12:01:51 +0100 Message-ID: <20260323110151.2352832-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260323110151.2352832-1-andre.przywara@arm.com> References: <20260323110151.2352832-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A532 SoC implements 10 GPIO banks, each of which is interrupt capable. However the first bank (PortA) is skipped, so the indicies of those banks range from 1 to 10, not 0 to 9. We described the skipped bank correctly, but missed that for the IRQ banks, where we rely on the IRQ bank index to be aligned with the MMIO register offset, starting at 0x200. Correct that by increasing the number of IRQ banks to 11, to cover both the first skipped one, but also the last one (PortK). This fixes a bug where the interrupt numbers would be off-by-one, due to that mis-enumeration. The big caveat is that now old DTs break the kernel, since they only provide 10 interrupts, and the driver bails out entirely due to the last missing one. So add a workaround for this particular case, where we detect the requirement for 11 banks, but only 10 interrupts provided, and continue with 10 IRQs, albeit emitting a warning about a DT update. This would still be broken in terms of interrupt assignment, but it was broken the whole time before, so it's not a regression. Signed-off-by: Andre Przywara Reviewed-by: Chen-Yu Tsai --- drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 22 +++++++++++++-------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/= sunxi/pinctrl-sun55i-a523.c index b6f78f1f30ac..a1d157de53d2 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c @@ -17,7 +17,7 @@ static const u8 a523_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS= ] =3D /* PA PB PC PD PE PF PG PH PI PJ PK */ { 0, 15, 17, 24, 16, 7, 15, 20, 17, 28, 24 }; =20 -static const unsigned int a523_irq_bank_map[] =3D { 0, 1, 2, 3, 4, 5, 6, 7= , 8, 9 }; +static const unsigned int a523_irq_bank_map[] =3D { 0, 1, 2, 3, 4, 5, 6, 7= , 8, 9, 10 }; =20 static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =3D /* PA PB PC PD PE PF PG PH PI PJ PK */ diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/= pinctrl-sunxi.c index 6a86b7989b25..ffee79397590 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -1582,6 +1583,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_dev= ice *pdev, struct sunxi_pinctrl *pctl; struct pinmux_ops *pmxops; int i, ret, last_pin, pin_idx; + int num_irq_banks; struct clk *clk; =20 pctl =3D devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); @@ -1715,16 +1717,20 @@ int sunxi_pinctrl_init_with_flags(struct platform_d= evice *pdev, goto gpiochip_error; } =20 - pctl->irq =3D devm_kcalloc(&pdev->dev, - pctl->desc->irq_banks, - sizeof(*pctl->irq), - GFP_KERNEL); + num_irq_banks =3D pctl->desc->irq_banks; + /* Workaround for old A523 DT, exposing one less interrupt. */ + if (num_irq_banks =3D=3D 11 && of_irq_count(node) < 11) { + num_irq_banks =3D 10; + pr_warn("Not enough PIO interrupts, please update your DT!\n"); + } + pctl->irq =3D devm_kcalloc(&pdev->dev, num_irq_banks, + sizeof(*pctl->irq), GFP_KERNEL); if (!pctl->irq) { ret =3D -ENOMEM; goto gpiochip_error; } =20 - for (i =3D 0; i < pctl->desc->irq_banks; i++) { + for (i =3D 0; i < num_irq_banks; i++) { pctl->irq[i] =3D platform_get_irq(pdev, i); if (pctl->irq[i] < 0) { ret =3D pctl->irq[i]; @@ -1733,7 +1739,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_dev= ice *pdev, } =20 pctl->domain =3D irq_domain_create_linear(dev_fwnode(&pdev->dev), - pctl->desc->irq_banks * IRQ_PER_BANK, + num_irq_banks * IRQ_PER_BANK, &sunxi_pinctrl_irq_domain_ops, pctl); if (!pctl->domain) { dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); @@ -1741,7 +1747,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_dev= ice *pdev, goto gpiochip_error; } =20 - for (i =3D 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { + for (i =3D 0; i < (num_irq_banks * IRQ_PER_BANK); i++) { int irqno =3D irq_create_mapping(pctl->domain, i); =20 irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class, @@ -1751,7 +1757,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_dev= ice *pdev, irq_set_chip_data(irqno, pctl); } =20 - for (i =3D 0; i < pctl->desc->irq_banks; i++) { + for (i =3D 0; i < num_irq_banks; i++) { /* Mask and clear all IRQs before registering a handler */ writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); --=20 2.43.0