From nobody Fri Apr 3 20:53:04 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA80D5C613 for ; Mon, 23 Mar 2026 08:25:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774254344; cv=none; b=DL5Ji8y56rnodX1ard7VEJiOJm27gq7s9PFAVgtLjr2ssME1va5MwB7wErBbTRNvnJgCW7QJpUL7p9+VGmbyqPl0oJKmY14pEeK1gANCa2dVxZcH8s3I9lPFjeyV0v4aXx9d9YrB8s+IxR8NNaoXAXh7jDYJzGQH4q1IyjMLrCk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774254344; c=relaxed/simple; bh=bzK1tMLqJbO+RnPDdsxA5EnS5wetK1kd+lTn6z4nHWo=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=O9YBzOPUVAt5l4jW9XVJHlRVINmEG9nRVEr17N7A0Kb+RbTbHcXT2UxhEhKGnIZQKQHBCY1zD6L/qfI1BU+wEVrKD8PgEPfDC0lhpbjAoKl1/NW+gIa5yRH4GFzxXbk/MLLFpEPmHVcwJgeQNDfafF+F6pilHtUFUvLwbfLFv8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=C7YO3wAy; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C7YO3wAy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774254342; x=1805790342; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=bzK1tMLqJbO+RnPDdsxA5EnS5wetK1kd+lTn6z4nHWo=; b=C7YO3wAykcFF+NFXpT7rzCkx7iMhWhRRVEAyDiCiUB2eRGe7wqoql4/d bed/ylT8u5SU0oleJSG07iTdVFzAEYH9WzgDDs6RkF6NJK8Zi4I+L0s/9 jaVOBQiDPHJl2wUAediKMKQTwgANKcMm/nyc6R5ppJLb9Z9V4WEAfJZMM 48LJ/0U3yoh4+kv8VZTGGsntrsase/AQQnOsKcyr4rbTDmYbQjj804ivF ER8Pl4sjbLazn7ThH+AcHBnUKXSu4+UWAsQSaSoH3WptgUHIb8ZBOV/Zm RWtY8RXKpjUkHkUbYWaODXq6j3mcDAWekJhsVW1szEs06d0d7P69bT0RN g==; X-CSE-ConnectionGUID: 1XDoYsTmS/y6t94E9iKJJA== X-CSE-MsgGUID: +9OiHZ9qQheYJnQa58CF8A== X-IronPort-AV: E=McAfee;i="6800,10657,11737"; a="74266041" X-IronPort-AV: E=Sophos;i="6.23,136,1770624000"; d="scan'208";a="74266041" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 01:25:41 -0700 X-CSE-ConnectionGUID: YNq7vz3/QIGwWZ/+twFCEw== X-CSE-MsgGUID: CpYbLRP5SSehhSkpb2VsEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,136,1770624000"; d="scan'208";a="224170939" Received: from khuang2-desk.gar.corp.intel.com ([10.124.221.3]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 01:25:37 -0700 From: Kai Huang To: tglx@kernel.org, mingo@redhat.com, peterz@infradead.org, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com Cc: x86@kernel.org, darwi@linutronix.de, david.kaplan@amd.com, kees@kernel.org, linux-kernel@vger.kernel.org, Kai Huang Subject: [PATCH] x86/cpu: Align the vmx_capability array to size of unsigned long Date: Mon, 23 Mar 2026 21:25:27 +1300 Message-ID: <20260323082527.732899-1-kai.huang@intel.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A WARNING splat was triggered during system boot with a kernel built with CONFIG_DEBUG_ATOMIC=3Dy and CONFIG_DEBUG_ATOMIC_LARGEST_ALIGN=3Dy on one Intel platform: systemd[1]: DMI BIOS Extension table does not indicate virtualization. ------------[ cut here ]------------ (unsigned long)v & mask WARNING: ./include/linux/instrumented.h:67 at show_cpuinfo+0x4e9/0x620, C= PU#133: systemd/1 ... RIP: 0010:show_cpuinfo+0x4e9/0x620 ... Call Trace: seq_read_iter+0x130/0x4b0 ? rw_verify_area+0x15b/0x200 vfs_read+0x224/0x350 ksys_read+0x61/0xd0 do_syscall_64+0x12c/0x1510 show_cpuinfo() calls test_bit() for each bit in the cpuinfo_x86's vmx_capability array to print the supported VMX feature names in /proc/cpuinfo. Per Documentation/atomic_bitops.txt, test_bit() is an atomic bitops, and it requires the provided address to be aligned to size of unsigned long. Commit 80047d84eed2 ("atomic: add alignment check to instrumented atomic operations") added the WARN() if the alignment check fails. The vmx_capability is an array of type __u32 thus it's only naturally aligned to 4-bytes, causing the above WARNING splat. On x86, it is necessary to ensure the "true" atomic bitops only operate on the address that is aligned to unsigned long, otherwise the atomic instruction may end up crossing cacheline boundary, causing a full bus lock. If the kernel has enabled split lock detection, a full bus lock can cause #AC split lock exception, resulting in kernel panic. The cpuinfo_x86's x86_capability array once was only aligned to __u32 too. The commit db8c33f8b5be ("x86/cpu: Align the x86_capability array to size of unsigned long") changed the alignment for x86_capability in order to support split lock detection in the kernel. However, this particular WARNING splat caused by test_bit() is more like a false positive, since test_bit() is a non-RMW operation and x86 implements it using BT (bit test) instruction, which can never be used with LOCK prefix. Except for the test_bit(), there's no other atomic bitops is used to access vmx_capability array. But it's still better to get rid of the WARNING. For simplicity, align the vmx_capability array to size of unsigned long, following the change to x86_capability. Note: Commit 80047d84eed2 ("atomic: add alignment check to instrumented atomic operations") was merged later than the vmx_capability was added. And there's no real harm here, hence no 'Fixes' tag. Signed-off-by: Kai Huang --- arch/x86/include/asm/processor.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 10b5355b323e..7ef10f638161 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -150,7 +150,11 @@ struct cpuinfo_x86 { int x86_tlbsize; #endif #ifdef CONFIG_X86_VMX_FEATURE_NAMES - __u32 vmx_capability[NVMXINTS]; + /* See the comment of 'x86_capability_alignment' below */ + union { + __u32 vmx_capability[NVMXINTS]; + unsigned long vmx_capability_alignment; + }; #endif __u8 x86_virt_bits; __u8 x86_phys_bits; base-commit: fde794883717fd67a5521fa69881afd8c8979764 --=20 2.53.0