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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 576133F70A8; Sun, 22 Mar 2026 20:51:36 -0700 (PDT) From: Ratheesh Kannoth To: , CC: , , , , , , , , , , , , , , Ratheesh Kannoth Subject: [PATCH v7 net-next 4/5] octeontx2-af: npc: cn20k: dynamically allocate and free default MCAM entries Date: Mon, 23 Mar 2026 09:21:09 +0530 Message-ID: <20260323035110.3908741-5-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260323035110.3908741-1-rkannoth@marvell.com> References: <20260323035110.3908741-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: tNuscvPknY-Tk4nB5NIzpgdlE6eizyVZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAyNiBTYWx0ZWRfX5lIRuZh7fa+b sfIDRSUQP0dATXg5XumJ+J/2DRj2q3FRBIBVYpWjFGou01NXNFPh8vxj5mlArKTGZuBptQFWwpH KaCTyDXBRTK/VImEJ6fDbm3vSA9XaiR7dTCPT0V/OLGN6jQ8E/F4iW+rXsSNEZknK6s4wIHeVAC Bfn6f8X/rdp8wn/675rupuL0ohkwy+R0FnrpTMhw/aTbthYH1oKxa7iCWkGWU+mc6SdVucYTPcy ig+mQzkaYpGLVb/koAvTiwHMXUad6fEhw2qq8ZLwjKxa0hcEJK1fV7XWldAeUta104g+flCazqK ejULRWRp0RdAqktrRcO1hA9mb++vRPChdRo/SW0sS5lJXaJQUoU6bzhLNaojRgmg7lM4W398qih VjJi8q+fkNo3Xa5zWwVOUpIvX59GZiJT7kz/xl0xwqhmEaqI5jDhQPNY6btY0eg6CPcpxZzanud 8zJwMCo6l6TxVJgx0sQ== X-Authority-Analysis: v=2.4 cv=Ed7FgfmC c=1 sm=1 tr=0 ts=69c0b8cf cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=M5GUcnROAAAA:8 a=WDb9-8Tz2aN2ynPxKakA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: tNuscvPknY-Tk4nB5NIzpgdlE6eizyVZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_01,2026-03-20_02,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Improve MCAM utilization by tying default (broadcast, multicast, promisc, ucast) entry lifetime to NIX LF usage. - On NIX LF alloc (e.g. kernel or DPDK), allocate default MCAM entries if missing; on NIX LF free, release them so they return to the pool. - Add NIX_LF_DONT_FREE_DFT_IDXS so the kernel PF driver can free the NIX LF without releasing default entries (e.g. across suspend/resume). - When NIX LF is used by DPDK, default entries are allocated on first use and freed when the LF is released if NIX_LF_DONT_FREE_DFT_IDXS is not set Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 108 ++++++++++----- .../ethernet/marvell/octeontx2/af/cn20k/npc.h | 1 + .../net/ethernet/marvell/octeontx2/af/mbox.h | 1 + .../ethernet/marvell/octeontx2/af/rvu_nix.c | 16 ++- .../ethernet/marvell/octeontx2/af/rvu_npc.c | 125 +++++++++++++----- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 6 +- 6 files changed, 189 insertions(+), 68 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.c index 153765b3e504..69439ff76e10 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c @@ -808,6 +808,11 @@ npc_cn20k_enable_mcam_entry(struct rvu *rvu, int blkad= dr, u64 cfg, hw_prio; u8 kw_type; =20 + if (index < 0 || index >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index %d\n", index); + return; + } + enable ? set_bit(index, npc_priv.en_map) : clear_bit(index, npc_priv.en_map); =20 @@ -1053,6 +1058,11 @@ void npc_cn20k_config_mcam_entry(struct rvu *rvu, in= t blkaddr, int index, int kw =3D 0; u8 kw_type; =20 + if (index < 0 || index >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index %d\n", index); + return; + } + /* Disable before mcam entry update */ npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, false); =20 @@ -1132,6 +1142,11 @@ void npc_cn20k_copy_mcam_entry(struct rvu *rvu, int = blkaddr, u16 src, u16 dest) int bank, i, sb, db; int dbank, sbank; =20 + if (src >=3D mcam->total_entries || dest >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index src=3D%u dest=3D%u\n", src, dest); + return; + } + dbank =3D npc_get_bank(mcam, dest); sbank =3D npc_get_bank(mcam, src); npc_mcam_idx_2_key_type(rvu, src, &src_kwtype); @@ -1190,11 +1205,24 @@ void npc_cn20k_read_mcam_entry(struct rvu *rvu, int= blkaddr, u16 index, int kw =3D 0, bank; u8 kw_type; =20 + if (index >=3D mcam->total_entries) { + WARN(1, "Wrong mcam index %u\n", index); + return; + } + npc_mcam_idx_2_key_type(rvu, index, &kw_type); =20 bank =3D npc_get_bank(mcam, index); index &=3D (mcam->banksize - 1); =20 + cfg =3D rvu_read64(rvu, blkaddr, + NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, bank, 0)); + entry->action =3D cfg; + + cfg =3D rvu_read64(rvu, blkaddr, + NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, bank, 1)); + entry->vtag_action =3D cfg; + cfg =3D rvu_read64(rvu, blkaddr, NPC_AF_CN20K_MCAMEX_BANKX_CAMX_INTF_EXT(index, bank, 1)) & 3; @@ -1244,7 +1272,7 @@ void npc_cn20k_read_mcam_entry(struct rvu *rvu, int b= lkaddr, u16 index, bank, 0)); npc_cn20k_fill_entryword(entry, kw + 3, cam0, cam1); - goto read_action; + return; } =20 for (bank =3D 0; bank < mcam->banks_per_entry; bank++, kw =3D kw + 4) { @@ -1289,17 +1317,6 @@ void npc_cn20k_read_mcam_entry(struct rvu *rvu, int = blkaddr, u16 index, npc_cn20k_fill_entryword(entry, kw + 3, cam0, cam1); } =20 -read_action: - /* 'action' is set to same value for both bank '0' and '1'. - * Hence, reading bank '0' should be enough. - */ - cfg =3D rvu_read64(rvu, blkaddr, - NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, 0, 0)); - entry->action =3D cfg; - - cfg =3D rvu_read64(rvu, blkaddr, - NPC_AF_CN20K_MCAMEX_BANKX_ACTIONX_EXT(index, 0, 1)); - entry->vtag_action =3D cfg; } =20 int rvu_mbox_handler_npc_cn20k_mcam_write_entry(struct rvu *rvu, @@ -1671,8 +1688,8 @@ int npc_mcam_idx_2_key_type(struct rvu *rvu, u16 mcam= _idx, u8 *key_type) =20 /* mcam_idx should be less than (2 * bank depth) */ if (mcam_idx >=3D npc_priv.bank_depth * 2) { - dev_err(rvu->dev, "%s: bad params\n", - __func__); + dev_err(rvu->dev, "%s: bad params mcam_idx=3D%u\n", + __func__, mcam_idx); return -EINVAL; } =20 @@ -4024,6 +4041,13 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16= pcifunc, u16 *bcast, void *val; int i, j; =20 + for (int i =3D 0; i < ARRAY_SIZE(ptr); i++) { + if (!ptr[i]) + continue; + + *ptr[i] =3D USHRT_MAX; + } + if (!npc_priv.init_done) return 0; =20 @@ -4039,7 +4063,6 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 = pcifunc, u16 *bcast, npc_dft_rule_name[NPC_DFT_RULE_PROMISC_ID], pcifunc); =20 - *ptr[0] =3D USHRT_MAX; return -ESRCH; } =20 @@ -4059,7 +4082,6 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 = pcifunc, u16 *bcast, npc_dft_rule_name[NPC_DFT_RULE_UCAST_ID], pcifunc); =20 - *ptr[3] =3D USHRT_MAX; return -ESRCH; } =20 @@ -4079,7 +4101,6 @@ int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 = pcifunc, u16 *bcast, __func__, npc_dft_rule_name[i], pcifunc); =20 - *ptr[j] =3D USHRT_MAX; continue; } =20 @@ -4174,7 +4195,7 @@ int rvu_mbox_handler_npc_get_dft_rl_idxs(struct rvu *= rvu, struct msg_req *req, return 0; } =20 -static bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc) +bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc) { return is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc)) || is_lbk_vf(rvu, pcifunc); @@ -4182,9 +4203,10 @@ static bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 p= cifunc) =20 void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pcifunc) { - struct npc_mcam_free_entry_req free_req =3D { 0 }; + struct npc_mcam *mcam =3D &rvu->hw->mcam; + struct rvu_npc_mcam_rule *rule, *tmp; unsigned long index; - struct msg_rsp rsp; + int blkaddr; u16 ptr[4]; int rc, i; void *map; @@ -4209,7 +4231,7 @@ void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pc= ifunc) index =3D NPC_DFT_RULE_ID_MK(pcifunc, NPC_DFT_RULE_PROMISC_ID); map =3D xa_erase(&npc_priv.xa_pf2dfl_rmap, index); if (!map) - dev_dbg(rvu->dev, + dev_err(rvu->dev, "%s: Err from delete %s mcam idx from xarray (pcifunc=3D%#x\n", __func__, npc_dft_rule_name[NPC_DFT_RULE_PROMISC_ID], @@ -4223,7 +4245,7 @@ void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pc= ifunc) index =3D NPC_DFT_RULE_ID_MK(pcifunc, NPC_DFT_RULE_UCAST_ID); map =3D xa_erase(&npc_priv.xa_pf2dfl_rmap, index); if (!map) - dev_dbg(rvu->dev, + dev_err(rvu->dev, "%s: Err from delete %s mcam idx from xarray (pcifunc=3D%#x\n", __func__, npc_dft_rule_name[NPC_DFT_RULE_UCAST_ID], @@ -4237,21 +4259,47 @@ void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 = pcifunc) index =3D NPC_DFT_RULE_ID_MK(pcifunc, i); map =3D xa_erase(&npc_priv.xa_pf2dfl_rmap, index); if (!map) - dev_dbg(rvu->dev, + dev_err(rvu->dev, "%s: Err from delete %s mcam idx from xarray (pcifunc=3D%#x\n", __func__, npc_dft_rule_name[i], pcifunc); } =20 free_rules: + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); + if (blkaddr < 0) + return; =20 - free_req.hdr.pcifunc =3D pcifunc; - free_req.all =3D 1; - rc =3D rvu_mbox_handler_npc_mcam_free_entry(rvu, &free_req, &rsp); - if (rc) - dev_err(rvu->dev, - "%s: Error deleting default entries (pcifunc=3D%#x\n", - __func__, pcifunc); + for (int i =3D 0; i < 4; i++) { + if (ptr[i] =3D=3D USHRT_MAX) + continue; + + mutex_lock(&mcam->lock); + npc_mcam_clear_bit(mcam, ptr[i]); + mcam->entry2pfvf_map[ptr[i]] =3D NPC_MCAM_INVALID_MAP; + npc_cn20k_enable_mcam_entry(rvu, blkaddr, ptr[i], false); + mcam->entry2target_pffunc[ptr[i]] =3D 0x0; + mutex_unlock(&mcam->lock); + + rc =3D npc_cn20k_idx_free(rvu, &ptr[i], 1); + if (rc) + dev_err(rvu->dev, + "%s:%d Error deleting default entries (pcifunc=3D%#x) mcam_idx=3D%u\n", + __func__, __LINE__, pcifunc, ptr[i]); + } + + mutex_lock(&mcam->lock); + list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { + for (int i =3D 0; i < 4; i++) { + if (ptr[i] !=3D rule->entry) + continue; + + list_del(&rule->list); + kfree(rule); + break; + } + } + mutex_unlock(&mcam->lock); } =20 int npc_cn20k_dft_rules_alloc(struct rvu *rvu, u16 pcifunc) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npc.h index 6f9f796940f3..1b4b4a6fa378 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h @@ -345,5 +345,6 @@ int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mca= m_idx, int *sb_off); const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz); int npc_cn20k_search_order_set(struct rvu *rvu, u64 arr[32], int cnt); +bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc); =20 #endif /* NPC_CN20K_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index dc42c81c0942..e07fbf842b94 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1009,6 +1009,7 @@ struct nix_lf_free_req { struct mbox_msghdr hdr; #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) +#define NIX_LF_DONT_FREE_DFT_IDXS BIT_ULL(2) u64 flags; }; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index ef5b081162eb..bd671b553df5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -16,6 +16,7 @@ #include "cgx.h" #include "lmac_common.h" #include "rvu_npc_hash.h" +#include "cn20k/npc.h" =20 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc); static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, @@ -1684,10 +1685,16 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, if (is_sdp_pfvf(rvu, pcifunc)) intf =3D NIX_INTF_TYPE_SDP; =20 + if (is_cn20k(rvu->pdev)) { + rc =3D npc_cn20k_dft_rules_alloc(rvu, pcifunc); + if (rc) + goto free_mem; + } + err =3D nix_interface_init(rvu, pcifunc, intf, nixlf, rsp, !!(req->flags & NIX_LF_LBK_BLK_SEL)); if (err) - goto free_mem; + goto free_dft; =20 /* Disable NPC entries as NIXLF's contexts are not initialized yet */ rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); @@ -1699,6 +1706,10 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, =20 goto exit; =20 +free_dft: + if (is_cn20k(rvu->pdev)) + npc_cn20k_dft_rules_free(rvu, pcifunc); + free_mem: nix_ctx_free(rvu, pfvf); rc =3D -ENOMEM; @@ -1775,6 +1786,9 @@ int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, str= uct nix_lf_free_req *req, =20 nix_ctx_free(rvu, pfvf); =20 + if (is_cn20k(rvu->pdev) && !(req->flags & NIX_LF_DONT_FREE_DFT_IDXS)) + npc_cn20k_dft_rules_free(rvu, pcifunc); + return 0; } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index c2ca5ed1d028..8d260bcfbf38 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -165,12 +165,20 @@ int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, =20 switch (type) { case NIXLF_BCAST_ENTRY: + if (bcast =3D=3D USHRT_MAX) + return -EINVAL; return bcast; case NIXLF_ALLMULTI_ENTRY: + if (mcast =3D=3D USHRT_MAX) + return -EINVAL; return mcast; case NIXLF_PROMISC_ENTRY: + if (promisc =3D=3D USHRT_MAX) + return -EINVAL; return promisc; case NIXLF_UCAST_ENTRY: + if (ucast =3D=3D USHRT_MAX) + return -EINVAL; return ucast; default: return -EINVAL; @@ -237,12 +245,8 @@ void npc_enable_mcam_entry(struct rvu *rvu, struct npc= _mcam *mcam, int bank =3D npc_get_bank(mcam, index); int actbank =3D bank; =20 - if (is_cn20k(rvu->pdev)) { - if (index < 0 || index >=3D mcam->banksize * mcam->banks) - return; - + if (is_cn20k(rvu->pdev)) return npc_cn20k_enable_mcam_entry(rvu, blkaddr, index, enable); - } =20 index &=3D (mcam->banksize - 1); for (; bank < (actbank + mcam->banks_per_entry); bank++) { @@ -1113,7 +1117,7 @@ void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, = u16 pcifunc, int nixlf, index =3D mcam_index; } =20 - if (index >=3D mcam->total_entries) + if (index < 0 || index >=3D mcam->total_entries) return; =20 bank =3D npc_get_bank(mcam, index); @@ -1158,16 +1162,18 @@ void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu= , u16 pcifunc, int nixlf, /* If PF's promiscuous entry is enabled, * Set RSS action for that entry as well */ - npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, - blkaddr, alg_idx); + if (index >=3D 0) + npc_update_rx_action_with_alg_idx(rvu, action, pfvf, + index, blkaddr, alg_idx); =20 index =3D npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, NIXLF_ALLMULTI_ENTRY); /* If PF's allmulti entry is enabled, * Set RSS action for that entry as well */ - npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, - blkaddr, alg_idx); + if (index >=3D 0) + npc_update_rx_action_with_alg_idx(rvu, action, pfvf, + index, blkaddr, alg_idx); } } =20 @@ -1212,8 +1218,13 @@ static void npc_enadis_default_entries(struct rvu *r= vu, u16 pcifunc, { struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, pcifunc); struct npc_mcam *mcam =3D &rvu->hw->mcam; + int type =3D NIXLF_UCAST_ENTRY; int index, blkaddr; =20 + /* only CGX or LBK interfaces have default entries */ + if (is_cn20k(rvu->pdev) && !npc_is_cgx_or_lbk(rvu, pcifunc)) + return; + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); if (blkaddr < 0) return; @@ -1221,8 +1232,11 @@ static void npc_enadis_default_entries(struct rvu *r= vu, u16 pcifunc, /* Ucast MCAM match entry of this PF/VF */ if (npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf)) { + if (is_cn20k(rvu->pdev) && is_lbk_vf(rvu, pcifunc)) + type =3D NIXLF_PROMISC_ENTRY; + index =3D npc_get_nixlf_mcam_index(mcam, pcifunc, - nixlf, NIXLF_UCAST_ENTRY); + nixlf, type); npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); } =20 @@ -1232,9 +1246,13 @@ static void npc_enadis_default_entries(struct rvu *r= vu, u16 pcifunc, if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast) return; =20 + type =3D NIXLF_BCAST_ENTRY; + if (is_cn20k(rvu->pdev) && is_lbk_vf(rvu, pcifunc)) + type =3D NIXLF_PROMISC_ENTRY; + /* add/delete pf_func to broadcast MCE list */ npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, - NIXLF_BCAST_ENTRY, enable); + type, enable); } =20 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nix= lf) @@ -1244,6 +1262,9 @@ void rvu_npc_disable_default_entries(struct rvu *rvu,= u16 pcifunc, int nixlf) =20 npc_enadis_default_entries(rvu, pcifunc, nixlf, false); =20 + if (is_cn20k(rvu->pdev) && is_vf(pcifunc)) + return; + /* Delete multicast and promisc MCAM entries */ npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, NIXLF_ALLMULTI_ENTRY, false); @@ -1301,6 +1322,10 @@ void rvu_npc_disable_mcam_entries(struct rvu *rvu, u= 16 pcifunc, int nixlf) if (blkaddr < 0) return; =20 + /* only CGX or LBK interfaces have default entries */ + if (is_cn20k(rvu->pdev) && !npc_is_cgx_or_lbk(rvu, pcifunc)) + return; + mutex_lock(&mcam->lock); =20 /* Disable MCAM entries directing traffic to this 'pcifunc' */ @@ -2504,33 +2529,58 @@ void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 = index) static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mc= am, int blkaddr, u16 pcifunc) { + u16 dft_idxs[NPC_DFT_RULE_MAX_ID] =3D {[0 ... NPC_DFT_RULE_MAX_ID - 1] = =3D USHRT_MAX}; u16 index, cntr; + bool dft_rl; int rc; =20 + npc_cn20k_dft_rules_idx_get(rvu, pcifunc, + &dft_idxs[NPC_DFT_RULE_BCAST_ID], + &dft_idxs[NPC_DFT_RULE_MCAST_ID], + &dft_idxs[NPC_DFT_RULE_PROMISC_ID], + &dft_idxs[NPC_DFT_RULE_UCAST_ID]); + /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */ for (index =3D 0; index < mcam->bmap_entries; index++) { - if (mcam->entry2pfvf_map[index] =3D=3D pcifunc) { - mcam->entry2pfvf_map[index] =3D NPC_MCAM_INVALID_MAP; - /* Free the entry in bitmap */ - npc_mcam_clear_bit(mcam, index); - /* Disable the entry */ - npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); - - /* Update entry2counter mapping */ - cntr =3D mcam->entry2cntr_map[index]; - if (cntr !=3D NPC_MCAM_INVALID_MAP) - npc_unmap_mcam_entry_and_cntr(rvu, mcam, - blkaddr, index, - cntr); - mcam->entry2target_pffunc[index] =3D 0x0; - if (is_cn20k(rvu->pdev)) { - rc =3D npc_cn20k_idx_free(rvu, &index, 1); - if (rc) - dev_err(rvu->dev, - "Failed to free mcam idx=3D%u pcifunc=3D%#x\n", - index, pcifunc); + if (mcam->entry2pfvf_map[index] !=3D pcifunc) + continue; + + mcam->entry2pfvf_map[index] =3D NPC_MCAM_INVALID_MAP; + + dft_rl =3D false; + if (is_cn20k(rvu->pdev)) { + if (dft_idxs[NPC_DFT_RULE_BCAST_ID] =3D=3D index || + dft_idxs[NPC_DFT_RULE_MCAST_ID] =3D=3D index || + dft_idxs[NPC_DFT_RULE_PROMISC_ID] =3D=3D index || + dft_idxs[NPC_DFT_RULE_UCAST_ID] =3D=3D index) { + dft_rl =3D true; } } + + /* Free the entry in bitmap.*/ + if (!dft_rl) + npc_mcam_clear_bit(mcam, index); + + /* Disable the entry */ + npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); + + /* Update entry2counter mapping */ + cntr =3D mcam->entry2cntr_map[index]; + if (cntr !=3D NPC_MCAM_INVALID_MAP) + npc_unmap_mcam_entry_and_cntr(rvu, mcam, + blkaddr, index, + cntr); + mcam->entry2target_pffunc[index] =3D 0x0; + if (is_cn20k(rvu->pdev)) { + if (dft_rl) + continue; + + rc =3D npc_cn20k_idx_free(rvu, &index, 1); + if (rc) + dev_err(rvu->dev, + "Failed to free mcam idx=3D%u pcifunc=3D%#x\n", + index, pcifunc); + } } } =20 @@ -3917,13 +3967,22 @@ void rvu_npc_clear_ucast_entry(struct rvu *rvu, int= pcifunc, int nixlf) struct npc_mcam *mcam =3D &rvu->hw->mcam; struct rvu_npc_mcam_rule *rule; int ucast_idx, blkaddr; + u8 type; =20 blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); if (blkaddr < 0) return; =20 + type =3D NIXLF_UCAST_ENTRY; + if (is_cn20k(rvu->pdev) && is_lbk_vf(rvu, pcifunc)) + type =3D NIXLF_PROMISC_ENTRY; + ucast_idx =3D npc_get_nixlf_mcam_index(mcam, pcifunc, - nixlf, NIXLF_UCAST_ENTRY); + nixlf, type); + + /* In cn20k, default rules are freed before detach rsrc */ + if (ucast_idx < 0) + return; =20 npc_enable_mcam_entry(rvu, mcam, blkaddr, ucast_idx, false); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index ee623476e5ff..81b088f5a016 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1053,7 +1053,6 @@ irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void= *pf_irq) /* Clear the IRQ */ otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); =20 - mbox_data =3D otx2_read64(pf, RVU_PF_PFAF_MBOX0); =20 if (mbox_data & MBOX_UP_MSG) { @@ -1729,7 +1728,7 @@ int otx2_init_hw_resources(struct otx2_nic *pf) mutex_lock(&mbox->lock); free_req =3D otx2_mbox_alloc_msg_nix_lf_free(mbox); if (free_req) { - free_req->flags =3D NIX_LF_DISABLE_FLOWS; + free_req->flags =3D NIX_LF_DISABLE_FLOWS | NIX_LF_DONT_FREE_DFT_IDXS; if (otx2_sync_mbox_msg(mbox)) dev_err(pf->dev, "%s failed to free nixlf\n", __func__); } @@ -1803,7 +1802,7 @@ void otx2_free_hw_resources(struct otx2_nic *pf) /* Reset NIX LF */ free_req =3D otx2_mbox_alloc_msg_nix_lf_free(mbox); if (free_req) { - free_req->flags =3D NIX_LF_DISABLE_FLOWS; + free_req->flags =3D NIX_LF_DISABLE_FLOWS | NIX_LF_DONT_FREE_DFT_IDXS; if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) free_req->flags |=3D NIX_LF_DONT_FREE_TX_VTAG; if (otx2_sync_mbox_msg(mbox)) @@ -1926,7 +1925,6 @@ int otx2_alloc_queue_mem(struct otx2_nic *pf) struct otx2_qset *qset =3D &pf->qset; struct otx2_cq_poll *cq_poll; =20 - /* RQ and SQs are mapped to different CQs, * so find out max CQ IRQs (i.e CINTs) needed. */ --=20 2.43.0