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Add SoC data and update top comment to describe register layout in more detail. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 75 ++++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 61 insertions(+), 14 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 857301baad51..c1e8a804d783 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -7,22 +7,60 @@ * Copyright (c) 2010-2020, NVIDIA Corporation. * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer * - * Overview of Tegra Pulse Width Modulator Register: - * 1. 13-bit: Frequency division (SCALE) - * 2. 8-bit : Pulse division (DUTY) - * 3. 1-bit : Enable bit + * Overview of Tegra Pulse Width Modulator Register + * CSR_0 of Tegra20, Tegra186, and Tegra194: + * +-------+-------+------------------------------------------------------= -----+ + * | Bit | Field | Description = | + * +-------+-------+------------------------------------------------------= -----+ + * | 31 | ENB | Enable Pulse width modulator. = | + * | | | 0 =3D DISABLE, 1 =3D ENABLE. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 30:16 | PWM_0 | Pulse width that needs to be programmed. = | + * | | | 0 =3D Always low. = | + * | | | 1 =3D 1 / 256 pulse high. = | + * | | | 2 =3D 2 / 256 pulse high. = | + * | | | N =3D N / 256 pulse high. = | + * | | | Only 8 bits are usable [23:16]. = | + * | | | Bit[24] can be programmed to 1 to achieve 100% duty = | + * | | | cycle. In this case the other bits [23:16] are set to= | + * | | | don=E2=80=99t care. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 12:0 | PFM_0 | Frequency divider that needs to be programmed, also k= nown | + * | | | as SCALE. Division by (1 + PFM_0). = | + * +-------+-------+------------------------------------------------------= -----+ * - * The PWM clock frequency is divided by 256 before subdividing it based - * on the programmable frequency division value to generate the required - * frequency for PWM output. The maximum output frequency that can be - * achieved is (max rate of source clock) / 256. - * e.g. if source clock rate is 408 MHz, maximum output frequency can be: - * 408 MHz/256 =3D 1.6 MHz. - * This 1.6 MHz frequency can further be divided using SCALE value in PWM. + * CSR_0 of Tegra264: + * +-------+-------+------------------------------------------------------= -----+ + * | Bit | Field | Description = | + * +-------+-------+------------------------------------------------------= -----+ + * | 31:16 | PWM_0 | Pulse width that needs to be programmed. = | + * | | | 0 =3D Always low. = | + * | | | 1 =3D 1 / (1 + CSR_1.DEPTH) pulse high. = | + * | | | 2 =3D 2 / (1 + CSR_1.DEPTH) pulse high. = | + * | | | N =3D N / (1 + CSR_1.DEPTH) pulse high. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 15:0 | PFM_0 | Frequency divider that needs to be programmed, also k= nown | + * | | | as SCALE. Division by (1 + PFM_0). = | + * +-------+-------+------------------------------------------------------= -----+ + * + * CSR_1 of Tegra264: + * +-------+-------+------------------------------------------------------= -----+ + * | Bit | Field | Description = | + * +-------+-------+------------------------------------------------------= -----+ + * | 31 | ENB | Enable Pulse width modulator. = | + * | | | 0 =3D DISABLE, 1 =3D ENABLE. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 30:15 | DEPTH | Depth for pulse width modulator. This controls the pu= lse | + * | | | time generated. Division by (1 + CSR_1.DEPTH). = | + * +-------+-------+------------------------------------------------------= -----+ * - * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. - * To achieve 100% duty cycle, program Bit [24] of this register to - * 1=E2=80=99b1. In which case the other bits [23:16] are set to don't car= e. + * The PWM clock frequency is divided by DEPTH =3D (1 + CSR_1.DEPTH) befor= e subdividing it + * based on the programmable frequency division value to generate the requ= ired frequency + * for PWM output. DEPTH is fixed to 256 before Tegra264. The maximum outp= ut frequency + * that can be achieved is (max rate of source clock) / DEPTH. + * e.g. if source clock rate is 408 MHz, and DEPTH =3D 256, maximum output= frequency can be: + * 408 MHz / 256 ~=3D 1.6 MHz. + * This 1.6 MHz frequency can further be divided using SCALE value in PWM. * * Limitations: * - When PWM is disabled, the output is driven to inactive. @@ -56,6 +94,7 @@ #define PWM_SCALE_SHIFT 0 =20 #define PWM_CSR_0 0 +#define PWM_CSR_1 4 =20 #define PWM_DEPTH 256 =20 @@ -418,10 +457,18 @@ static const struct tegra_pwm_soc tegra186_pwm_soc = =3D { .scale_width =3D 13, }; =20 +static const struct tegra_pwm_soc tegra264_pwm_soc =3D { + .num_channels =3D 1, + .enable_reg =3D PWM_CSR_1, + .duty_width =3D 16, + .scale_width =3D 16, +}; + static const struct of_device_id tegra_pwm_of_match[] =3D { { .compatible =3D "nvidia,tegra20-pwm", .data =3D &tegra20_pwm_soc }, { .compatible =3D "nvidia,tegra186-pwm", .data =3D &tegra186_pwm_soc }, { .compatible =3D "nvidia,tegra194-pwm", .data =3D &tegra186_pwm_soc }, + { .compatible =3D "nvidia,tegra264-pwm", .data =3D &tegra264_pwm_soc }, { } }; MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); --=20 2.53.0