From nobody Fri Apr 3 22:13:49 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010037.outbound.protection.outlook.com [52.101.201.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A67D722B8AB; Mon, 23 Mar 2026 02:37:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.201.37 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233435; cv=fail; b=kUYlCljCd2ZmlD2QDSNWcl4InatsC0HHG33ih8y0uYYoCdd5lGDPusAkMRh2hwJmlpATpRuKfXC5oLQ+AIR9Oo1GjKoL3OFL51CM9nbgWLKCQZYZCJ3Eyj7G/J32trJFJx54aKO1JL8P9OjhouKGR4e98IEwtKNz6yfhRPuVF1I= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233435; c=relaxed/simple; bh=gwfZQNWBWxoyNzQ8CFlQALVbozDu4ay9nAB824R2taA=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=U3ic7FVZ1pV1kJ50CYArOTTGACYj5LqJ+K9cTbE+89ajk+o21essDLhyc2sYDVYyMtiLrofQQdQcepoEICMHsCvtIoGTYHzeiqKx6CEtnvKD6FczM8Ebg19NELIaPoxFP3S/st0/aQ8hVXkojmHArIAE8I2GppmMgTtiH29UyI0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=oH6tbawE; arc=fail smtp.client-ip=52.101.201.37 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="oH6tbawE" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=UP2aIIbDvY2HFfVI51cjjTuClm6ptO8EE4iNS8xpnuzWyq/XEdy46ld3WKibmwviHn7HmSuy5hZoWg1NBjfwIeFlC8/UMoaA+MHR065v0ApfE+4m3tb9jFwRthFp10aRLnSjnqFgcdh5Oo6P3wPsQTAs7cYRi+Nlsoj293kc/P+oon7QIB0kcylNNLVnFn9BeW+QgTLpD+9tPQzvDbWs9H+IZXSZbX8KV4YsRUxwNR+8gUZQn82fLIlrBewiDVuAsV0aiWYuvz52B4AbQNAMNCIIwzo+06NVe9wh86RNhSaLaDV483Rm7SwqF51BGD3yfsaHbdXrQnbQAWq8RpNVpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=FQExniY/fbSpmugBiJjHKjENNl0DOkT3zT8DJ+f5VP0=; b=FjPNp0HVYgDx0zamRqxdkbmdaDkZgKaBd7EaDFuRJO8JJzfkpNyC4VgkPn5teBVrBnlXh1zc/A57rxNsD8YX437IJsaHXfdtB+J7KK3rCvN1fPu68dESXhyEcYjwMp3SyGHjOdlzjr+86ohpRF+ZG8TQVHMdiMSvlPTvAO3InBgAj1Pt2D92j9GPwklljlWiPr5p32IwLvRJakl9JkakY+R7X834u8vXH8I6DFg5UfuuaydH2yG3E4YCw2hiVR0NBu3+0n1BvFjXA7rIuo/lh7VRW/fGuFhoBUvb9i/wMyYgrFzsu/AcvgvLur6Q+sx0XsEUMcqaxMvhsB2HIB/RCQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FQExniY/fbSpmugBiJjHKjENNl0DOkT3zT8DJ+f5VP0=; b=oH6tbawERJLxbzhwteOkKDEHT/7ezlnS3cZE7d1CjQxWUN1mX6WwMl2t74qXK4g5loWK0t91wySvRIjSZcZVZFMqb2NlGkgmIeJSe6w0ynehMY7zZV/axkkS+fKnc3Cuvs08OPg4LDPpVomvydJFVJ8XYlinlXmIQwWfr6fzKaCNFoe4MLe6azpp3pcrKR/frTxMJ/c7mHh7c3iOdcLsnFc1LyqP5STq2TwjxIf6QYe9q6C7cW74zIPNAAhXB6YyFPIHbeLDYzGSm4cAltM3uM4H8R86div0wZdgS8xIMTz5gmtwDNKUXikWL9tmOnZRuJg0u0LGiwpva+H39UZ3nw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) by DM4PR12MB5724.namprd12.prod.outlook.com (2603:10b6:8:5f::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.20; Mon, 23 Mar 2026 02:37:10 +0000 Received: from SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017%4]) with mapi id 15.20.9745.012; Mon, 23 Mar 2026 02:37:10 +0000 From: Mikko Perttunen Date: Mon, 23 Mar 2026 11:36:37 +0900 Subject: [PATCH 1/5] pwm: tegra: Avoid hard-coded max clock frequency Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-t264-pwm-v1-1-4c4ff743050f@nvidia.com> References: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> In-Reply-To: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Yi-Wei Wang , Mikko Perttunen X-Mailer: b4 0.14.3 X-ClientProxiedBy: TPYP295CA0039.TWNP295.PROD.OUTLOOK.COM (2603:1096:7d0:7::10) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|DM4PR12MB5724:EE_ X-MS-Office365-Filtering-Correlation-Id: 43088d7e-e634-48c6-6607-08de88851585 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|10070799003|366016|1800799024|376014|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: i6NkVvJzjO+7IoR0s7yYWIqY07dExa7Il3Z+o07eg7cL05l9oLp+lJomkGjU5ARgftE/4PSWjviX+lZK1+673lBmAF0VGOOKInnavqlTkDJ5jT9xbJ9vw6/L7z9qGVRxT1Zf/ICalJuFcgQL0ahutkk1ce1pbpZ9KJ3z+qWLPyPcXEDpifP49VPeVfyaSSp8j2W/4OBqUyaIvBYulDZ+Ec+s//H0Omas/LPws/9Q0PoJNDaLXKfU0pYctQ0m+zH0nRyeJxiTqL8VhkEteqJ/4CVm7EGwBcjDDF5TakhpUnfE2mttooJum5b0h6c3vA4eWeRJHv7Fa3vLqJ6ZFfwasyOGP/D8wCS4W+a2fdyzd41j17zLV7OLfJKJkUgvmuj39AEVb39Mi9TcxXn17pLnJGqNSuRadrOUaQcoJ6+HgKMkWPu9Biuw+2/Y6pm009nhz2x4ZgAvjnczAIcZuqujuTif7a+vjiBR7/2xsfFTDTiDVoaeF2vRcB7LofpN1+5iUCvnObmtZhL5vJgfrHi+8UdGUtnoKGuOaJnDm1U8l0VNAwwAqgSE616pm+PVaIDOhoEfmzmkwtP70/b4BHN6SEk9ZpT3xMzjYZa3hST8v2R9qLRKTQn9a4TbwUHglAVoEso+fg5P/jV+j/iZ5C9DMLqGp6tmwBHN0EkN9TBgOwpzmR7jIuvqGfJR9o4A5r8TXm+MjIVsCjTrSDj5+4KCrOJryr/gwN8YBVsT9MKp7y8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SJ2PR12MB9161.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(10070799003)(366016)(1800799024)(376014)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?S1VYeXpKOVVaeW81bGNwTWxsYkpDc21ieVlkSDBpNmQ2c2RjR21TODVmYlN3?= =?utf-8?B?Y1d5eXhqUUVVcUQ5NzduajdLSTlDQWRHQ3dleUNqMGwwbnZlblRrMm5iOU15?= =?utf-8?B?TFE5bGpyc05vNHprU2VucSsxakVPaGZCbEdkQ2ltR3hySjNsL1liVC9zUEwv?= =?utf-8?B?L1FqYXJOcnk3TzArTjhhQmVxMDBZVjVGbCtoZE5ycGJDQjV0WHIvUG1JcEtj?= =?utf-8?B?UGV5eUZzQVp1TlJPdlc3NCtDajdBaldFWnNIdFIyQW1LeW9BNENkMXBTeStv?= =?utf-8?B?NkNPSFU0UkNaU3pYTkV4WExmMnQrS0k1QVU3bGhiQlZvUktFZ1BTOHpuZ1J1?= =?utf-8?B?V2FtUFM3WVhGQlo1QUh6dzU2WjNpenJqWllGMkdVVzFnbGxmaWErVkZHZ0VE?= =?utf-8?B?V05QSi9UcmFDdUcydWwxZmFxVHFhekdXTldNYm1MNFdNVmRRL3cwaTBYcTQ5?= =?utf-8?B?YVNheEd2cis2MzZLK1dPSlU5RTh5WnVZOXNNd1JneTVmbkRIak1IcTdGN20y?= =?utf-8?B?bklUMDBEWG1meHJIZktuZ004eVF2bEFZNWw1NUNTby9HaG9LTEVyTzh3QllU?= =?utf-8?B?QWpCeXZoVVByblZDMGNxNFNIRTZjdTJic1lMTW84SkxqczQyTXpVS2FxU0hU?= =?utf-8?B?MnNhRG50SzRtU0ZnS1F3OTFDTWJiLzFlSDVRNnIxTVNnWGxRVkY0ayszU0FR?= =?utf-8?B?bDBKeVB5M2RzeUF6QnpKVHJ1bXZPRnp5Zk1MeU5ySEpmd1JHSFlVbGpwZ2FZ?= =?utf-8?B?Tld6S21sQjdKY1YwcTNhRUg4VnBOTGNSZnZWUlVUU1QvTlJUT0srQzcxOHNM?= =?utf-8?B?MVpmY0NLNGVvSjUxMEtlS3VYT3hhb0RSc05ZZ2diM1owRXVtaDJLcGNMTjQ4?= =?utf-8?B?Mm1DUHJ5SU1tdUltMWJUTGVuUURwN1haem1kYUhrM3o5NVJWTXVibjF3RCtE?= =?utf-8?B?VjlqZkxUbVFKSE9NNWNHQmRFbVRha0RVY3ozZzhQK0g1ajZjVEZ4Nit1NFkw?= =?utf-8?B?ak1KcklQSGNwa2pPbTZUMkF3NHM2U1ZSSThuTzdnWXF2OWdYOFQrenk4WHhl?= =?utf-8?B?bTVteGNyQVF3ZlB1U3RMZHZUcDhtR2szdHZpMHFZZjMvQ01lazR3L0lMVGpM?= =?utf-8?B?LzhRaFBuWTBRRGcxbEJSNzdEbTBiUitwVjZPL28zd3BjRG1qWUs2c24weHQw?= =?utf-8?B?U2k0MlpmN2s2bStPblcxTGJBOEtTbENqMTJXSmZnUWZvZXZiQmtkTFQ5UjJ5?= =?utf-8?B?WW81cnE1OVh1cWhRVkN1T0RmOVBNRDJ5QnJVaUhxeVR1Wm13U0d1TGR5OUpH?= =?utf-8?B?ZTAwQUp3VXdpUXcwQ3FLaFl6aFY1djFWdmwvcm1RWnpaM29qWTJSRTQ3RVZ0?= =?utf-8?B?S0swS3JuZEdrVXk1TW5vOXI5YkRCeGg1UnhDSzVYblZVOTJkd2MxMG5YU3Fh?= =?utf-8?B?YVlVc3ZqYU1ZUlBHbDF4OHZVT1VrbW9NaXhPUCs4ZmlnMzR0RmdKcWJNWnJU?= =?utf-8?B?dkZvRHZPMklla2hTZWo3NlI0U0E5VFlRZys3WWdYZVlGclFzUGN0ZWU0NmhE?= =?utf-8?B?bjVFRzQyeEI4cTdwNjlta1VadzFaMGJ6RG1FTTJGa0xBa2pPci8rN1NIM1BZ?= =?utf-8?B?eFRiQ25DV2duMGt6aUtNUkpFeEVLSE5LdWZzaFg0OE1uZzYyMWRyM3VMKytI?= =?utf-8?B?RlhqUEtKSXV2ZGs5YndMSyt1ZkNIblVtWnhOOFQ0YkRPem1obk16N3VRbVVQ?= =?utf-8?B?Ny9yNEVSbEhKOVplRVJZL0pVYy9Uakw5TkkrUExPTkNlay9jL0l0cGlpKytq?= =?utf-8?B?TjkzRThONEd3dUJ1QXFnZHRnNWhEVlVManE2ZVYzTXlQWWx1WkxkQUp1Q2NL?= =?utf-8?B?dnZXblIzV3pidG9iMXppUDhkRVBQaHpOeDlpdnNReGV1cTExNVRPSlVHemMx?= =?utf-8?B?dExpMHVrZDZFSStVTkdGbnQ4R3VKeGZCYmlvTFVVVWxTMk1BMlcwckxCTEhC?= =?utf-8?B?NnY0SmpWaTROS0UvaHd0dHZYNGpPRmFxRnVnK1Y3WVZVSysrWDhya3NhZ1lm?= =?utf-8?B?dHVaaUc4QTgyYXA4S1FHM25jbjYxdEhheHNaWmlXZHc4bGtkbFc0V1djUFkw?= =?utf-8?B?dTZoelNsMXhUd3hBOG1xeWVJejBKbVFnSUJrRk43eUFGU0ZMazJ0WCtOcmhO?= =?utf-8?B?MnVRRXBaV2hWYmtUZklPdGU1cmpZdS9WZGdtNWw5dnk2cEU0UVg1R3piRm9l?= =?utf-8?B?OXAyaWJENHlsaTVOcnZiOTdkazRWMGhHTWlyaVRxUGZ6cm9aMzlvclc2Z2o2?= =?utf-8?B?MCtnWFkrSlFXeFVRanprZ0tMazdNTGlyMU43M2ZEYjRkc2VCTStqVUFZamh5?= =?utf-8?Q?AEc/2PEPoGqj+s0NUvAZ7lWK2+JZdCF/2rPch51YNl8AB?= X-MS-Exchange-AntiSpam-MessageData-1: 9jU/iGIOl7xn/Q== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 43088d7e-e634-48c6-6607-08de88851585 X-MS-Exchange-CrossTenant-AuthSource: SJ2PR12MB9161.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2026 02:37:10.7005 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: l+ZyXVTHkDSuSdW8YQheQAxZI/yefvztm7T/mrRf3McJdo8xSopCglyfjxMQk5qwv4yXaabvWrCGeWjcooTGmw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5724 From: Yi-Wei Wang The clock driving the Tegra PWM IP can be sourced from different parent clocks. Hence, let dev_pm_opp_set_rate() set the max clock rate based upon the current parent clock that can be specified via device-tree. After this, the Tegra194 SoC data becomes redundant, so get rid of it. Signed-off-by: Yi-Wei Wang Co-developed-by: Mikko Perttunen Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 172063b51d44..759b98b97b6e 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -59,9 +59,6 @@ =20 struct tegra_pwm_soc { unsigned int num_channels; - - /* Maximum IP frequency for given SoCs */ - unsigned long max_frequency; }; =20 struct tegra_pwm_chip { @@ -303,7 +300,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) return ret; =20 /* Set maximum frequency of the IP */ - ret =3D dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency); + ret =3D dev_pm_opp_set_rate(&pdev->dev, S64_MAX); if (ret < 0) { dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); goto put_pm; @@ -318,7 +315,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) =20 /* Set minimum limit of PWM period for the IP */ pc->min_period_ns =3D - (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; + (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1; =20 pc->rst =3D devm_reset_control_get_exclusive(&pdev->dev, "pwm"); if (IS_ERR(pc->rst)) { @@ -397,23 +394,16 @@ static int __maybe_unused tegra_pwm_runtime_resume(st= ruct device *dev) =20 static const struct tegra_pwm_soc tegra20_pwm_soc =3D { .num_channels =3D 4, - .max_frequency =3D 48000000UL, }; =20 static const struct tegra_pwm_soc tegra186_pwm_soc =3D { .num_channels =3D 1, - .max_frequency =3D 102000000UL, -}; - -static const struct tegra_pwm_soc tegra194_pwm_soc =3D { - .num_channels =3D 1, - .max_frequency =3D 408000000UL, }; =20 static const struct of_device_id tegra_pwm_of_match[] =3D { { .compatible =3D "nvidia,tegra20-pwm", .data =3D &tegra20_pwm_soc }, { .compatible =3D "nvidia,tegra186-pwm", .data =3D &tegra186_pwm_soc }, - { .compatible =3D "nvidia,tegra194-pwm", .data =3D &tegra194_pwm_soc }, + { .compatible =3D "nvidia,tegra194-pwm", .data =3D &tegra186_pwm_soc }, { } }; MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); --=20 2.53.0 From nobody Fri Apr 3 22:13:49 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012045.outbound.protection.outlook.com [40.107.209.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04C6C2475CF; Mon, 23 Mar 2026 02:37:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.209.45 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233439; cv=fail; b=QiHTLQuZ8MIoeColV/s1lfR0TCvA6eVlMC/2ATCUJmTCuMs4yd2ML5h4iaSM2kfGORf/i/Hz0ZQChb9RiSRX28wnLNRmOiKNrLikj2AwZcvrU9k2URTYJzTqDNniGFh+FukSWyQEVdfBow3YxoYKR1EeNvUWUzxDDDjoXlQY2Gk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233439; c=relaxed/simple; bh=ucV7O3uQ88HeCUavFZaczBpruvo2XmgQ0OjBCZ3wa2E=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=k2TNE4KqGO4WWF8JK5BTZ3olI8c8ibI4Jv/97iMiXD3pRC+b2h3qp735SnTESd/dW2GDlW+6HlYgzsbMydd8mvNOWy/JlnEEM+YEeWMVmjuhEVEbKe79GCffD5O8nNEneeEa+/U9Y8Z87m0Sgn1VDOwCXF4ZsU25/Mxm5duj1K8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=b+YA33mk; arc=fail smtp.client-ip=40.107.209.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="b+YA33mk" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nOU1qEoAFlUkzuezGyx7Rmnxg7m12sFUYum46y+GSYLK530Cmp2pzKokLFqMt2eyLvB+wtHRCYilE5cbNG0/hkLly13Wpq8Pv1IaHPauX43WyLB0H8cMCD4yb9jLVmWm/ZRC28PPx+vvusPBsVJuReoBi0yEOoP1L572oVKV8FzKFkqZNUGz4D2CG97KNISPaMXj1pkSBoMeJGBLlJgHsNR7nDvExoIMnRndMfefC7xNcX23YjluwdXDNDKRJx2UJV7muvRTsY0/gy+ZZII+WlvZdBe446T01OJyoevDTyIO1Wte0bXqAUN6d7vE9F/CkpIiDgEs7PvpeIGb5s5FQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yg808l5jGFqdOjNqiqmM6dwsAJWgRw49wD8NvoOW2PQ=; b=Z80W/B+hS+KoLZGa70R4SHDZQ06JdwOglO6yVi1c41EJJ9uijjX6SRolEuFgV2icYnFqUyZ/FcYQzNLDX7P6mj8q88UwVkktinbVWApV/OeBusvYe/6i14ULHGj4h3tJnQmugEu2m5hymAH4qsmY9MObj4hyxeAY9wtLzrS7Tbmln6X9DaLIEZRfIUwLiOlVO1nH/ACPC4i+3XkN4ftLGZsukm9rdwyf1D9nz4BgUg5h8yvgq5wnjiWhExe3+adbJQsFB6GtBPP9oB2573Nbl3SbNDf0OiKN7EwtywswBdT22jQMy9oTRGad5uP9eQChPiv1KgAGm50lD2FeJ5ieQg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yg808l5jGFqdOjNqiqmM6dwsAJWgRw49wD8NvoOW2PQ=; b=b+YA33mkRcXnSkCc+XQCZrd0ZHwumxoRcHYqnz0OQUYaP+WzNNFA1B7Ow3xJvCLAVVbTM9r/6G3dWHpFhb2SEWNvyYnpm5YQv9RxcDZMfgCUZY1jCio018bxM8Mam6mLRSpr8Nyk81lLlnxbCePMfFAMUrX/8hL/F3OmZUMJ8IpUEXME7CRACaqN+/kNQtMHUJ1+RahOFFFtYMHpzmmqoS6NecTQlXZbWQq8+SsuDn57wsI/mruMAwshCDSzgMBY//2i4Hz3Hb1NCSAs4d1dnpzIKXL+QtCgyHZ/+lTuXgBNTLBnWtkQnOmdPM3vapeYRYFaovtca+Er/Df+NNad0A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) by DM4PR12MB5724.namprd12.prod.outlook.com (2603:10b6:8:5f::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.20; Mon, 23 Mar 2026 02:37:15 +0000 Received: from SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017%4]) with mapi id 15.20.9745.012; Mon, 23 Mar 2026 02:37:15 +0000 From: Mikko Perttunen Date: Mon, 23 Mar 2026 11:36:38 +0900 Subject: [PATCH 2/5] pwm: tegra: Modify read/write accessors for multi-register channel Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-t264-pwm-v1-2-4c4ff743050f@nvidia.com> References: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> In-Reply-To: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Mikko Perttunen X-Mailer: b4 0.14.3 X-ClientProxiedBy: TP0P295CA0032.TWNP295.PROD.OUTLOOK.COM (2603:1096:910:4::20) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|DM4PR12MB5724:EE_ X-MS-Office365-Filtering-Correlation-Id: 09466213-d911-4459-3a5f-08de8885181c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|10070799003|366016|1800799024|376014|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: Ic5odF4nAPmThmyegCwN+hY9PUae47FkQmVnqDu5MiRSCYTrPjYSdbcFwSRZsugPEaCmszLvJmITd2GKaf2oMs3kImF8Uolc/nETQ1rspQbedzvAK+SLzcanvp/CNOMJkZYZWJi4V6IXfTCCB98ZCFL69yN+hobOPuD987lG7OYBpTZ9T6vh53QFsgKFP6Y/UKIXg/BK24E/lIOrZR5clUd7E9xEYja3pG2qQFyCD18HmMg60vYGucp1zXkdQHzgKQoNhsYs//kKfS29E7pjmlgnv68pm30sD8RMg29V9DzPJuj6tdJd7vVCh7L4Y06HXncKfQkhvK7GBf7heQUHb2ttmTT6k45bdCwjMBjmfoRXd4vM9LCu9yXt+fFkOKxuvPG/wPoNOb+GsJMMtQCmT8UB2QYSdnCtGRxQE/cUSr5XQaOliBsN4QZOlQp0CeZKhpd9OEUQtcie0k4oEUO8jXHL4QuuLQ8JR6xEJOrcsILnjbORYWMX6crzZAQbPvJXYq6zDpXIX0s6Ms/4j+7/yrVUbkl4Kgt4VnMYUM+ZJXBeh5mkFqkZo6++Fir7nVlb1aBp3xtN4+mUW102Yxnq33ldqHEnSD6AE8h/rgP13faXhLeJ6el5qOBFRggCEgT8N5uaC7+op540ItGdOu8BsP2LTnJT4x2HhSrPnB+huPCVO1dc05bpq8k80EibZlgzpev0kvciAJoyjElLGVnj21M7W1K3IMsw9SCd+kdYHEc= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SJ2PR12MB9161.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(10070799003)(366016)(1800799024)(376014)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?WjloZVVNUy9NMnJRUVlaQ2k2eU9FU0o2d2lEQ1dxQ08rZFB1Q2dmbzBnZ2Yv?= =?utf-8?B?bUhpUXpNTXEwMDdoS1VKNXBzNkRsK3p0YUVWNHVwNnlkbVpCeWp5R1hBcnBJ?= =?utf-8?B?eERaZG9tempuRWN5dEtzQVlFaEZhT3pDcE1hT215SEt1TDBFVjU3a1F3ZDRs?= =?utf-8?B?a1RCczhuNUpmNU1HQ1Q4RzVhM0Z6ckcvelNJSk56SEVCMzc1RTZTRmloLzBT?= =?utf-8?B?WFY4SjR0Ui9hcHRJUSt4T1p1ZElpRTFQR3MyaXlhYlh0WG83Z1dLZ3Q2dGJR?= =?utf-8?B?UEY3bFMvVDA2YTRCT3pvNXdwbzBUcm9kMGVyS2V3NmluUmVabWtzN0xRN0FH?= =?utf-8?B?QTFndVdzNU53SEt1VE5UOHR5ZXZxQ0h1N2hiMEFMcjJVeWxtWFVYQnQreFV5?= =?utf-8?B?SStpQkgxeEdFMzhOUzdlVnA2SDVYWUp1Y3FlU1BRNnJWOTAyYzBnYXQraDhw?= =?utf-8?B?c3RIYUVyMWlVUEZLWlRXd092MSt4MHZTaS8wWFRrc0YvQTY3L2ZSb3lkdHAz?= =?utf-8?B?UTJrV0ZFdHVCd0pnQ0c4L0F1T2xHWDFSVmFkb2NDd1JoQ0N1ckMza0VJZ25q?= =?utf-8?B?ellLYUVmWmIwaW9QMFJQRCs0bVdzNEZYdjUyNU45RWt2ZzJWa0tMUk81NzV6?= =?utf-8?B?ZVJrUnpRUE1MS2dyRnBicEVZWU04REVST09wZ1Y4VUF4MWxGRXJqQ1J4NkFw?= =?utf-8?B?Q256a2hTMW1BRHR6eEszekhsdXU0VXVncVlBOWNOQlRTNm9EbnJrbjNNWS9u?= =?utf-8?B?YlVxMzIraW5QT1cvQnRJTXdjSWQyb3h0TXI5RFYwQVlaakhxc2UzYUFOYU82?= =?utf-8?B?TndNeGJSeXBPNEMwSXlyUjBGdElMSDMrNE9tS0hGUWFHMHJDSXZHQmh0RW9T?= =?utf-8?B?Q0ZCSjZTWnZTenk1SVo3VHlJdnBHelMzRGk3emhpUmRKTm1OS3Jhcit2cXlr?= =?utf-8?B?WTNVMW5oRi9RM1RiK3lYeDVQKytvL3BRZ3A2SzJlSzVPa1RZMGlSTlh6N2Fn?= =?utf-8?B?TjJ3a1hNVkNtdUZqaUY5dWZ5WFdjcDRTNGErbFVTalJCN0c0eTFOMHJCUThT?= =?utf-8?B?VFpQc2Fuamc5NlVkWW9vTDFmdUdMb0pYNEVhUERONnR4N0ZFUUt4VzJvT1A1?= =?utf-8?B?MktjL29IaFZqdE10ZlRLb3R6VFl6ZEc3UlV1akRqaThYS1M2dmxHQjlIdFhE?= =?utf-8?B?QmZXNHlUSU5hV2czMCsxUU5IczI1TFpzNnlnUnVxNFZodU9nR0JLQWErWVJF?= =?utf-8?B?aEl3enhmNmw4Y2l1c29WZkhzeWFjRTVxSWNxbVlmcHI1czlDY0pwNzVPUzQ5?= =?utf-8?B?K2E3NFZGMnFkNTlicVRZdmVSUmtRTkJiTGVzbnlrTDhCMUtZZjR2YWJNRWFr?= =?utf-8?B?MnZXS0JRdVJoaGl3cUNJZlRaVEI5WGVIZVpNaFpoTlVOL3FuUjBvVk1UWVlu?= =?utf-8?B?V0IzNEtaUkN1Ty9tUWZMN0NPODBCdEFCay91SjYzRXhWSUFJYTd5V1RvZFZF?= =?utf-8?B?aVd4KzFYYU1nM05jeDlGQi9LVWs5SFRnelBmTzFRS2ZhOGRMVDU2eWpuazM2?= =?utf-8?B?dXRkNjhxS0VyRlpIY0hSVy9tRDFQb2JjVTZnWTBySHBPdCtKa2wrbUIzWi81?= =?utf-8?B?UkFleEhxNmFXMmlVMzNJbnlUQkxTcTN0RDZrRnFyZkxYSENvZk15TGw5S3JD?= =?utf-8?B?NXRPdG1nZ3c2dDVEOXRRTUZGbXErZ3JxQU9TaFhITDlXZDJKMDR0WXFqZDVv?= =?utf-8?B?UHJOd1o0cDdKSHVzeEZOYTlwOVF1NWVwOXhaTzhYOWdjbEtrMEdrRkVBTk83?= =?utf-8?B?NDhkRURjSHBjNkVISXA3UzAzbUFUazlYSE10Y1g0RmhBQ1J3VWluaVlxRDhD?= =?utf-8?B?YVV6RVc4Ky9UQlhkMGU2cFF2Q01XdmZKcGNScVlWRzgxc3NNSWk4WWR6cHRj?= =?utf-8?B?NGhFaTFNRU1tT21rTlhjR1dGVmRrZW1LRzkwRnkwTks2S1FNVkthdnBCckdn?= =?utf-8?B?K1ZidGtZUVZ2N25VWTN1aC9pMUEvZFY3V25oWjY5NVhKd2EwbFVVVjNvNUp2?= =?utf-8?B?dUptVjV0WEJjOTFsZWR6MWRybGtjcDZhdW9HTTBpdU9rbTI3Uk5sbWZqN2RT?= =?utf-8?B?UFF0dEVVTFBPNnJqSEtQeHRCOTNGYVlVendsWEs2bmZiZUF2SnhxbCtlcW9y?= =?utf-8?B?eDY1eVJDeTVEY1R6bFp1RUJ5QWtrN3hQU0cvSW5HQ2JWRmtEYTFmRXNYeHZv?= =?utf-8?B?cGttWUZnc3YrVmJkSUdGalZHVjVEQkM2c1htMWJlZ0tZN3dEWTRvVHExYzVv?= =?utf-8?B?S09FK2dnaWFZNXJNb2VrUnQwSmRsVGIvT1FMYUxPVWQ0U05wMmt6UUFUUmxr?= =?utf-8?Q?ETtHxDertPTuAiyj+g3o71OgCM1JcWs7vE08pYuRXqIL0?= X-MS-Exchange-AntiSpam-MessageData-1: T1McualNS8Y1CQ== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 09466213-d911-4459-3a5f-08de8885181c X-MS-Exchange-CrossTenant-AuthSource: SJ2PR12MB9161.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2026 02:37:15.1948 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /gCRZDxw0OipPt31yreeH25KctqP3opfB9qH3tlEhSohB1C2ZPBklkWzE/ZF1MkZqfiJcBDR9rEP0j7RBZkhow== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5724 On Tegra264, each PWM instance has two registers (per channel, of which there is one). Update the pwm_readl/pwm_writel helper functions to take channel (as struct pwm_device *) and offset separately. Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 759b98b97b6e..cf54f75d92a5 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -57,6 +57,8 @@ #define PWM_SCALE_WIDTH 13 #define PWM_SCALE_SHIFT 0 =20 +#define PWM_CSR_0 0 + struct tegra_pwm_soc { unsigned int num_channels; }; @@ -78,14 +80,18 @@ static inline struct tegra_pwm_chip *to_tegra_pwm_chip(= struct pwm_chip *chip) return pwmchip_get_drvdata(chip); } =20 -static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) +static inline u32 pwm_readl(struct pwm_device *dev, unsigned int offset) { - return readl(pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip =3D to_tegra_pwm_chip(dev->chip); + + return readl(chip->regs + (dev->hwpwm * 16) + offset); } =20 -static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offs= et, u32 value) +static inline void pwm_writel(struct pwm_device *dev, unsigned int offset,= u32 value) { - writel(value, pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip =3D to_tegra_pwm_chip(dev->chip); + + writel(value, chip->regs + (dev->hwpwm * 16) + offset); } =20 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -194,7 +200,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, } else val |=3D PWM_ENABLE; =20 - pwm_writel(pc, pwm->hwpwm, val); + pwm_writel(pwm, PWM_CSR_0, val); =20 /* * If the PWM is not enabled, turn the clock off again to save power. @@ -207,7 +213,6 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, =20 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); int rc =3D 0; u32 val; =20 @@ -215,21 +220,20 @@ static int tegra_pwm_enable(struct pwm_chip *chip, st= ruct pwm_device *pwm) if (rc) return rc; =20 - val =3D pwm_readl(pc, pwm->hwpwm); + val =3D pwm_readl(pwm, PWM_CSR_0); val |=3D PWM_ENABLE; - pwm_writel(pc, pwm->hwpwm, val); + pwm_writel(pwm, PWM_CSR_0, val); =20 return 0; } =20 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pw= m) { - struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); u32 val; =20 - val =3D pwm_readl(pc, pwm->hwpwm); + val =3D pwm_readl(pwm, PWM_CSR_0); val &=3D ~PWM_ENABLE; - pwm_writel(pc, pwm->hwpwm, val); + pwm_writel(pwm, PWM_CSR_0, val); =20 pm_runtime_put_sync(pwmchip_parent(chip)); } --=20 2.53.0 From nobody Fri Apr 3 22:13:49 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011024.outbound.protection.outlook.com [52.101.57.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE9FD234966; Mon, 23 Mar 2026 02:37:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.24 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233445; cv=fail; b=jYbMyoyCrgLmy07Dmwog1ck07rl5l8IBRlRUsbe34+NADHLn3OUwFY+jrGKj3SuPFPKl9/uZsXom2dfXgg0FwWSVE/uudvgOegCNtqo1b3R+p+565H3KPigzdGJp3R82fHoAAlkFBMJrcTgxh5Hoclr8ddqJS5p+uJ5WErwfL0g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233445; c=relaxed/simple; bh=Evj6yJSB0LLQL+CIC5V2U8+LZLkz/oljN2lXio4LwqQ=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=EeNY+idOb4hN5RmojJkYjqKA8kdEzZigIIdFhkaLwF7wmkR8KSJvLhO5yO9bDNc/mTNJEc0kGB2sxUbbrflLxT37D3P7HEsztPIVPE6ElmztS13exdwIPdHam/p2M8GI+9XH0scmAdxR54cG3g1dDbi89nmcOdfntlpC3HDLKhY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=lE/D2RX1; arc=fail smtp.client-ip=52.101.57.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="lE/D2RX1" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Hhm+7GoUJ0E6U7dAa4BTMb6D5tn8i/r7V7sRIH0eRe80XfXGb7+uJZlm1mNWLKJqAAYLYDElHVUIk/I0RHbu1GkJcCAMUHcNZdXMqKuouWvVSOObl0bgjDobkMAHDq6XovUYCVQ+X4nBXqQBNn76CWhevOXzDwOx4AVKI2ocjQVZzHxpSNUhNsL7rbV+1yN56XEXM9qSG1eW9acrUKRuhobtf8w4GN6EVrX5It/pmJkz3fEnq+g14xbOvWNACybX2eFMF/Lb3G84QO45wAYOoXJW+Ww6DIbgLVfzVknA7FPRAsyOSdhHdp64ixfJFvaTvDbli5gddwP/SrRBWmwBTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=DD56M22Y17aXtRpKBTowRAmFt2qj3NH7Zvb4xJmEOR0=; b=Of5UJneLhcJBcDOcEg8wwfEYNdBbXaQnlfmPaW+kaiL8kwLlf+QT6I1MskLJw0gBa3rrdEbxkTQbvXgS5zXKtgXNfVlEyWvCkOtlla+VrruGcePIisnHSn7Moc8IPExJEX/sw0egcmwwyCr81deUK5yWalaiLuJEDMfZILlneNpnWDLkOgPkVMTLn/8PiTecXXUwYLjh1HpmPNLKjRlIqSJesOd0pVEoG5uLdP3uehD9s6P0nbyYbStvKskB0DiF5+/suYAhqZYy8yW0+iQQ+Gbejqv4m2co7v8ypcFpMwtrOEyfUHLn5ZnYDrYnCGLUk4V4dhoQyujNxiEm7MieEQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DD56M22Y17aXtRpKBTowRAmFt2qj3NH7Zvb4xJmEOR0=; b=lE/D2RX19f/ucZ1bh3L2WiyU9A/YFGXkVAL1vn1PLmlnQz+nc1l2dXzGjaaG4N+Gg0TporwIIR1GFUuRLlaKzUlA/17tYdAikvTZJ0+z5+YeojTnLMsqGMYSGy2ShmRmq14uzFOgCqf98U2SmlrYSaB78z36qPWDsAHY8Ut3WzZ3M6lRc8mMR3PbntWRiaN6N7Sc88ZwrN2dIdh3UQVzTD6k7WwMKSfpnQsJynoK9gVpZWQKw3zNccQjZc786C2eOOvCb2MXSDVYFdFROlHdnLqUTn4+eCnI7kNN6B2MMDWw6/nC/YbbHjsao0KsZjKIvZS38oLGx7fgP4WSZkPU/Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) by PH7PR12MB6717.namprd12.prod.outlook.com (2603:10b6:510:1b0::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.19; Mon, 23 Mar 2026 02:37:19 +0000 Received: from SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017%4]) with mapi id 15.20.9745.012; Mon, 23 Mar 2026 02:37:19 +0000 From: Mikko Perttunen Date: Mon, 23 Mar 2026 11:36:39 +0900 Subject: [PATCH 3/5] pwm: tegra: Parametrize enable register offset Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-t264-pwm-v1-3-4c4ff743050f@nvidia.com> References: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> In-Reply-To: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Yi-Wei Wang , Mikko Perttunen X-Mailer: b4 0.14.3 X-ClientProxiedBy: TP0P295CA0027.TWNP295.PROD.OUTLOOK.COM (2603:1096:910:5::14) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|PH7PR12MB6717:EE_ X-MS-Office365-Filtering-Correlation-Id: 294fc68c-63bb-4c12-ff46-08de88851ab4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|10070799003|366016|376014|1800799024|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: qauFsl/Bg3c5xjzNWD47XP+sZtUdX5MbxwlHYtvK4qDc9w9slttTP+LMCVpmHGwytrk9fJRUZ3dg8QHNmk18OZDmWH2H2fkZtlS1z+o0OQC0gMHkWdB6kH/+t8AShTKq5NhAxycTH+i2ul/i76gvT49DupmhUx7apub/8aagkdxgxJxxaxQ0f20uXh3Un7qtWGG0ksuEjXKZWiGbXtl5X60/EHiwjFKggxVWqZ0LNdIkqNE9aeugkKq0YmmOdzzfs/e5cC4noemV1hyqRLwfgOV80xV+u/DpZ0xGTO5fiTgdUwERooNBb/qlfE5A1NKQqhvZHZZ/2o+Db2cLdsSLFvW9tCcdcmUOD/Ji7HyvT+AkN5ySZvhX8RXmO13y0IEo0gNaIHpY/xWRGti90SaKN+ZHuy5xchrojNJcIZSHMZDO8gHVs4tMEMrantN9TGCd2vzzJkWUK9yBBftDuzfoeqYYcut7ZTgiAzaRvRJJ1MQwhG26AQPZ4fTL1M0gq+Toh85iYMG3go1KWiynCnaFdJjyAAb/lE7kQbzP6EFdDNyhyQqPLsWpgjI5WHfyNMPNzyJ7FfLUdRt6Eg10iKon9tGbmuZ7K85S8ha7hpg9ux/rVVkFa93j/2zsDB/EvivMd8EcbxJorysDnhz8wCCeeKHuYtwxGPv/8fWWdHCHosg/9RpArsIHpaHqwZYNsovMA48TXnbB+zgve4sMAoZs/gXCuS5fX+Y8wHkZqD0du+E= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SJ2PR12MB9161.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(10070799003)(366016)(376014)(1800799024)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?K2hwbUQvN3lkdlo4RmtpcW90d2MrTm56d09hK0dwQmtIeUo2YmNhZ3hhWUhU?= =?utf-8?B?Uld3cXFHNTVKL2NSL1JxcjA2UjVxNWVJYnYxMHhPMUtteGQ3YW9zNHg5Yml4?= =?utf-8?B?cHdXTXNnSDE0Y3ZKa0ZjeFZ2UUR5VTBidDFiQ2Q2ZHRVTytYcXluNVFydlpk?= =?utf-8?B?ZDJ5WHlmN01MSWtCU09Dd25PdXZuUXhIRG9DWkx6aW5EQlFTY2lRdURZSEFW?= =?utf-8?B?QkhBWUY4M3EwR08vY1gwNXJuNEsydGhyd0pWZGFlM3daWVlUMytGZVNCSGh5?= =?utf-8?B?dHhKanJxN2NtYVJ2d004ZVZ5TGZaOTVxNzdMRElnczBOT0VOM09Jbmw5clln?= =?utf-8?B?OFZBUGdtWFJNV1RSaGJ1MkowZGFXYTJNQVV6WDNxWGhKWnl1aXlDYmp1RCtS?= =?utf-8?B?TU9kYXNMRmZTZUtHTWxWcVFrNkdsNUgzYjYzdyt3ZXN4VDAxZS9hUzBsNjNX?= =?utf-8?B?L1V2YzJZalJ0NzdHTlRHZ1V5U09mQjFONityVkZabEdUR1B1N1drNU5LSUFY?= =?utf-8?B?R2c2cmxQN3J6cjR2Z0FEcU5qRHRIbEIyMHZzbkw3OElic09obVJicVNKSDMv?= =?utf-8?B?Z0ZvZFNBaTlUa3QxUW0ybmlmaXdEUkdKbnUzajAyWHJrZkRVRm5uU2d3cmJV?= =?utf-8?B?OVFVZGI3OEJLR0lGbmpUeElwdDIyTGdvS25vdFVTMDVxcUtzNXBsM0x6OXdO?= =?utf-8?B?cFNSVzBtVzYyeTVhRk1xK0pzWjFQeG1uQkRPOHZsS2N1L0ZBR3hYRnpMbTdy?= =?utf-8?B?K0RCMEJDaEgzbVY4NkhuVEVDTGRUcUY5UEQ5Z1huWkYrbnB3THJNSUY2R0NI?= =?utf-8?B?Rjg1RjNRTWZqZnFGUHNVMGNySEJlSXhEaU1YUmdkWGo3UHZIUE1COTZ2R2xC?= =?utf-8?B?bjA2MWhJZkd4SDZicWd0U3UxR2ZvODVSZXR2MEJNUUtTVGVOZloyWEFtV1Vl?= =?utf-8?B?VFZOV2t5ai9OSXE1RlBZeGVXbmY2c1FBbXg3VHJYZmdzblNaUTJhclA2bGxH?= =?utf-8?B?SW9FQ0htM2ZtYjNLSTlCWWlFT0xJUEdQRDJnUDEraXAvd1ZtOUs1cUMvWkdl?= =?utf-8?B?T3V4R0lTSjJlZ1FSZ2F4UEhjbkJ3ME13bkRwTkNZK1hBVkJLajF5Rm9wOTFX?= =?utf-8?B?SXIweVhaOGtkMGNWcDFEM3hrUWptVHBrN0lDeit1dXl0RUpkV3M3U2FZYnd1?= =?utf-8?B?M2oyNnVtMWlYdC9OVW1GL1orc2YvS1FlbjBqQWM5bjJTNjRkRnV1SHZNZUN1?= =?utf-8?B?SmVlN3M0YitvU1VwY3FIYldYWlNUOUdYL3NkbGlqTTJWcGNIRzZBcVpCQ1FK?= =?utf-8?B?eDJtemZxTmZrZFp2SlVyRnNHY0s1c3gyRDRyY014VWIwTFcrRGVVUlE5bUQy?= =?utf-8?B?M1NNY2J3VDJ5STNidTBURWtBT1hubDF5WDZ0Y3MvTjMrMW1DdGoxUXk2dklL?= =?utf-8?B?VDRsaG5IbGFMbkVwYzlGc3J1d09TMDB5T2RTTzdvQmFtZnFGcm02Rkk0aW5Z?= =?utf-8?B?YkxnRWhNRTVJQ1lua0dtVU1ZYW1zRmVmSmFUb2FhTzFmbEhENDg1aWQ3QlVm?= =?utf-8?B?bXlPZlVSR1NWeFdxcHk4eG5LYUJPS3k4WEdOSXVwWjA1TWtSR3hyM2hKM1U1?= =?utf-8?B?U2F4NXdhR05IN0d6OFNJaithSEtEbkhNSU81Qm8vSGZoMmRWZG05SllKYzk0?= =?utf-8?B?eE0rTk1JeDZ4VW9QRG1NakYvR1dkSHRmVlZwZkJBQWtycGtjUmZqSFBOenFw?= =?utf-8?B?WTBqYlhQMXN6V3pCODZOb0RlekUzY1hsbVNuTldiYTlyWmVJOTBrQlNLUGZw?= =?utf-8?B?Q0JnYjJlUUJCZHpacEhoSmVwaW1rSVhKQjNhWGZjQ0FYa0s1RmIydDl0QWlD?= =?utf-8?B?ZjZBdFcreUdaSEl1ZXl0K2g3azkrSHVJWU10MDVlTEVuN1NaUTdWbHNDZmV6?= =?utf-8?B?d2ZJWkg5TWxSUmxOZEZpd29seW13b2xBUXFPeDBLazlwempWSHRMOFVWbmpq?= =?utf-8?B?MFdvclBFdWZRVDlxa3NUR0orQ1JPcHduTzhEdGI4UFBUaWxzaTZicHpLR2hD?= =?utf-8?B?djU0RnEyOTNSeG9Bb2MyOVVacGIySjVIN2RiU2JpUmsrdDgzNlZCeHU0TDhB?= =?utf-8?B?ZVJyTFV5b1RkWDlIN2hwUExTdGUwOEhGNk80bURBbjhTdWpacnJqaitwMVpI?= =?utf-8?B?SFQyaDV5U1dFQUh1SFVFNE1PSmEyMTZkWWNYQmR1dFBCU1JSaC84SjZhQW1s?= =?utf-8?B?bmtOY1dlSC91dXVaRENpVmtjaXhVNVlxZ2lLNFFMUDl5ZlJjeFRuSjQxdmFv?= =?utf-8?B?ZnViS0c2Rk1HanY0RlFmN3NiaFhIUFB6VjY4bmlId09UK1ZpT3k3YzRqV0pz?= =?utf-8?Q?9E0zlva5/PzmLfXfmWemiwsZIjSkkp/B2bDQ45usoCuUn?= X-MS-Exchange-AntiSpam-MessageData-1: E3HsCRdL9lzvaw== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 294fc68c-63bb-4c12-ff46-08de88851ab4 X-MS-Exchange-CrossTenant-AuthSource: SJ2PR12MB9161.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2026 02:37:19.3971 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: U8M3kCAXNwR0a53a+D0yZHy59EnRGRBLfQS0MTZEcKiviQSvXszjYa09EbnmjusEMMQXTwZizcp0iDhCi1csZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6717 On Tegra264, the PWM enablement bit is not located at the base address of the PWM controller. Hence, introduce an enablement offset field in the tegra_pwm_soc structure to describe the offset of the register. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index cf54f75d92a5..22d709986e8c 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -61,6 +61,7 @@ =20 struct tegra_pwm_soc { unsigned int num_channels; + unsigned int enable_reg; }; =20 struct tegra_pwm_chip { @@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, err =3D pm_runtime_resume_and_get(pwmchip_parent(chip)); if (err) return err; - } else + } else if (pc->soc->enable_reg =3D=3D PWM_CSR_0) { val |=3D PWM_ENABLE; + } =20 pwm_writel(pwm, PWM_CSR_0, val); =20 @@ -213,6 +215,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, =20 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { + struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); int rc =3D 0; u32 val; =20 @@ -220,20 +223,22 @@ static int tegra_pwm_enable(struct pwm_chip *chip, st= ruct pwm_device *pwm) if (rc) return rc; =20 - val =3D pwm_readl(pwm, PWM_CSR_0); + + val =3D pwm_readl(pwm, pc->soc->enable_reg); val |=3D PWM_ENABLE; - pwm_writel(pwm, PWM_CSR_0, val); + pwm_writel(pwm, pc->soc->enable_reg, val); =20 return 0; } =20 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pw= m) { + struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); u32 val; =20 - val =3D pwm_readl(pwm, PWM_CSR_0); + val =3D pwm_readl(pwm, pc->soc->enable_reg); val &=3D ~PWM_ENABLE; - pwm_writel(pwm, PWM_CSR_0, val); + pwm_writel(pwm, pc->soc->enable_reg, val); =20 pm_runtime_put_sync(pwmchip_parent(chip)); } @@ -398,10 +403,12 @@ static int __maybe_unused tegra_pwm_runtime_resume(st= ruct device *dev) =20 static const struct tegra_pwm_soc tegra20_pwm_soc =3D { .num_channels =3D 4, + .enable_reg =3D PWM_CSR_0, }; =20 static const struct tegra_pwm_soc tegra186_pwm_soc =3D { .num_channels =3D 1, + .enable_reg =3D PWM_CSR_0, }; =20 static const struct of_device_id tegra_pwm_of_match[] =3D { --=20 2.53.0 From nobody Fri Apr 3 22:13:49 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011047.outbound.protection.outlook.com [52.101.57.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71ABF265CA8; Mon, 23 Mar 2026 02:37:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233448; cv=fail; b=rfoJalWST2rDKn6eRNNvMOy1bdLFRVUey2hYArx7KxqyMWnzD0JvaRRuMu4Bs3YuPgo+GY26H+QyMWi266i3fMPKT0JSi47JN7DRHQnuYNahkAGNJ7SKh/qvHlxxxMpIvdq6onHVYL7oifxf96FNHk8ydxNmpW4uhKxk1ibBi0k= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233448; c=relaxed/simple; bh=CvEDDxhl1fQITOzJwP9B3ngqq6SfzMFb3/Q7UMCe+fA=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=ekQ3HvDvYV0g0bFGyhz1+lBSXX10eHaM4q5lACHdnLMR0ro0gpI+N93cOLhZzqB4WMXF4K1WdFGuxSyTMoV0VjSu+/2jHTr686d3g2O+pjmzEGo+ARf273ykEvXDgSPhQi+H28kGqBjel5lj+mlh02mhMJFPpVyn74eXds+4xb8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=gP+MDUV5; arc=fail smtp.client-ip=52.101.57.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="gP+MDUV5" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=lWSdaIK+kDLwfjVbTJ8T6Cq/nDo5jHjbLub5YhsocQrM1acOIpJGm4sa7mCmXoqAe67OlWbjcGM3NVx4zdVU6q4tY9BpgvaGzdviTj7scG8nA8d+Ybo5/baL3PewoIAzBH0X2zrvFMCOnP8lT2HTssYxEeIEgWcnbbIWh1ehGhAM3Pu19W22p2kDafwFts9ZY05FtPAQGQYNCadnGy/PlB3WSXqfhTyZiav6pdQxuDo61qimg+SD8q0oAN3zaBTrEmVmcj1l4gUvkB/me549YvIaV9y9ILiuW9qnnfmLIsMUFuZeXAeKT6eI/ZVr71kd3mX8UbjANfswSjET6G9foQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yWTuFH2ku7rYybzhP0qo9F0sgEx2rGXM3tRrGkq4dlo=; b=Ujl1okUZeaZlWJ+nlyfQe1x2NzJfHzSvomCCgxFY44WbRLnHlrkF/0S+tCAAurXX3zDTjPIijGRIYLlki3//whuazpTgoiShfS8XvH3GndPMuS1oUzS3KRijct8Tv9/T5qHFD6DXt+7QGc8KduSNqDu1KvHQCdKEJuAgjEASqHVM8zDsxWOGhdF3MxW3MwQuN5qreTZ0piXpPQdwFkxPdheRoDw9TrTggT8gVBnkH/IUjs0bP8xZYPFBuMOHP9q6h9D2XQHrjkrmuRaeocgE4UKNtEPyphNwf3FE4lZ8N7pKmQL5FEnKbQOL8SW/UDHwgEruv5F1SsMOF+4GZk4FDA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yWTuFH2ku7rYybzhP0qo9F0sgEx2rGXM3tRrGkq4dlo=; b=gP+MDUV5k2uQ7aAACwt8VpsMG94nc7sb9XPUAmsKVnK3o1feY0sCBI/rX5WPZRju2XTa25ihvvEEdHDT9oBDNzbtcVi3+3OibyLxEy/EvggHyreIbiiS0Kd6sgfPwWtUk+KwvygQ7ppv06TPMRk+mKbRABAvK0f86coUmhBKNyQpPtW7gJibMyVR6wWNFy3wQL+y8JeCAdVEHZgVFOgbvsr58qiRNrH0d4YYYGtTGRstuyVKIVOiuKCUgvBDCoe/iRRMlBOdJh9eihQ3jBVpNTUVeXNHCcjrhUHXWTi+N/Y5SNQjjKlmg3NU3B0EpUGUEnx5hKJ/yey0Er18WldSMQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) by PH7PR12MB6717.namprd12.prod.outlook.com (2603:10b6:510:1b0::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.19; Mon, 23 Mar 2026 02:37:23 +0000 Received: from SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017%4]) with mapi id 15.20.9745.012; Mon, 23 Mar 2026 02:37:23 +0000 From: Mikko Perttunen Date: Mon, 23 Mar 2026 11:36:40 +0900 Subject: [PATCH 4/5] pwm: tegra: Parametrize duty and scale field widths Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-t264-pwm-v1-4-4c4ff743050f@nvidia.com> References: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> In-Reply-To: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Yi-Wei Wang , Mikko Perttunen X-Mailer: b4 0.14.3 X-ClientProxiedBy: TP0P295CA0044.TWNP295.PROD.OUTLOOK.COM (2603:1096:910:4::6) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|PH7PR12MB6717:EE_ X-MS-Office365-Filtering-Correlation-Id: 58c85a69-52a9-41c8-c7a0-08de88851d1b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|10070799003|366016|376014|1800799024|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: pRJoywXqCfj18O+TG1SvzS5T0hQoIVSo1hUDHQyRQ2QQY/Z+E0L1Ua2CkbAOxMTzNVgOC+iJIf5EfsOuOgWcFLTZ98KeRNMkRZHIx+lovtyxKUmkQ8SuMk3HyoSzuL92T/8Ngtc++JURdXzskduS4HeL+7el+FQAcbRzdK8jiShmHn9tc15jKNLSu4rxkdbYB0SMdVGltBXHb0Z3cqiNDwhdtzDXh38jNQaHx14Gdll0eezlwoduPpk5EfdEg9ks/0OzFlG42+70ZRvW2cGK+UzyLu/wmoS8Wh+PBSVRC5jfIED4oqVJ1dPFz5qLlp9SbLkJ5mXYXnF/eQ5XiNPjycBQ2higTYO/Yn8Y4I6vzR7g2WSYDQuWha/gAEW0h6uApCpjI4YGMiQUhK1897Lo4AVH8+Y/msqWckKP880fExDMG9cuyRCbP3zSjfFfUYC0U81WV5n7l1++YIjAUwP/F/83aO7KO/1g7Dyu8K5a8a2HHCWi+9hEclriZqXL3BZwEeuo2LkeEXkFruyEow3C0ItYTsKPPoybQHz5vU6zCposRF2Oh5gKBHcz2EHyJOOcm7HgatOtk5bsJ+w1A+gfYiCAtKTDmn3GDeEbOaYiDU93j+DU3NW4XlTU/S/PKtVZyRCmxnhg/uD7forxNNdTgpyRAMzX8ESzsqvCrUTNuMur4qxABzuMGTSgCGb6TOOqcHm6qa9zvMKIKMf0R6Y7+sQkdKEuRsXbS1KHjK23mU0= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SJ2PR12MB9161.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(10070799003)(366016)(376014)(1800799024)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?a2VkQWV2aHlsaldKVWM0ZzZ5QTAxRjNtbGtWWm0vTWN1VDhHT25RWmkyQjQ0?= =?utf-8?B?WGlkSUczWSt4bHpIbWFiOXFpNjVhdktmZTZNdEQ5ald6Y1ExdXRuK0RtM0J2?= =?utf-8?B?VEpLay9GT0owNDRvb2FGcEdPVkh0dit2MFpFbE51QnZFZml2cU8xSFR2UUl1?= =?utf-8?B?Z2dndVFMTVBiTzF5M1VWQlhmc2tyZCtXUmRvOExxVXVGR0xUeXprTER2K01p?= =?utf-8?B?VnFlMDZJSStvY2xtWS9HUVVUQS9aMmhPdHpzdXdDWVcwcjZmRWRQNkZxcEhn?= =?utf-8?B?a2NCZHkzUVpVNGdodmN2Y1dCRUJQUFFPbDhhQzFqY3ZKMlUxeXNEODA3NGdH?= =?utf-8?B?TVZyOFFLSjBkUHVWU1JwSkNmSVRRbTRpNkZJZTFaQlNIaGl5SXhwZmx6QnRC?= =?utf-8?B?UUxvTVlibGNDWWdMNjgxZ3cyTGViVkpWcnNENHJSWnlrbk1HVmNldzFXSzcv?= =?utf-8?B?czRLU1RFQ0g1eDdTQnpwOGp6d2lXVEN6WnhmMjNBMFRzdmMwZi82QzcyS1pH?= =?utf-8?B?T3N4MTR6QnJUZUZGb2VpUER2NlZpSWx6OWQ1ZnA5U2I3SS9IZ2RCcjFHVmlI?= =?utf-8?B?YU5GbFhuRE9SSXRlYUt3VkNZcWJrd3RMZlRyYU1uK08veUZ3K3hMeFNMazBE?= =?utf-8?B?ZGh4NUk2dEpOWWU1MXg1TTZ6akVjYVpSZ1JiODZrR0NsODFtaFFzUVpiaFFw?= =?utf-8?B?MVVPc3RMaHBGZHJIMG1WUFdjcGtMVTRvMTVxSkxpdE05b1RmdjJ2SHpMYVJt?= =?utf-8?B?Um9lZ2lmRGlGM1RHYWNsY0RXMDV0TUpSYzY5T3J5c3BiVXJKbTNEWFU4NHZN?= =?utf-8?B?aEJLRDRuaDQvWU1JTEptamlOQmdKV0JQTzc1bGJDRmxJanZtSGgvMVZlT0cz?= =?utf-8?B?S3BQQnh6bm1CejVGUEFGNjdmUG1qN0NqcXRnZmp0Y0R0blR3T3pGL2JRNERw?= =?utf-8?B?dGpnVnhuT2pqYVBuc2pUc3UrZG1yZ0NibmI1Tit6WVZGWmhmOGh0N3lraXgv?= =?utf-8?B?OWk5QVJSNTFMVXJjVE1KMjE0dmo1c3c5cTZOWTZiQzFhY28vME5GQkF5ekdl?= =?utf-8?B?RUdad2dwRU1ZMVp6UmZCdHA0SnA3S2ZsVkpNNk5KUnJodW9XU0VYOHNEN0pv?= =?utf-8?B?Q2hSL2x3SHVTWlA2MnVyWEVwZ2VHK3BqRnZHQmxobjk1bGRGNWM4U1dFWEE0?= =?utf-8?B?ZVNHRktNMUp3alhVN29kR0ZQcGNHRGNCbzQvNHNsQndSaHBydUtBdUtMTmpz?= =?utf-8?B?OUx5c0tZcTU4d2N6STd2UWtoRlVkVDZxTm5HNEN3SWtTalVDY1MzQVI5eE5I?= =?utf-8?B?SXFKb002ekpaejdwbU1hVDFiNnRkaTRwcXZxd3Q0L2JaZkp2TktiZ1lQenQx?= =?utf-8?B?c0piRklSTDFXYlczSDZNYUNkZXdicjBnNnVYOEVMWnhKa3E2YUpwcWRuVTRG?= =?utf-8?B?QS82b21QTk5Jd1VjVFpLVFVINlprckUwZUp6ZmlwQWZhUVY4RHdwKzMrcmI0?= =?utf-8?B?NHpIRnlKcGpCUyt3UGh3bE1yblE4Q2lBYmhRN1VZaVJ2emhHRStDaERjUHlt?= =?utf-8?B?dmtqN21aYmd3NWp5SlkreDQ1cHpyYWl5ZEJISWF1QWFXV294Ri96SWt0Yndj?= =?utf-8?B?bHBZbmxEMlo0Uk9tbU0zMUF3TmJ1K0ZmSjJzV0lvTk1PaGMwbEV1S1hZUnV5?= =?utf-8?B?VGtHKzZ2UmhvNDlud2wrOUkyeUtCczR2dElKOW1MdDIzdWdHVjYyV0FudVhj?= =?utf-8?B?Q3ZIQ1IycHdndFhWTjFLOEh3UFZLSjJwSnBkVDNRTm1HNnNwd0J3Qkp5QkhX?= =?utf-8?B?TW1yeFZpN1laRlF4dy82QTFyVEV6eWdpNmx5TEs1VlQxZGZySEVzbGFBUHdz?= =?utf-8?B?dVhJa1U1K25iR0lrSFQyTWNxTjMvRFM4QU11K3lKN3NEbytvVEVhK1NKcmxY?= =?utf-8?B?eGgyb2VDSDNibk9HczhGNXZqcktsaElqSGliVytQdGhQeE10MElacWM3U3dJ?= =?utf-8?B?b1ovRjhBTlpGN214Sk5ZTnJVa2lSK21yT000TlRVTmlIdWw2clltK3pQeFZX?= =?utf-8?B?bHYza1pVUW1sQzlHa3lOZ1hOeUR6Mk1yVWZLZ0cxNUV6WEVoRTZLWjVDMVV4?= =?utf-8?B?RnBBSWNCaHRjTGlEUVBReU5jQ2V6ZW05UXRnY2RoK1lLWnhZdEt2ZlY5REdV?= =?utf-8?B?clNxVEp2YlVJaTJQTm5NcG56MS9ld05jS1BIN1F3Mi9GRDQxSDFlVVMyTW1L?= =?utf-8?B?dnN6Y1luWjFNUitlVzBMVlpSQWp0OW55UCtMREY1RjhacW8xcHB5ZGM3Sks3?= =?utf-8?B?YSt4a0JEcENyWnluRFZadnEwR3huQUYvdm5mTzdyU1lMcm82SFpvNkdHL3hF?= =?utf-8?Q?64ZpqKDi3nBf9sd/c/qXDpomnhVmGhFxYK+PTwUTdLV39?= X-MS-Exchange-AntiSpam-MessageData-1: 4BxtZ4O188LhYw== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 58c85a69-52a9-41c8-c7a0-08de88851d1b X-MS-Exchange-CrossTenant-AuthSource: SJ2PR12MB9161.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2026 02:37:23.5578 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5yj42mi4PzZWUOzQ9i+q8DWggmbvHzTqoTJScZiomJEJk6a0exVaJh8gG8lFj2GKA8F1YOMYciEpYosjB4GRYw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6717 Tegra264 has wider fields for the duty and scale register fields. Parameterize the driver in preparation. The depth value also becomes disconnected from the width of the duty field, so define it separately. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 22d709986e8c..857301baad51 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -52,16 +52,19 @@ #include =20 #define PWM_ENABLE (1 << 31) -#define PWM_DUTY_WIDTH 8 #define PWM_DUTY_SHIFT 16 -#define PWM_SCALE_WIDTH 13 #define PWM_SCALE_SHIFT 0 =20 #define PWM_CSR_0 0 =20 +#define PWM_DEPTH 256 + struct tegra_pwm_soc { unsigned int num_channels; unsigned int enable_reg; + + unsigned int duty_width; + unsigned int scale_width; }; =20 struct tegra_pwm_chip { @@ -106,22 +109,22 @@ static int tegra_pwm_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, =20 /* * Convert from duty_ns / period_ns to a fixed number of duty ticks - * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the + * per PWM_DEPTH cycles and make sure to round to the * nearest integer during division. */ - c *=3D (1 << PWM_DUTY_WIDTH); + c *=3D PWM_DEPTH; c =3D DIV_ROUND_CLOSEST_ULL(c, period_ns); =20 val =3D (u32)c << PWM_DUTY_SHIFT; =20 /* - * min period =3D max clock limit >> PWM_DUTY_WIDTH + * min period =3D max clock limit / PWM_DEPTH */ if (period_ns < pc->min_period_ns) return -EINVAL; =20 /* - * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) + * Compute the prescaler value for which PWM_DEPTH * cycles at the PWM clock rate will take period_ns nanoseconds. * * num_channels: If single instance of PWM controller has multiple @@ -135,7 +138,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, */ if (pc->soc->num_channels =3D=3D 1) { /* - * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches + * Rate is multiplied with PWM_DEPTH so that it matches * with the maximum possible rate that the controller can * provide. Any further lower value can be derived by setting * PFM bits[0:12]. @@ -145,7 +148,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, * source clock rate as required_clk_rate, PWM controller will * be able to configure the requested period. */ - required_clk_rate =3D DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WID= TH, + required_clk_rate =3D DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * PWM_DEPTH, period_ns); =20 if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) @@ -169,7 +172,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, =20 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ rate =3D mul_u64_u64_div_u64(pc->clk_rate, period_ns, - (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH); + (u64)NSEC_PER_SEC * PWM_DEPTH); =20 /* * Since the actual PWM divider is the register's frequency divider @@ -185,7 +188,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, * Make sure that the rate will fit in the register's frequency * divider field. */ - if (rate >> PWM_SCALE_WIDTH) + if (rate >> pc->soc->scale_width) return -EINVAL; =20 val |=3D rate << PWM_SCALE_SHIFT; @@ -324,7 +327,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) =20 /* Set minimum limit of PWM period for the IP */ pc->min_period_ns =3D - (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1; + (NSEC_PER_SEC / (pc->clk_rate / PWM_DEPTH)) + 1; =20 pc->rst =3D devm_reset_control_get_exclusive(&pdev->dev, "pwm"); if (IS_ERR(pc->rst)) { @@ -404,11 +407,15 @@ static int __maybe_unused tegra_pwm_runtime_resume(st= ruct device *dev) static const struct tegra_pwm_soc tegra20_pwm_soc =3D { .num_channels =3D 4, .enable_reg =3D PWM_CSR_0, + .duty_width =3D 8, + .scale_width =3D 13, }; =20 static const struct tegra_pwm_soc tegra186_pwm_soc =3D { .num_channels =3D 1, .enable_reg =3D PWM_CSR_0, + .duty_width =3D 8, + .scale_width =3D 13, }; =20 static const struct of_device_id tegra_pwm_of_match[] =3D { --=20 2.53.0 From nobody Fri Apr 3 22:13:49 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013042.outbound.protection.outlook.com [40.93.196.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 726AF18FC97; Mon, 23 Mar 2026 02:37:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.196.42 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233452; cv=fail; b=TWaNnwyqTbzqUGhJY0HxoHoPVjNssRhkll8gFpHZAuoVpSKxXGrWysoS9Hd5s9djSUuPApSJwnhNTTZYg+Xv/TZzFJu9wZy00axshU80rLEDi3hNHDCv1aVu+DO9Ym+bLdOBTSs2Ruk38VD/SntC84BJ4JXCs2nhMs5szFa+bS8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774233452; c=relaxed/simple; bh=/Ta0Axt7KJjBrFu00qLjZJNsY3MmjgJ0zry7Jm+m/dw=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=Ajjp0nqgWjL1fXd+eRgLnzW7Ub8ELpN69nYQr+8/eJfRUE7q9d+haXZCatzpeTDLbB5bzMxhdiNG3AbnSF4j+cyH4suxfJmUFcMnzaH6IXTwb8L8AGzXpnz7vqlEw/V//EkPUkJn7wI2j42gdq92LEZkJO/apaqSiZT3XNjDGpM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=G/HowF95; arc=fail smtp.client-ip=40.93.196.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="G/HowF95" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LGPNrSjvesTciuOmrysndLB51mkFq5gBz2BLo2NWn1N3Z7boMK4RmusizHC/se822fRWpmpSuPDr1GnXFOVo5mTstjBNZQdaJMSZxSHHzPdMFtcRqGgtxyRIPg8qqdyI1RJbN64ZCr0WlCci/y+SPbtArctNFrpaUMj3bF7YCuRKOtCMUxf1k9tdbOC/rjYD3OyOqGlRHS4ExEneihQRA8JZi/SvHJuWdfYl6ZKsukoWHe3r7YwrkfqF9Zr/nJnxkLex70DpAtoZwPdYse1tKrG7MoPvLcV3x9cvvzytS6LYTbi5VkwLtSnymGVP9d2xrz7UgadwK/9qXeuJ4c3iAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6lI5vCtTJRWEYYBs6iFamPe8E0USN1Uctqb9jRn6Rgs=; b=mcqH9O/prxlg1EG5uflHISta/pC4pMMMYKwqp+EryVREuCSyPv9ofO1Cz25dlZJ78O1Hb9uGzpK13Z5We351etyCUUNeCK1PZmTcK8nIIWNrzk/6BU5wFt3WJ1vg+6UMbpYSq81p8dWagbgcC04yKK3OhqucYIjpaVadQqdIQLNN8dqzdE0lcfewAGhB2rmU7Mr+XDUsRRm08afc3pFvYwvj7jBuE+5Mix3/6dsdRJTSDKURPoNiVPSBVwCDaXH7w0UK729Rn/8ef2KhvBaNFDoISicFnUSTND/1gCymGgNAo/VCrV0PxieECG6NFtWaLBEYo4XUgwtBGcf90Gg0VQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6lI5vCtTJRWEYYBs6iFamPe8E0USN1Uctqb9jRn6Rgs=; b=G/HowF95v5RBRblqPnIoTbSyOU+bk6dNF7DVIrBIPJlU1x4s6cvwj1Bd+pWdlwCKRJwSLXC5c6qdbFwKYpeuHg13TppdNNQVD4cK777XKBBeB9H7UjKzXISU0euY117mlgasTmzETmBy8Gge1cWicwvfw1aemduO1tIsEDrzDSQJeuW0CHRouruKOHRwkpS1nNYERtaxqq62uks/BcvvGWuty/KjakyS6wkMcGO2NmU2Grj1rL9ChUQhL1kO9++m4X+sVyuR9e9USgoxcQ4eszCS+XylkY0KIa30SkTEeSbIdqp1kSjFs4NIxwVjk94DXaRYHegusBgCGk77HNCXRg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) by PH7PR12MB6717.namprd12.prod.outlook.com (2603:10b6:510:1b0::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.19; Mon, 23 Mar 2026 02:37:27 +0000 Received: from SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017%4]) with mapi id 15.20.9745.012; Mon, 23 Mar 2026 02:37:27 +0000 From: Mikko Perttunen Date: Mon, 23 Mar 2026 11:36:41 +0900 Subject: [PATCH 5/5] pwm: tegra: Add support for Tegra264 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-t264-pwm-v1-5-4c4ff743050f@nvidia.com> References: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> In-Reply-To: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Yi-Wei Wang , Mikko Perttunen X-Mailer: b4 0.14.3 X-ClientProxiedBy: TPYP295CA0043.TWNP295.PROD.OUTLOOK.COM (2603:1096:7d0:7::11) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|PH7PR12MB6717:EE_ X-MS-Office365-Filtering-Correlation-Id: 36b9a641-045e-4e4c-4740-08de88851f85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|10070799003|366016|376014|1800799024|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: siezgzp2Vj59klhkEGoXAazZiFCvSzI/JLgChNo9a3kV9MZL2qdERF2cdmBqbpHAXG1YVV8/Hx+PvKPDFyruxEBzA63bQLGPMDuiNCAsjv1KT9jxj+uNHIVMF/MoMdleZkMhKnF4eA6bG1zwrF0zlrYAmgTFiBjLq0xuPoZZ7ZvVoOF1fU3u3eIslq8WObeoqsU39gQ8zbv1ffQpSCn61oKXFEZLyOluenDtw3Gpxpo7Eg+iUHCUzQdKhINO6vM7OVsttJocTWE6rAVcAcWnlmHjdtyZQuANMsKNk6OyXaC52lC8egpQ4d9Y6G2DBX5+x9JF7CpVRFj6YfkdSmsrW+ajGQ1QhmDzeR8DYazfYsxSnBEqlYKTu5yBepyW7XOecUUfIGO0hp4stOiWA1F5G0df2hnpay1Ac1TLxJrKPJUHOTZvvpCbIbG7AZD2VDiu7I2Y348RZGXeE4tRxtKmyEUXejgmkd0hP8vexTS3hhAcd2UI/aMtJ0b+SezYTr0DfV9w3X1XoLhayyF6JMDpgqqSh5EPm8wJt6SaIEBDYjLr4spgK4CSSIBQGYADag7YeinFaamuP4I5G/KLgg6Z6poF3B8FqK/5rv3E1gHS0VBjG527Mq+87FNVKvXExx+SBhq6HfdIjiqkKUDADZzShzxursfBEY9a9R4DzYUXE0Xa1etp3U4V5zhvG7yuJ9frnbT/FTI9F2lSNr7KLc6Fa1bVicJUfvgDhP9UHS/ri2k= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SJ2PR12MB9161.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(10070799003)(366016)(376014)(1800799024)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 2 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?OSt3RjZYSUN1aGp5ZzNzR0x3S2FXaWJ3Tkw3a0w3RWsydjZRcm1aWlhFbG9s?= =?utf-8?B?QnVUL0NNc0ZsdlFFcCtYWWt6dXBIOEozcnJhZCtXQmNBcmR6YU9BaklHM3E3?= =?utf-8?B?SEdGSGlzZXFPMzlIajJtYlU1aUJyTE5CSERzZ21EdXNPUnBjL0huMEU2SGcx?= =?utf-8?B?NmlWMTViQk53YXRtVE12Z01VVnNpY0I3ZGs5Q01haSttQUFYcXkwSFJMNlN6?= =?utf-8?B?ZktkQUt0emJteWFUYjBDRWNsVHJITnZhS0x4Mm9NaFpMbkV5UmNYOTUxUDFM?= =?utf-8?B?SnV2eDlKL0krb3pqam5jOEFCSStpVG1kbUxhTnFLbzk4c3BqMWVacjhxb1F3?= =?utf-8?B?TWV5NzMrbHEvbFZFOHVwKzU3MmdybHBHanN4Q2JydHpYMmlLbVVsNGVwKytE?= =?utf-8?B?MTJ4M1VFWGluOXFDV0x2OUZRd2oyekt0c0g2RW10OEdsNk9NeWdLbEVpYmJo?= =?utf-8?B?TW1CVkRmTFk4QkFzMDFyQlVXdk9uRXREZHQrK2NwWURlcGRpK2hTRmtWbUM3?= =?utf-8?B?UWxITHlMcWpUcDRoZjBIZDNId2VOYkFEeEkvS1NMZ1FaTjc1aWxlbkhFVzV6?= =?utf-8?B?dnJWbTgvUWxFa09weEhoSytiOFY2QUdKQUc1K0gzaXZ2cVZ2SVZGVHJtTGZK?= =?utf-8?B?dzREbWNNdUNHVlBTSmZ2TGhHaTAvdnFtbWVMa1RGTGEyYzZGVzUwWDZ4emVl?= =?utf-8?B?KzNIZkovenVxWUpJb2k5QmlqRUdsQ0FFY3lma1MxTjczLzhYcHJScU12N0d1?= =?utf-8?B?ZUhNYUpBMXRKakZVZjFMVU1mVjJ0K0FjZmJ3S2dKRTd3ODNiZUhSSDVzWk5h?= =?utf-8?B?aUwxZlkwdFQzSEg0ZlIwdGptcHhKdnlxN1ZIUW1vdE1wSWszRkxMUVU4T2NV?= =?utf-8?B?S1dBSFFDUUF0eWJvc3RZNGRHOUhzMUx4RUZoMnBkODBZV2ZvVFVSYXM5ZVdn?= =?utf-8?B?SkNmRGtTVGdCTU1rU0MxMDc0OWdCem9KaGNrK1FjbitrUWxwNHpVYi8yZmtB?= =?utf-8?B?THVBQjhBSGpIR2pEbWFaQStWZTlRWFlHL0NuV2lWUFo5Y2Y3ZnNzRGNHZWx4?= =?utf-8?B?Q29scGIrMy9va2orRHlKYWlHZlR3czRpNjk4RVRrUnBRdGVLSDl3U3dEbG1T?= =?utf-8?B?bkNsd0RLQXQ0ZWtwZmlBZnl0ZjdyWFowVHNSU2VLTkVOODRJUU9OMmMyeCtl?= =?utf-8?B?Vnh6QnlBVjNFQk5mUTlkeGpaS3ZPWjZOVHZMY2F2ckhuVUJFa2JiSGR4Vjhi?= =?utf-8?B?Mm83QnVWQXJ2cy9zdzlFNXI5aEtNOHlDU3BGR2xxMFczby96elk0YVlWOU5v?= =?utf-8?B?N1ZYcWRUS2Z4R1RmWVRlV3VtQ2VPSU41dFhkZVZ2ZkJhVUtNS2VHQXZTeXNl?= =?utf-8?B?RWFrV1lleFNxYVQ1Vy9acVZ0bC9rbW1DbTA0SUp4TjVmMnZFdTR4VlpZL09a?= =?utf-8?B?b2xXRnFTMHJVaVZ0RFJhSTNLRU9BdFh4QmttVXFoSjVneVIxR3h4MExseC9K?= =?utf-8?B?UHo4c0xkMkttUThSVjVaS0cxNXZPVGlrcWY2Y0d6QUxsRXdFdW5ONzVPd3dN?= =?utf-8?B?ZlAyc3Vid04xNkEyMWRtY3RWcEZBMlFoSno0SFhDQlJ4U3FMRE8xbmVueFVD?= =?utf-8?B?OTZoWWJ4bzQ3S3VTWjNyejBncGYrMVR6UkQvb1A4a1RRZi9oNlI2VDh6dE1X?= =?utf-8?B?Um1QclhTYzZOWWlDdDhUR1kycVF0c2Rab2lKbnVyZzFzTktwUXJPeVQvd3lD?= =?utf-8?B?alJ0R0s0RXRvQ0cxeDlDSThId2JsVkFtYWhDdlRPblhna0ljZk5hMVpzb1U4?= =?utf-8?B?NkNlcWxiRTVPVXJ6Q3JuaStHaGZ4RmVPZUlvV25TSGNDQUo1aTg5WURhd0hP?= =?utf-8?B?ekpJdWxyUDhDdVBQVTllUkdXcXZ3clhGM0lSQS82UWYrbytOTTk4MzhuNi8y?= =?utf-8?B?VVk4UDIxck84ZkJPbG9EdGM3TXZzODM2bFo1MXZxQVQrczAyb2lMS3FnZllh?= =?utf-8?B?cEo0ZHdNUVJPUld2bEZyWGZvNUVGQXZDRXFWa3hFMEY3M1hTT2NwMS9lWlVM?= =?utf-8?B?cTFKQzk2eG5MT2o4U2RSckljUWJyRk5jS013V3B0NEVGZmxKbHY2SnVuLzM3?= =?utf-8?B?Nmd6OFZBS2U3SHhFUGNTVXN1RzRwUkpDaDdkd3hrYVhSTklpRUxacGp3Q2Fv?= =?utf-8?B?OE03WVQ4RUFhNGQ1dmNtdTRRK2ladEgyRFBZaERBVHRwMUFJRGFyV3RUeHlE?= =?utf-8?B?TE9HYnVvcjZkeGNOcWsweUtNS01kVVZsUkFkMUhmdDRVZHZRZFF5a1hyZURl?= =?utf-8?B?TlZSeDk3ZGxkYi9KZkpSam1HSUp0cVRRYlZvd3hhUExxc3JjU2ozTHBkZkpr?= =?utf-8?Q?nT1R4YpTCJMTo96bf6qKVagV5rtNh1Q6br6SlG94rifkU?= X-MS-Exchange-AntiSpam-MessageData-1: 9yC6VtLRw85png== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 36b9a641-045e-4e4c-4740-08de88851f85 X-MS-Exchange-CrossTenant-AuthSource: SJ2PR12MB9161.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2026 02:37:27.6527 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 18c5v9DeNyVeI2zcjG46k5phddstJ0ze0+JV6jvJpoYDVl0NXONoeoFWdkUmo/ot1OgYQqywPmvfYQv0xp8Eog== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6717 Tegra264 changes the register layout to accommodate wider fields for duty and scale, and adds configurable depth which will be supported in a later patch. Add SoC data and update top comment to describe register layout in more detail. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 75 ++++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 61 insertions(+), 14 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 857301baad51..c1e8a804d783 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -7,22 +7,60 @@ * Copyright (c) 2010-2020, NVIDIA Corporation. * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer * - * Overview of Tegra Pulse Width Modulator Register: - * 1. 13-bit: Frequency division (SCALE) - * 2. 8-bit : Pulse division (DUTY) - * 3. 1-bit : Enable bit + * Overview of Tegra Pulse Width Modulator Register + * CSR_0 of Tegra20, Tegra186, and Tegra194: + * +-------+-------+------------------------------------------------------= -----+ + * | Bit | Field | Description = | + * +-------+-------+------------------------------------------------------= -----+ + * | 31 | ENB | Enable Pulse width modulator. = | + * | | | 0 =3D DISABLE, 1 =3D ENABLE. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 30:16 | PWM_0 | Pulse width that needs to be programmed. = | + * | | | 0 =3D Always low. = | + * | | | 1 =3D 1 / 256 pulse high. = | + * | | | 2 =3D 2 / 256 pulse high. = | + * | | | N =3D N / 256 pulse high. = | + * | | | Only 8 bits are usable [23:16]. = | + * | | | Bit[24] can be programmed to 1 to achieve 100% duty = | + * | | | cycle. In this case the other bits [23:16] are set to= | + * | | | don=E2=80=99t care. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 12:0 | PFM_0 | Frequency divider that needs to be programmed, also k= nown | + * | | | as SCALE. Division by (1 + PFM_0). = | + * +-------+-------+------------------------------------------------------= -----+ * - * The PWM clock frequency is divided by 256 before subdividing it based - * on the programmable frequency division value to generate the required - * frequency for PWM output. The maximum output frequency that can be - * achieved is (max rate of source clock) / 256. - * e.g. if source clock rate is 408 MHz, maximum output frequency can be: - * 408 MHz/256 =3D 1.6 MHz. - * This 1.6 MHz frequency can further be divided using SCALE value in PWM. + * CSR_0 of Tegra264: + * +-------+-------+------------------------------------------------------= -----+ + * | Bit | Field | Description = | + * +-------+-------+------------------------------------------------------= -----+ + * | 31:16 | PWM_0 | Pulse width that needs to be programmed. = | + * | | | 0 =3D Always low. = | + * | | | 1 =3D 1 / (1 + CSR_1.DEPTH) pulse high. = | + * | | | 2 =3D 2 / (1 + CSR_1.DEPTH) pulse high. = | + * | | | N =3D N / (1 + CSR_1.DEPTH) pulse high. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 15:0 | PFM_0 | Frequency divider that needs to be programmed, also k= nown | + * | | | as SCALE. Division by (1 + PFM_0). = | + * +-------+-------+------------------------------------------------------= -----+ + * + * CSR_1 of Tegra264: + * +-------+-------+------------------------------------------------------= -----+ + * | Bit | Field | Description = | + * +-------+-------+------------------------------------------------------= -----+ + * | 31 | ENB | Enable Pulse width modulator. = | + * | | | 0 =3D DISABLE, 1 =3D ENABLE. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 30:15 | DEPTH | Depth for pulse width modulator. This controls the pu= lse | + * | | | time generated. Division by (1 + CSR_1.DEPTH). = | + * +-------+-------+------------------------------------------------------= -----+ * - * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. - * To achieve 100% duty cycle, program Bit [24] of this register to - * 1=E2=80=99b1. In which case the other bits [23:16] are set to don't car= e. + * The PWM clock frequency is divided by DEPTH =3D (1 + CSR_1.DEPTH) befor= e subdividing it + * based on the programmable frequency division value to generate the requ= ired frequency + * for PWM output. DEPTH is fixed to 256 before Tegra264. The maximum outp= ut frequency + * that can be achieved is (max rate of source clock) / DEPTH. + * e.g. if source clock rate is 408 MHz, and DEPTH =3D 256, maximum output= frequency can be: + * 408 MHz / 256 ~=3D 1.6 MHz. + * This 1.6 MHz frequency can further be divided using SCALE value in PWM. * * Limitations: * - When PWM is disabled, the output is driven to inactive. @@ -56,6 +94,7 @@ #define PWM_SCALE_SHIFT 0 =20 #define PWM_CSR_0 0 +#define PWM_CSR_1 4 =20 #define PWM_DEPTH 256 =20 @@ -418,10 +457,18 @@ static const struct tegra_pwm_soc tegra186_pwm_soc = =3D { .scale_width =3D 13, }; =20 +static const struct tegra_pwm_soc tegra264_pwm_soc =3D { + .num_channels =3D 1, + .enable_reg =3D PWM_CSR_1, + .duty_width =3D 16, + .scale_width =3D 16, +}; + static const struct of_device_id tegra_pwm_of_match[] =3D { { .compatible =3D "nvidia,tegra20-pwm", .data =3D &tegra20_pwm_soc }, { .compatible =3D "nvidia,tegra186-pwm", .data =3D &tegra186_pwm_soc }, { .compatible =3D "nvidia,tegra194-pwm", .data =3D &tegra186_pwm_soc }, + { .compatible =3D "nvidia,tegra264-pwm", .data =3D &tegra264_pwm_soc }, { } }; MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); --=20 2.53.0