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Mon, 23 Mar 2026 02:18:29 -0700 (PDT) Received: from hu-hdev-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35bd358b5ecsm3923448a91.5.2026.03.23.02.18.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 02:18:29 -0700 (PDT) From: Harshal Dev Date: Mon, 23 Mar 2026 14:47:55 +0530 Subject: [PATCH v4 02/11] soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-qcom_ice_power_and_clk_vote-v4-2-e36044bbdfe9@oss.qualcomm.com> References: <20260323-qcom_ice_power_and_clk_vote-v4-0-e36044bbdfe9@oss.qualcomm.com> In-Reply-To: <20260323-qcom_ice_power_and_clk_vote-v4-0-e36044bbdfe9@oss.qualcomm.com> To: Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Manivannan Sadhasivam , cros-qcom-dts-watchers@chromium.org, Eric Biggers , Dmitry Baryshkov , Jingyi Wang , Tengfei Fan , Bartosz Golaszewski , David Wronek , Luca Weiss , Neil Armstrong , Melody Olvera , Alexander Koskovich Cc: Brian Masney , Neeraj Soni , Gaurav Kashyap , linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Kuldeep Singh , Krzysztof Kozlowski , Harshal Dev X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774257482; l=2504; i=harshal.dev@oss.qualcomm.com; s=20251124; h=from:subject:message-id; bh=GRasFOQDQnuoi6LdOvdCuvHUGo8tuUdcLZv2gGWTa7I=; b=0AKNRl6KfF/JYgXrtGC4dExbf3Ox7uxMEZ6hQ/OzDCKpAt31J5XhaBXgEeDlTCqSJjJZuQYds bmivaZvOYjPDXR3cTODuxf7D9DSQNwkbi3lePlT0YgGyra7M2ElG3TS X-Developer-Key: i=harshal.dev@oss.qualcomm.com; a=ed25519; pk=SHJ8K4SglF5t7KmfMKXl6Mby40WczSeLs4Qus7yFO7c= X-Authority-Analysis: v=2.4 cv=fKc0HJae c=1 sm=1 tr=0 ts=69c10566 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=DGDWbsvPyNGGEFbMfx4A:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: IxCAvymhpR99dwc0EueQcwcqNDx4yHTN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDA3MSBTYWx0ZWRfX3QImbFyKpSNf PRIfdDlpclmu4Nf1c26+kCCUr4LfuYkczQGAVdKpcTgLP9O4if6tU89Rk3fkdxxPFsUXPa209oW ilhjjOqurJsIWdwUFHC+WkPqL2wyJaFtEquzlmMEuDQQqkcFoOn7Mqak+THMCyXxivWcx6JQUMT Ndl+Fz4pMmhGOfcOBBbc3y40dz0O5SzGnvLztUPqsEU0cuYlIDOJI5Bw8Ovx3/5eM6j7e6MwGV9 6xgUOfUaYnsF3BQtQ15znCDAum+Acxd+GRUhXWoBl9oEKSOpHNdfztSEjVyqu7kYZQsU5AQROj7 zL+hYJ38EBjQBViKD4IHzbeS/zvHCXFopGCWUkGVHRFZs/GGzCDj42Us6bh74bPr4lU3IuddJQT jRNhT7a1vL0pTkBKVjtq11mOUEm3SZ0Aixxm+quDBn9ZmDC2B/kwoxZ6hoFneA7sW8xXKL7OpbV oBpnd3ve5nlCqhTld3Q== X-Proofpoint-ORIG-GUID: IxCAvymhpR99dwc0EueQcwcqNDx4yHTN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_02,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 spamscore=0 suspectscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230071 Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver de-coupled from the QCOM UFS driver, it explicitly votes for its required clocks during probe. For scenarios where the 'clk_ignore_unused' flag is not passed on the kernel command line, to avoid potential unclocked ICE hardware register access during probe the ICE driver should additionally vote on the 'iface' clock. Also update the suspend and resume callbacks to handle un-voting and voting on the 'iface' clock. Fixes: 2afbf43a4aec6 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicate= d driver") Signed-off-by: Harshal Dev Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Reviewed-by: Manivannan Sadhasivam --- drivers/soc/qcom/ice.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cad..bf4ab2d9e5c0 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -108,6 +108,7 @@ struct qcom_ice { void __iomem *base; =20 struct clk *core_clk; + struct clk *iface_clk; bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; @@ -312,8 +313,13 @@ int qcom_ice_resume(struct qcom_ice *ice) =20 err =3D clk_prepare_enable(ice->core_clk); if (err) { - dev_err(dev, "failed to enable core clock (%d)\n", - err); + dev_err(dev, "Failed to enable core clock: %d\n", err); + return err; + } + + err =3D clk_prepare_enable(ice->iface_clk); + if (err) { + dev_err(dev, "Failed to enable iface clock: %d\n", err); return err; } qcom_ice_hwkm_init(ice); @@ -323,6 +329,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); =20 int qcom_ice_suspend(struct qcom_ice *ice) { + clk_disable_unprepare(ice->iface_clk); clk_disable_unprepare(ice->core_clk); ice->hwkm_init_complete =3D false; =20 @@ -579,11 +586,17 @@ static struct qcom_ice *qcom_ice_create(struct device= *dev, engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice_core_clk"); if (!engine->core_clk) engine->core_clk =3D devm_clk_get_optional_enabled(dev, "ice"); + if (!engine->core_clk) + engine->core_clk =3D devm_clk_get_optional_enabled(dev, "core"); if (!engine->core_clk) engine->core_clk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); =20 + engine->iface_clk =3D devm_clk_get_optional_enabled(dev, "iface"); + if (IS_ERR(engine->iface_clk)) + return ERR_CAST(engine->iface_clk); + if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); =20 --=20 2.34.1