From nobody Fri Apr 3 22:13:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA441203710 for ; Mon, 23 Mar 2026 01:17:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228650; cv=none; b=J9AIjyEEKMxZy7QDo3+l6HrmUXwhONgSvNtwRS/r4EgntYmR7OKJVXDYxB8iHQx/Sa+hfs2bHlcQHdAQnmJo0roL2RzkgLBjJmtKjRirnyJiIHSdKkmTHuE+Pg+Jy0xZ4UGQHiRhndPyqMBoEgn/s4GTjlV645uZqmE3ZMgtGDA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228650; c=relaxed/simple; bh=ve60Hat4fjDGd6a0MMY2a+1ZxOsOvrbkOAK4ZWhT+wM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DBYuyqGi5+vs2g7MMKKeYQ34F6AwMAUdyndBK4gCAFUbjif9KaCxJ4SyhdV3mk1fcgZXCIgb2lm3b78gCuBMAYxWFbtZTq34Kj5zFZEp2W1w0k81uE7NVosTLhaoIfozGPVavTSYMcohr/bk1Q5p/GQtnEyvdfimrYw9VF4FFRg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=F6CYOZCL; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=cFSJvcjn; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="F6CYOZCL"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="cFSJvcjn" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62MKnLqr422006 for ; Mon, 23 Mar 2026 01:17:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= CsLnVUkiBBNLZ7fR/kaHQdxLUTQ7WZot6+FHpylt1ow=; b=F6CYOZCLv0pLDWtx XTI+ZEEIDyqveP9oLmGoSXcAx5pZm1AcAf61skGhoG9Sd0NFiyWUkPge/DsKuu9c 3I3GWJRNRI5jf2S4I6LVVUgssBDyWs2mQxvC+QD8IL1nfnv3oNLpkRGNqzztuQDO w8xM99YPZ28Y63KzcVOLPCdkkbWIH/TCS9+glJcBOJX8yE9hP4gA8QNTJQuNS4SZ 2QFkUPw4QTKOoVPbGYT4iMZPDNXcghuw2O7Xrb7CMIilj96LSUURGq5m5tAPKucB ALOQX/CaoZwcmToG3Tv9eToqXgKxxmecBaKVThWErSuxtdAicmsPHjDFfV2zWBys TpTaRg== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d1jwvk9y2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Mar 2026 01:17:27 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-50b44f7b7bbso171126731cf.3 for ; Sun, 22 Mar 2026 18:17:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774228647; x=1774833447; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CsLnVUkiBBNLZ7fR/kaHQdxLUTQ7WZot6+FHpylt1ow=; b=cFSJvcjnY58N86jUXuCsZjCq+MsFIM9u0gjUn8NJwrhN4TeXSoC9+KlpzljE6pBR+h IIBx4L9+lzT5MsVUtO09jAGHrgis3W0RIyjfJiarRhQIeLR0sJyUskcIbpGGH5jL+fCp ixYefTnFLE1YpBnJjZoJ1WJg9Ch9Xw2oNWJ+W98Xpb8FnCpUsKKpZWiXk9sID6O7SssE pLywrZ1ZpR7UkieGZu0XYpnrZBl4GR1FB+1THAGYESNtawlCN1MtVZYQc0rrxzMac1j9 2q1w9e+WF8CntMBIbFtSvsFTKvJKB23ZvE0sKnADtSPR/2SAeiM0AsOaJugCi1oXXVTY Z0og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774228647; x=1774833447; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=CsLnVUkiBBNLZ7fR/kaHQdxLUTQ7WZot6+FHpylt1ow=; b=q+NMpwqLyBkHhoT3bkqj6Ca3FzFed23d3rZNiinJlNrMBAQXKJb/JyYSSEvflrJ0Zk Pxn+beja5uPcx/pUf/kzVZGMMLSSlFZtr5jB27avRiDfuAtbZwp7uujaiVMlp6zTIv3j 4x8IyOEo5TQHMLaQ7aAlbr7XKJA3RQxMGtx3+Xk3zriLTIvYigud+6PXQu1cCx5rUGN5 naihwwHrQTMjQC1QgNGylDhZZMvbiY6zrIrf8maPR1sBQJvX682nAbqgSsgBTLSactHR ZznDLVEmwsOzp1bha8sDlnD4uByPwTQ9alnUPYM6kn4jRniUA+f1CeJRLWtXDZFpCsOk b4+w== X-Forwarded-Encrypted: i=1; AJvYcCWQ8O1o9mD90o/tFOH+F8EKB72EEFSVs9ECfVRxVDNHusIQYje+iIhGLMUGmiiRExTyhiDfN65AfwsUdfA=@vger.kernel.org X-Gm-Message-State: AOJu0YzPpKScs5EGlFw5tClHXbQe8+sn+rrJwihfB5wKDg6yjbKwuFcj eT3lO1KNM5uaybFN5jluuPtG1i0Cuabl9rWo3mQqD2oErPW9Iv5Iqs2mRxIyUft90D4uhA/tKTX Cwifj2+WWNtcPMjYuWbArhGFnmLZ9EUPNAjJ1Dm7byoJZib+CfM0zAhWRsMOKA4vw3tw= X-Gm-Gg: ATEYQzxVA5EXv2CsdC1UKKh2rzaEJ+SAzgW0IDf1AjNVLXzIXvngLKuwyJj9+sLCt0u qAncRKo11qgr8CPH/+sEHgdwobNuAyNHZQ3ed3/v370fJzULVFz2upXgwzvXtCrHKXQzHR8kqFO 0WCDQbAeYC33msQxqgV/TCuIuomtMpdHykRHEBpD9BleqaaQz4pQpA5yrc2SGlmx0m9CAW/d87L qmauBBxavK75LDrzOSTqm59XGrAol9GLk+ocMmClPrRJiVfsaEYGfKidP80Lue0pNC1n4yzSNQM kc8vToJLSfcnGh7sx8xVyJvSX1NMSh6f8WGKg+Tu1204F9Cx+BYbR6yUxvS8S7AFzlOq0f7e/RC c4urEFy6YPUQhBaCt1vBEz/jFKJ0DVRptARXRtfYG1vzyYrLReWtZkJINjgee/5ZhqRA1XorDow sEOjpUqX4LZJnKBb/up/cU8MFIWZkQNs4Fv5Q= X-Received: by 2002:a05:622a:8c:b0:50b:3831:417f with SMTP id d75a77b69052e-50b3831446cmr155920611cf.45.1774228647262; Sun, 22 Mar 2026 18:17:27 -0700 (PDT) X-Received: by 2002:a05:622a:8c:b0:50b:3831:417f with SMTP id d75a77b69052e-50b3831446cmr155920261cf.45.1774228646653; Sun, 22 Mar 2026 18:17:26 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2853050e7sm2216150e87.61.2026.03.22.18.17.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 18:17:24 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 03:17:17 +0200 Subject: [PATCH 1/9] dt-bindings: interconnect: qcom,msm8974: drop bus clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-msm8974-icc-v1-1-7892b8d5f2ea@oss.qualcomm.com> References: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> In-Reply-To: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> To: Georgi Djakov , Konrad Dybcio , Bjorn Andersson , Luca Weiss , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1735; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=ve60Hat4fjDGd6a0MMY2a+1ZxOsOvrbkOAK4ZWhT+wM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpwJSe3RQdQJFeHh2xXQt4k+38SLjcj2g9+v+Nc s9xarp4oQqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCacCUngAKCRCLPIo+Aiko 1TuBB/9xmgcOyCA7bpzuVj8O8Z0KrnHaDq0TyTJ6Bv6KFU+xUce704YUp5HWPkbolR4kyocq6t2 c6Vn96ja8bJN1L+uS5g1Z3VxA1BTh6o4QkYu9SVsCMMieVOp82xsIu3QJtyvo9rB35eVdJbe28N UKf4HIOA6y1XrLi0/EQkJmRS94HEgRx8CgT00wnYEcFDnYyhwv/cOzDqAr7TkTJIDx+oTwer0Ad Pw1C2ncE0GzrocHxvmckHAZmyA4RA/l8kLNult6q6uwY6EbYTZ0AII/sCL7zZKVrrG7T6URI1a1 zWtx37rlS3/gvihjkFrJ92N645FTALb+DBK1xH31qmQPYYaj X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAwOCBTYWx0ZWRfX+5sM2LKBTGcf 0oTtQgILjV9JV90m8N6tXO5NiyrsarZQZpy3AEFsFjk06SQRjEAg6kHtdA9dTkFVwfAWb+VNQA6 eWaDcR6+dyYNBjkcqnOWPqp2g7mBzfaStfEEJbdVCGIkc/iGo+DftnUH9m7B4eIYEkzvZatrZxS 0hSmEzZ/QzFggQQC10sSrTOJr6SYIZJ2h13wR5uxdRWZGELCazKzfDckzgBHChW811gbPzWpY2r Tg5dGGwNpB668iDaZOBgWTWJRWgeClRkwzrXzyZGpOmx/g3eSAI2twchkmRzzEQpJPQS/M7bQJq 98mhMCp1oHcGE2Ljcbmf6HAXbzFG1bwsMBQYZzyjTcKISnIouN7JA+89znqD4eYX2MBKQSoTuCP M1PBTLqYz/dXgDDYbC0t0EhDvj4S1pSpKe8rnEwF6KVgQ3VYpwCDj37q5vzryOMJq5jqOScplr4 ofR8aX4jvdHbZboDwEA== X-Authority-Analysis: v=2.4 cv=bcdmkePB c=1 sm=1 tr=0 ts=69c094a7 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=xO2zaiYFPJaqVjnw6b0A:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: 2figm16SzoL3HCCacQAVHpN4mR4v4ko1 X-Proofpoint-GUID: 2figm16SzoL3HCCacQAVHpN4mR4v4ko1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-22_07,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230008 Remove the wrong internal RPM bus clock representation that we've been carrying for years. They are an internal part of the interconnect fabric. They are not exported by any device and are not supposed to be used. Signed-off-by: Dmitry Baryshkov --- .../bindings/interconnect/qcom,msm8974.yaml | 21 ++++++++++++++---= ---- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8974.ya= ml b/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml index 95ce25ce1f7d..89a694501d8c 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml @@ -32,22 +32,32 @@ properties: clock-names: items: - const: bus - - const: bus_a =20 clocks: items: - description: Bus Clock - - description: Bus A Clock =20 required: - compatible - reg - '#interconnect-cells' - - clock-names - - clocks =20 additionalProperties: false =20 +allOf: + - if: + properties: + compatible: + const: qcom,msm8974-mmssnoc + then: + required: + - clocks + - clock-names + else: + properties: + clocks: false + clock-names: false + examples: - | #include @@ -56,7 +66,4 @@ examples: reg =3D <0xfc380000 0x6a000>; compatible =3D "qcom,msm8974-bimc"; #interconnect-cells =3D <1>; - clock-names =3D "bus", "bus_a"; - clocks =3D <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; }; --=20 2.47.3 From nobody Fri Apr 3 22:13:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A7D01B424F for ; Mon, 23 Mar 2026 01:17:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228653; cv=none; b=SK46WWTz6oPqXjtNiEpoNRBW4A811gHCDdM4VwXu70AmdHrtIBa+p03E/FQmG6bcvIEBNbgy8rNM5rkyD9bhyG8bOPEfV0DDC0RvDBCWnkBqzw8RPL2c0ANOmZGlmCnozNektouOZZFQYI3QjIfsXwctkOEIGV/ITlpFsEv1TTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228653; c=relaxed/simple; bh=yVthNPm3DjOsdKVYIVqko1MZL9hhEvKfRIuyqdTPA9I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MypDcZP5QAqTaynVGs/TDveofk/zyyrpsEg7BhbyNZmiEWGTqePJgfegikiFITSPwWmNtvlfHKwBLNEP7P89A6g9wQ5nBcydMbD6KDnryFvIxNykaMwlh93iaI5ASNz0XVhsseZjlPWdvNARFEmKq5Fb/3r1TMw07HXXQDE23jQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=FY4KdvMy; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Jzq4QLu4; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="FY4KdvMy"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Jzq4QLu4" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62MM0JRh1203145 for ; Mon, 23 Mar 2026 01:17:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= hhwgxNDk8Z3SvSduo334zellR1VN2y2e+x1xd/K7O78=; b=FY4KdvMyK6U2JkzZ xU9D1xEGHdACm+ssoT+KUEzL3peXrb/nIUTBittNVi0y1UO0osI4qS9Xk6ZO863w 2geJODqjgkTby9JYFqwsU8XOQ8n4D2k2PSSwPXnFj5D6W8sdNJAtzkS6610IN+lL qKlEY2C1hrmh9KMeLbfobH0EvxeScVnGAloHUEKcJZczFxblpYLFiDLjn879XBPD 73xwt1KUg7NdQWQFLuucOuwpDGKhGUrOY1CuestwZgEN7/28Ns36CMTPX+8rOeIt FGA+GSUUUOac+SYbxLXVS1LYze+E2PjYUMPhxWZeyty4Ylu0Jd4NsWiWT3K06Bm2 Qw4p6w== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d1kq5u88y-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Mar 2026 01:17:31 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-50b4076dc16so50309061cf.2 for ; Sun, 22 Mar 2026 18:17:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774228651; x=1774833451; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hhwgxNDk8Z3SvSduo334zellR1VN2y2e+x1xd/K7O78=; b=Jzq4QLu4f1Y62ctQqO9wqNGbsDQaEWpEEnEZKO3LEnqW0PqgFgAZs4bAG3j5fa6vcl OIbXb/+vk/TWDM7P1WmGwaB/qpZk04yalIbgs3JjbP5svFf1tQiMfvOLfmnS4q4gknOV NSD0TznBoRHxod1z/8yEl9jcQiYOosoaeoH1HsbPBdzsnCHFcv2RwqyxOKBOzVlzGwRz xB4dRweb+7JPQ6OV2j44wTxoQ625um2epp9mDvoi86Pyj7jZn46vZ/rUqxK3NpGC02G1 VP2zJwUo6zbR1E7MgNcJr90WvAs6Uy7nGMpuH6GrhIxCah9t+BljlYr+RLyn+0mwFoCM aDiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774228651; x=1774833451; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=hhwgxNDk8Z3SvSduo334zellR1VN2y2e+x1xd/K7O78=; b=ZasiNP3iBvAz9pL+GE4xaI21k/Tg1WyXhCp5wc57KJx5tIJtp5t3+h1yjWvV5nl6x/ SPcgYF013xJrdnMftZXFw9383iLxVtq/61mXdIxGIuXVocEk4GJ49mapuVUpj8hrjqSg 3ktK+vsipNkr5xUw9O9sBhWBMrGwSJzgS7tmjFkvOUyFCyrnFsyW/cOAK1j+o1YNLGvW qeY9wITSEDNl64EbIU5L0Db1ibYtw/0VriPwShP5lFrPL9ss3Kftyd/7Wx2+s2vg7Pxu 5t76KRIXtJ7N0cRG/+IMwZnhoZDZeb0dtodLIjGWxq/fRnhYmN57Rrv/E4N068vUeAz7 zQJg== X-Forwarded-Encrypted: i=1; AJvYcCW/2qBmom8up8Dg8z1ESN64THZlMbqENLlkmd4RwuvLgzAzmqKRfXebtU+1X16Ek639lU2gsZ4Me/xZ3WU=@vger.kernel.org X-Gm-Message-State: AOJu0Yy8gYx7kzz84wANyxMthnnlJWmE6B0HC4vrR5l94OMsUmNqpufP KbtpU8Ixp+1xM/ILIvraoxmXEAvVZvXyt16ClYQiaMx2ZSXsh6oWBeZgd9Iep//lRp9oX8GKB5K OjZy+l+/WbNtTstlap6q2S+PVrI7eiPWH4Z/95SVkH88Ccn95CWCRT4Yo3ngaVNhA6Co= X-Gm-Gg: ATEYQzwQA6gecjtc/E8vy3KuhuJEqxq5N/hZc8Bn3kRRfOqcphxZ14h7etx04Z0ALiY lTCY+I1JKCGaQtEOBIJv6PlxeuxhuFd9W+67N9aegffyTh/lnWaFifTuwkgDLKIMEHnd7xg6oez ULaQ4+3vMQM5sX2+wODnOrpOIt2tnoelMLKsHIvRd2j1vJIVNv7enym6EMVEm0y97RhM2zItwM7 AwDnsARn4VHge/B5BUOtAKAKZoE3k1OPxxZWA/N+sZ+gNytWiJBhBjB5KHA/6yqfCqr3mBc1ykW mBffVbaxklQDbOXJ3MM252Sf4yrVWrz2QSNQPsQifhJH9P1H+m6cxTWw5ay63sm462AKjHdTMYS pqCL8w8TxkBE+pC/Mde1giQofX7yIULvQOz4S/1LNWaJaYN1ZnNxrQ7iE+nYTZTS9EGt0Q0x1DS A04xSAMc6hAZG3c5xxLm7EZuv3OK3iaJx378o= X-Received: by 2002:ac8:5f8b:0:b0:509:100e:50b9 with SMTP id d75a77b69052e-50b3744b162mr168872871cf.20.1774228650798; Sun, 22 Mar 2026 18:17:30 -0700 (PDT) X-Received: by 2002:ac8:5f8b:0:b0:509:100e:50b9 with SMTP id d75a77b69052e-50b3744b162mr168872571cf.20.1774228650277; Sun, 22 Mar 2026 18:17:30 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2853050e7sm2216150e87.61.2026.03.22.18.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 18:17:28 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 03:17:18 +0200 Subject: [PATCH 2/9] dt-bindings: interconnect: qcom,msm8974: use qcom,rpm-common Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-msm8974-icc-v1-2-7892b8d5f2ea@oss.qualcomm.com> References: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> In-Reply-To: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> To: Georgi Djakov , Konrad Dybcio , Bjorn Andersson , Luca Weiss , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1211; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=yVthNPm3DjOsdKVYIVqko1MZL9hhEvKfRIuyqdTPA9I=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpwJSer1NjPeJAAeCFMaqyxMwRyKlECRmJ7dvj+ hY4+MkP6zKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCacCUngAKCRCLPIo+Aiko 1YT6B/4oEXhkbm9aK0u/bRgee4XhZ4QKARH8HUCPa8uEUa2iRMNiXqId9Wppq7si1bV9u6WFQPM Pkiw8y5oZSoA6GqIMmvUWECOnTceC2gE97WmvfM9x+B9899/VmedCxZfzkrQ5ssN8lubTe5N4lK paOhSKvx0ioNCs5gNbYEReILOQmYfJchU3o3FLdEuXfvdcC1DwnQtmWK1YxVJXRDg3Tm/Aje51y eQOfRoGEJO35dZpkS6T2Gls1a6z+1QzQzDeuaogqYCd5hP2zFGsrsvEb/dIDLnOsYxyWYMGEQTd J100fGwG9/LuVDiaPGD1MdsG29SpiB8koH4/QS47m596utCt X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=GNoF0+NK c=1 sm=1 tr=0 ts=69c094ab cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=wtXhX3L6yvnwcyBavz0A:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAwOCBTYWx0ZWRfXwCajmkAexM8e IxmqAsjT8V7uDL7mkdr+agHc1KjzOxe02XkmKpGzmSFxMMj4dqpl/YKars1/8G+WLxS0yu/y8kF yALyS0U+Virm6wUClreBCAic6jzPFvijV07b1y6lIThpydt5i+WdC22zwWVLPesDEqtAtlYRNcU L+bHs3P7oPdtl/FQVhvoV7/yhsA7DlkrCnwHDCKt2hfRQELW5rkXecPjhMnBqVREFpVTKuh+IJK 78NRw+samkrqCASYiq1VD3NE58hpjZfJEQ1hPDd2wss+AATZHgFunYT5KCNGG6eceBWIVC2N0xC HUWTZu9LjVTH836qdV4eoYizQl1sHRZ4zDIqIKHJRxdYSDEwBoHz87AYJ9ZKbI7Jy4iwRZvUgJR leqlbh8UPlMVtNJojpROB6kFhKxHfkk6+TltZ3HrarUtBsM4d7vWGyOfg+YXB/qlyECmeTp5c5W fD6//danS4VkvBdqxig== X-Proofpoint-ORIG-GUID: Dw5uH5rK7uhCO5DnEZhdwNICQUTGBy7j X-Proofpoint-GUID: Dw5uH5rK7uhCO5DnEZhdwNICQUTGBy7j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-22_07,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230008 Use qcom,rpm-common schema to declare interconnects property instead describing it again. In future this will allow the platform to switch to the two-cell interconnects, adding the tag to the specification. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml | 7 ++---= -- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8974.ya= ml b/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml index 89a694501d8c..b35f6dd11c71 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml @@ -26,9 +26,6 @@ properties: - qcom,msm8974-pnoc - qcom,msm8974-snoc =20 - '#interconnect-cells': - const: 1 - clock-names: items: - const: bus @@ -40,11 +37,11 @@ properties: required: - compatible - reg - - '#interconnect-cells' =20 -additionalProperties: false +unevaluatedProperties: false =20 allOf: + - $ref: qcom,rpm-common.yaml# - if: properties: compatible: --=20 2.47.3 From nobody Fri Apr 3 22:13:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 908CA20125F for ; Mon, 23 Mar 2026 01:17:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228657; cv=none; b=K56WIL2O8T/z968QBg1bdOxnEcylWWIN8j/JMmHEXpEY+kAdHE6HtSUGtL2DlPDk1aHJrgzw7UtGHv9dBITmK8zwRDeJXm5KGS7LMwRXwgN3QkOKaI9tEOWYmoqSPaLv3xN3m4VCz42mfFmO8SoM4OJ6QDMFtXjuvHs4F+ZvCuo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228657; c=relaxed/simple; bh=yWGYHMvMuQOoFgMW09hmb437wfgDJSFA0so4gDay7xI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VmS+5cwezPsODg9EOiuqe3J/DCFDHIMXASKj/0pj4OTId841wCDeOuvNCkE4RdN02N0UTC74yTvHAOgabqcRLFggUs+JBEnk2sgUD5U3cahFHk02RHdx9001vm6l0o292Xpb+eY3iLYP1PazeWDqVnSfR2YoqXJHUE3SAtr4zW8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=oBOolYz6; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=BtoB8wZE; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="oBOolYz6"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="BtoB8wZE" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62MBqF893046621 for ; Mon, 23 Mar 2026 01:17:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= WgxylbfbI/Yb32tDq9tOK0ZiL/pL/XntVxHahWXIwAc=; b=oBOolYz6Qe+yNlRV PVSfJsLTCfMWMlyGD6f4WmOZqEMIsejqC6/xFHcQc3lPWUgiimaGgPYhS41wJWg5 WlFIOOfmhqhR4Z24vGhGPAYmwNiEGiqeaL8AkdXE/3+fHwIeQqYYnrVm+S4ESC3c Aw/hLjeCOSbLmO1ErKFSrzA5cqoBo9VBvkkkei4Pm9PghzBXCnuxg8PPI2YBiBDH 3UNoFmM2pxvP0Bzm3+SprYs2VVzZ/w+MBkVNJVJJZoEM7Wu6CC5ySY3U2jFO77O7 VM1K8sp32Uu60mQCVUe2VNXZXizVUsXyl2eIwaBQuVo5O0GL91eKvZhipc6l5BVd mkmvbg== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d1gpk3ena-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Mar 2026 01:17:35 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-50937cf66b5so35431341cf.3 for ; Sun, 22 Mar 2026 18:17:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774228655; x=1774833455; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WgxylbfbI/Yb32tDq9tOK0ZiL/pL/XntVxHahWXIwAc=; b=BtoB8wZE6t9elWH7anzwURBvMEc161cJ+wx9W91tEWVfH2Lr361YyriHZpLsowguru 3b7fVzJxP5QEOCXtQK+rBYgrvyMNIoWSOBFUoR9qKp1bC6P4m6ri0RDrKFeMAI2FtCMG jieY3OoVnhJhdJE/ba1EJzh7qwewDXXqZI5RKEQmSfRa+ERIoEmjrCkxWZa8dnqoCF7F OV4kRil/AoMAktwmBIcVEEW7e5AbZqT1v43tOhVsC1Dsg2R/7WfQjWB25rSiTBhLIeo/ 99RYIHDgsZ13Y2Qgy18QzI15VK/aBcWhCtsD6mXVc0voKY++6T8jm2/FiJ+G/k2HYsyt hDtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774228655; x=1774833455; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=WgxylbfbI/Yb32tDq9tOK0ZiL/pL/XntVxHahWXIwAc=; b=fcyDPIMsMpnXAXlV4bhaxOuHmh4WiAfXWeo3kxla1Aqr4wKML6BlIvEj9I178BjgV0 2+ZRovSiHBm/RIy+ZJroSPdv40IC6BrrQzrlnbYXJJh2WGJUMh04cvXHMm0RQZ8GO5nA 7+TPOV0vDF4EP1CylCEi21FpBbMIEhSMA0WkDD1zTucQrdAtRDZhDioGyJ7DqRw3LGyQ tDBzZ+IfVzwrfj7tB0Jho6Ioz+pL+ZiwDFOfcb8HBUNasfBJLgXfXU+DwWEgst+b5QM4 0EdPNaSURepuYMHNroOtOI9LBNK34FMo09OTxP4tvOrG6jhOaEDIcruPYiVNN4EQy145 C2sQ== X-Forwarded-Encrypted: i=1; AJvYcCXcTZCVW7h7Os/Jl/wvLZuvzhuXUFeJuahKFQXKBzruScusm+kyiq/pPeB4ESGyjQfYdHtR3Z5gau2YW5A=@vger.kernel.org X-Gm-Message-State: AOJu0YynTbDI5HcJbZdf2P1+O3Xt4pAJzOyu11oBXRP0GyuC3VQpLu56 WDWokaKRrCtfVLQz7XhUKnbyDnuKkVe9Orom2RjhhyaOvCcUqOocG/PPDyrPOrqVG0wDP7yCBEH 7GBCMDby41Vyo2r005MuPfQ58Phxz9MSFkUeTuyACuvHk7OoNYky3OLijAmXnQqYMk0s= X-Gm-Gg: ATEYQzxIa/TuPI/Opz2Is7ZSiae0wW7AlGU9brfrtDi3Xl3goW21z1wL9Cz+BbDY64B 7+Jya5KHK7iG+KWufB9OlJMtYKQW3D7I221I+zSP+vpSoAaF82OQuEWW2+z6/sAk/89kY6saahE m7aGkGbarXDLIkWAYYj22wO6HOp5wooullyR2rrn4GhbU0wDj3ipWis2m5NxXs4l2IB6FITQKSR CQNYib7lbVLAlOc90Vu6d0uAHMTW65lvLkYGKzAKxbfEVBEtN2hQkm0NHcgLctFVmqbzvuu3CxF qrPnaPQupfMUrFaziBTpnrOLzYJgAev833dra3/RANWKZg6hAJAlM4fKfusC9v9tKxoiB2bMAzd AOxdSJhlrEa2Kwkdgr59gPOsbdrC05ZNtw1UMVR2PVha4Y3q6xot+pU6hBJXe/b7y+LAVgbtOsN S8Y/V3F9OdzCs9f663Hm+HKN1WvXBLLpFbh8U= X-Received: by 2002:a05:622a:608a:b0:509:1216:73a3 with SMTP id d75a77b69052e-50b3753b8camr154613381cf.58.1774228654919; Sun, 22 Mar 2026 18:17:34 -0700 (PDT) X-Received: by 2002:a05:622a:608a:b0:509:1216:73a3 with SMTP id d75a77b69052e-50b3753b8camr154613101cf.58.1774228654496; Sun, 22 Mar 2026 18:17:34 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2853050e7sm2216150e87.61.2026.03.22.18.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 18:17:32 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 03:17:19 +0200 Subject: [PATCH 3/9] interconnect: qcom: drop unused is_on flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-msm8974-icc-v1-3-7892b8d5f2ea@oss.qualcomm.com> References: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> In-Reply-To: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> To: Georgi Djakov , Konrad Dybcio , Bjorn Andersson , Luca Weiss , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1136; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=yWGYHMvMuQOoFgMW09hmb437wfgDJSFA0so4gDay7xI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpwJSe7ieNQ1Heh0uoGPsKz8u8QLjSJKZv36LgM JKb9O09Y9eJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCacCUngAKCRCLPIo+Aiko 1d0CB/sEpaROlU7i52HdRAVxnsGIApTDzfrurpIz5L9a8/Hk6PmbI0VsThejviemkXjNLMRVPw5 ya6ionImhYUuB8qKTh0mdPSCnbwfz0zk+gRjIUV8hgc5XregqzgRRwiC9wF4qYXPn4VtX4m/6HW DUUK8CjHm0HPkoOENOswgWRWDtepae2bN3Rr14Kox4+lr/CoCTYKl11pRLZWp+MXUVlHQWxsj3t zaei5Bx5FzYW+dIHP8bLPBNUj6vfDlgSXhfj3Rs31qUNz5HbctWJoCsDxO56EfesMRVrspNPQgG D0nTm53zOEZ4hFxu7XdlVYrjnV1rEBZ+xPuvya1FwMG38VF1 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: U2DNWRIFd76pxwSs_9ZnDc8feM0ZpSOX X-Proofpoint-GUID: U2DNWRIFd76pxwSs_9ZnDc8feM0ZpSOX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAwOCBTYWx0ZWRfX418V/zsBMXQF t8WoBkp/SKU8vmirMYE4K2V2ctQSrZEWXZ5rK40aaTLgskphQFhSMd6WusFGI3YH51Kq6UhNE4H bHh+fKNZxoPUZSX8i2XNBPRENzMPXt2Q3IO3GenEpOlstLg6co4cuEENvzmzT55HVLnTat2mW6B 6FDT9xiRNpN6XcYQ55DMJAiSM+di9ZA0rO11oX/6qZcUqQQP3Aa5JKK4GDW4jrvBrDNcvW0jTm6 6D0Kf7pTd7k/5JBHbrCmSJepwWufJyJlD3uowAZ2zOSRAY2n8qg3fhSZQhvykLmqgVb0ClCteam BR4jXzXHxx9sqkcUmXS0gvVo9x//i9mn3h1kGyRWT9GuzyOmbrpIOT9TCHYYSewxmcZCPkdrmoJ J7T//cNlbDrfWAxpZMoLzHxaqpQyi1QkF55k3B6S8qAb1ENSuz2k/tKzHI1SgWfFcXZtoMZImGU JW3X3ZfwTo7JjJzAQhA== X-Authority-Analysis: v=2.4 cv=QKhlhwLL c=1 sm=1 tr=0 ts=69c094af cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=snkofG2PpA7MSmzZjVYA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-22_07,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230008 The commit 2e2113c8a64f ("interconnect: qcom: rpm: Handle interface clocks") has added the is_on flag to the qcom_icc_provider, but failed to actually utilize it. Drop the flag. Fixes: 2e2113c8a64f ("interconnect: qcom: rpm: Handle interface clocks") Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpm.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qco= m/icc-rpm.h index f4883d43eae4..3366531f66fc 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -51,7 +51,6 @@ struct rpm_clk_resource { * @bus_clk: a pointer to a HLOS-owned bus clock * @intf_clks: a clk_bulk_data array of interface clocks * @keep_alive: whether to always keep a minimum vote on the bus clocks - * @is_on: whether the bus is powered on */ struct qcom_icc_provider { struct icc_provider provider; @@ -66,7 +65,6 @@ struct qcom_icc_provider { struct clk *bus_clk; struct clk_bulk_data *intf_clks; bool keep_alive; - bool is_on; }; =20 /** --=20 2.47.3 From nobody Fri Apr 3 22:13:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CF441E1E12 for ; Mon, 23 Mar 2026 01:17:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228660; cv=none; b=J+WTvst5WguOnLAqmp3gdZuGnqkHxVfvcKRoaiYBeW5T3DTpSmfcLueFvbx4Hka4Z4s03zdCVir/NnEaMAWGPAPj1TupPw7fQ91TWNXKv+Fcga1PQ+DdTqQM2JqJ6Lh4eG1pUPZGGGKXBa7DPM8Q8Zt9Xn/5D4bSAxXRm2j2W90= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228660; c=relaxed/simple; bh=ozckWw8+tIOW7mP4eABTKY6sc1w7ANmcnxLtEjsHZKg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bZ7QzpIirJWrd/dW1xjBOEUX9C3G7UR2QXig/7lrE6mcSXr1arNxI62xvsPFtwJTemeHLyfWczqYteM5BvsRyK5IICHyJMB2YFit6u2G0hEKegERVa12sfCBcWsXGR6OiYshsJPy6kqgJPP6/tULY7VzhXnHKXlY5RrQPfVcAmI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ERWSg9wK; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=KpHZessk; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ERWSg9wK"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="KpHZessk" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62MDtaUD3292715 for ; Mon, 23 Mar 2026 01:17:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= BQNTikIJkmJ6qFsbEmCD83zmmN8XeAHJf1MCNwZkoic=; b=ERWSg9wKKw2XxByl nxqNd0oZKoeOduigol3txwFCFj38+/o5dvzhgdeHr4I7QKZf9XzvjwHCDBuG0qTc YG8qYhXEdQUToeM5svpmSJNu6DMu5Osb8h/5NuGG71q7dirK1QSxw3flb/OpkHLt ZOhQRa8LJg6OwWCuQYqMzgosmogfc2/c/by0c4c1Umj3QV8AxJ6tj/5i6ivMc5CV 9TX472xek/QLEenkQ6gTNDvFnUqTlT7xViJjgGfYf9wfpSAnnSRr5sSm4AJ94ySF ACCriPINgdX/SZT+4Kn+tu0Lu3oypQRe4Oq5OEQSciiy3KvF4LrUXupQkexN1FD0 Xix3ig== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d1gpk3ene-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Mar 2026 01:17:38 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-50b2cbe7223so23322551cf.2 for ; Sun, 22 Mar 2026 18:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774228658; x=1774833458; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BQNTikIJkmJ6qFsbEmCD83zmmN8XeAHJf1MCNwZkoic=; b=KpHZesskNSLnihWnMZch7yAkY4Bp2roCiaBE5U7qh+XY3wGAhCqReYY+6KTajxNQ0B qV9yQpHxi4FkwOmstWj4zF11srZpjoNdOa7JuabZNkugLydCDL0TzGqduUD/mxlZunU7 PUfeOUmsvivHp2Euio3JeprosskF5T4uOhAuHRszFZ0yLCzkUQZKOM6fcB24EQ2BIBWP ezhS+GuT9kt5VY/ru/+EbvdUU+sGUGG3nNpoLtFU7aBUrccXuPqWNvQKQp6hvpwuL68R tryav1E9JRsoilqXddGV8rBTyXvl9Rpu/34UkHSYJvpd2QGniOi77K8yJTgHk4NzJA6+ 4z/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774228658; x=1774833458; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=BQNTikIJkmJ6qFsbEmCD83zmmN8XeAHJf1MCNwZkoic=; b=q3at+1Or1lmvLKXl+RQZBOjOHQ0M5RBviSUm7YJH2Pen8nZfxjolWcMuJUfa5h1a3b 2zveJb829LO6/8OzEYYs6CZsaZYWCD20TKvAzE4RkEPYuqkEYgPeba6Xw2n0BbujTHlI 3iQkwF7JnUSxtGRijZEXCUGUJsAMhgwGp6m73kb30ZdjLLNpFfY8Y2lOT4e35VGSU6SI tr/hHwqz7gOwYH/yfJL33gBVKEmn1aCQAt1RYy9JY5Ktsl4oMyyIU/CqgByAkotihiq6 +KpyDQn7y7BzUhwS2nhEwZKlCgM/bDDkwY4d01B4B5GzIAEcoW/mY7xBL3ipmpXKnvpg CMmQ== X-Forwarded-Encrypted: i=1; AJvYcCUt3y7dmelSM6d8OQeeSb3R0cAhza4RhJiYd/+LQySwq0jkf6Wita+EoKMPtrtaoaBWGA2wfUyvv7vmeqQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxwtwiC4N97GDhqS/abxpiZKj4CKXNEGE6v3VSHha5ptFWYgpML Hjj/L4xFXqSSKQnJRT812wtE4We+BXFqRxk5cvCVX4CpTYWF47DFSenPuEubgNfA7jflKqPIiJh 4cdEM2x338a77nxre3XX1XsGGHZq1747H8tmgGNoaekCZXKN2ZuP+vlV4gw+619cjctU= X-Gm-Gg: ATEYQzwwQYmOSnrKv0PCDbK8rA/ygbXob/XfEbNFLDU3l9O7/sWNSDKHBqvUGYyUVlr jhFPLUxS0BqAg6s7FKGgu2Hpt+s2qJEOr0HK88i68iFIeAFpzax9sRDOVUhF03UsaJvRQeEeoOu B0QzB2Fh1te+AuFPY0BlYUU5E7pxKETvOHAuChav4Lcya5XLsB6SKq55l+jsa4/dDRP5uv0eHML /3tkFyRjJHcM52NugCR0yT8S/DUlzTLfba1XH6Xf8/GWdpdRQd+hjt444tnx+ktyk4JfhA22+b/ tw4Fm+KOEzOOTsM4m2PNiRc0zxVY8RRFUpkWy9/DfKQbnMgdOMFZM0zgY9ytri9clfOezG2mXc8 EvcFwojOzQO/YKEAYyLU5q4aj+nK/yorqM2k7ZdmRM3+IlvO5AmSYsLyaZcrHMHtCV3lYcjiZbq jSxeWZokys43KOJuFx3haUZJnzpZfOcpHiWkg= X-Received: by 2002:a05:622a:1e0b:b0:509:1dc8:e9e7 with SMTP id d75a77b69052e-50b37500af9mr161031741cf.51.1774228657763; Sun, 22 Mar 2026 18:17:37 -0700 (PDT) X-Received: by 2002:a05:622a:1e0b:b0:509:1dc8:e9e7 with SMTP id d75a77b69052e-50b37500af9mr161031501cf.51.1774228657354; Sun, 22 Mar 2026 18:17:37 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2853050e7sm2216150e87.61.2026.03.22.18.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 18:17:34 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 03:17:20 +0200 Subject: [PATCH 4/9] interconnect: qcom: icc-rpm: allow overwriting get_bw callback Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-msm8974-icc-v1-4-7892b8d5f2ea@oss.qualcomm.com> References: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> In-Reply-To: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> To: Georgi Djakov , Konrad Dybcio , Bjorn Andersson , Luca Weiss , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1384; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=ozckWw8+tIOW7mP4eABTKY6sc1w7ANmcnxLtEjsHZKg=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ+aBKfM6FASX8enmfMgXlBTeqqPz4nVom9CdafqlZ3Sml e7Y/8G8k9GYhYGRi0FWTJHFp6Blasym5LAPO6bWwwxiZQKZwsDFKQATcd3KwbDCcEmmzPJ+g62x TzdwZD/IVNR7HfzJqPraz9t73///xXhsu88GmTUX6lwXHXO/ITXJQyHez/Vjed28M+/LLslltuv 2ps07JRa+ckne9yUiUZb//jT/eOHxuVuQS1SyQfJMXkGMkn4ly92/7EunRfuIC6r37Dz3zfbJ28 sVvk097Wo8YRfezZVM5a3OX971WZQ1SvfEBKm0xf+k+5dytGeI5Rc7Tlxtuji7Y7vqtY1Tpnilx az7NFdVZUX6KpGHod2ntR70tmlUGqmszz/Q7fthce+q3IkqHTXm337YMyyI2nbW4XbbUkPtoL07 I9IKK/+Jv+T63xlw1ldGpPCqcGCCbtL/upwNzswSfI77AQ== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: P2ZVBIOIXA8bNOIe7SRUE0ZIPpxjCbTX X-Proofpoint-GUID: P2ZVBIOIXA8bNOIe7SRUE0ZIPpxjCbTX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAwOCBTYWx0ZWRfX9VWAYvkCzOJz TZhTWK8dEk3+cWspKCn1ubPeuu5Ac5mmYDBd1NwvGPuoDUASQOS8cMRvnmw48366Fyx/xxRZEPz sFTBNwfzcCArGa69Nohdd8v+gOOvTl7jOltX5M1u9m1lx1sWtnqSUgkQV9FQyTdowurTVIRdt/B gD6LLX3OMonEBDeLsH+h68ksAyb9Eg7LNve7wC2geiDUPy3rsete/PKmQhz8B2SHUyLM64mHubK 1fZiHw00IwLo1NupxLTk8lO7GtPtwofvCsx6aSxY0d1kaiI3x2B1iplyki0F+eW4+Fu4GuDIctU qvFEmi9O5GdhhUQQyWsIylUL3HzKW3+c6IagY1xLQwxNeolZehmiGRrTJgYJyAt4afrX2K5P14o /Zw093QWp+Y5vUVv1xdIjw2dXj58juPQU/WL55U8/paQdtkmfJDEQH0o7uHEvWqDpe0qDT/+Zox ODezqs639m273QiziPg== X-Authority-Analysis: v=2.4 cv=QKhlhwLL c=1 sm=1 tr=0 ts=69c094b2 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=6pvQaZlX7ZpTHHZizXIA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-22_07,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230008 MSM8974 requires a separate get_bw callback, since on that platform increasing the clock rate for some of the NoCs during boot may lead to hangs. For the details see commit 9caf2d956cfa ("interconnect: qcom: msm8974: Don't boost the NoC rate during boot"). Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpm.c | 1 + drivers/interconnect/qcom/icc-rpm.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qco= m/icc-rpm.c index ea1042d38128..aec2f84cd56f 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -553,6 +553,7 @@ int qnoc_probe(struct platform_device *pdev) provider->aggregate =3D qcom_icc_bw_aggregate; provider->xlate_extended =3D qcom_icc_xlate_extended; provider->data =3D data; + provider->get_bw =3D desc->get_bw; =20 icc_provider_init(provider); =20 diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qco= m/icc-rpm.h index 3366531f66fc..cbf0a365839d 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -135,6 +135,7 @@ struct qcom_icc_desc { unsigned int qos_offset; u16 ab_coeff; u16 ib_coeff; + int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak); }; =20 /* Valid for all bus types */ --=20 2.47.3 From nobody Fri Apr 3 22:13:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2F892192F9 for ; Mon, 23 Mar 2026 01:17:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228663; cv=none; b=Qbl7D4PVhlcO3WnW3+K8BeGD327JKx+ahUm5ScNCplZ+te1U5z9eELvwv+YaZEfmEkVnyYqQfeN4opagxBiu/3XBSl+/8Qmexqxb1nEkC6AqpaRbPT9+kOnj02708VuNfdm7msrtAPdzP/G9YoeWp8LHhZddSsSGj8YtTZ/+LCk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228663; c=relaxed/simple; bh=Ya/NJt7pKVR6io1jC1dQy2DY1Rkbk/XPlKWL7mD+Jmo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hW61mCJNmkTJpLVYwhKrefkPDppUsFk5n12N17jWWtyWhTW8+wv527S6AMNp2cMQ5gMXyG0sWGS/BPAt8xCGbKZ502aJiNla0TqKOm+FdM2zgRSMvUR+8mQti6Y0AH81qurbdSm3ZjafwxpGLl+CDGQ7EgH9jKuIgOKLpa9jln8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cXk0p3mh; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=KXMNUYlR; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cXk0p3mh"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="KXMNUYlR" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62MHOwxN1404387 for ; Mon, 23 Mar 2026 01:17:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wTOuT2RJ0koUSSURaKhqCLIXf071rLm5jfDuWF+MJ1Q=; b=cXk0p3mh9bZFmsB1 DFxBheHjhCI8KZKQWoagU5+TxwtUFBkzg9tDHefVwD0K90HjMv/1YLDiwOcJR/K7 s7JzwSeg5SyKctpppNsZm96XN7Ek/DJxQx17vsNjLmVs9lhXMFhPx2ADu9cf8tVD t0R7qYbPpD9HPglZIewp5TAU+3aqAak/T4Q4FTcJRF94pR+T8FlT8gCxo7XcZ+8S D8mzRFXYVok5TUGu5ZIu1Ows5gd6RJzvRnjX/vuFrWvB9VD4hRW1v+gKncTT+YoT HUsy3qmd4Di/ZGF6AA+WTKMlDg4FRTxLiXWS6jhPnErGySYGY8u9+7oIv+HGzQo2 ZsmXsg== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d1kdub8mr-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Mar 2026 01:17:40 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-5094ba09affso307646491cf.2 for ; Sun, 22 Mar 2026 18:17:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774228660; x=1774833460; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wTOuT2RJ0koUSSURaKhqCLIXf071rLm5jfDuWF+MJ1Q=; b=KXMNUYlRq6klgzjcJSDlL9fjnoPCIIneQBP86zBQT/y8heuTjLTzXBv/ZyBNEfUKYT 628WByvZ5aGi+DrCkPwC8Dg+cUd7CCf6lyxowvdkhGk+Smodo9wy2uR7KwGDFfxTWpLO fzhvY5VlW/00flOnRYoUiOY4w0mq4De465WkOqx5ikPg8CNB5zdFIH1SS4Yf/KzV8yLn 5jx4YEYvLBR+8lK2eyAdE/WOJCOoTGeKxD1nC4WH5vLtDRg9Bpx6WaRaqAphA/E/8t7q +r/NMzjVOHDe54rWosZXDkkLSOAdmWAJ6atI9m2AZascMb3K8+3lL274Sob44cz7yYS1 DCrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774228660; x=1774833460; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=wTOuT2RJ0koUSSURaKhqCLIXf071rLm5jfDuWF+MJ1Q=; b=q783689mD1SJ+AurLpBDrE/URWw89tX3LbBDCHM7HahOKIh2WQvH5OAkg7satfDu5T m2vWvCOm5ClY3mGjeLt/NqNf70hgFfck5QUBUF/yGIBWOBSgOeJTwoXNMSxyAW1ZmpN6 RpLB3kpmt4D7sQuh0F9iLOGKtFcLzXK8BAVgERyse3mnMHDvIOgmtBQ6/tsTVK1nVxxo 6Vc2NaW5FujZVYfxRnCPBoBu/5xdqyH037/12vL1V/xdNpn+P/qWAp7iXuZ0MexigJK4 8hnX71UUcw4/dyJB1EZq9jS6rIVnQFApTWVgUb6ejhruG9a+RoQ+AS9wYqNNYbzzxdRt 7lpg== X-Forwarded-Encrypted: i=1; AJvYcCXu0UyQpf5iWIaifzF+eErq/xIh9eMnchiKOOgYW3D6p75mZTShuGxEc88JnyuqGBA2m9Q8+hEImzcma7k=@vger.kernel.org X-Gm-Message-State: AOJu0YzFUfm6jFIPifwxvwLJg3JdNMwhu6no3/rhGxI5UjSryJMg6DIg mEO5K6jHIeGLC1Uf/74zG0T1LAE+szP7GkI/j5aRTqq1U/6LnjSN0PFXr+4/+/CvMq70hZqH61Y 4plLk/2ySGiV6DzLYmuNK4uPnO+9W32uKMnTNi5t7aaTAxfF1wWq2Z8u45qFd+Y1iruc= X-Gm-Gg: ATEYQzyfV1iJg7fEVOq2th/It96KuOk65UBUhbtFBnk/YNj+/5KG9tdhs+/bHMHt1T2 vc+n8o+MPHpcr0IVAGvFoikmTjA/jghasvZRFDi/iG8X+zk7EDwzF7Ms/TmP0kcHMdjmIn5Ucls HWoTV1+Wr4077QiSDOakbW0HLUNubBpcSL6jKumMhE049qgy5FFAmKUBknYOKjTTOvE8GR+Q6AK AU2dB9ROAcxRoyDwCpM2LSzNZuzJ9Q2zdj2af5eDX+X1uCVil7CYq4J116KBnyzAkWSjuXBKH8F oxK1xf3Obe8deY5BB2hk+kCXq/4g78Xu8y2V793HK2/rnJDQPHdmLAxBN8kWdCuA3edoQ9N2X8u ZIvtD3+OraZwWKOJP989v1uzfwj2puD7eZh8ogbhhS7KomyFZ7i2DTyp0MIaAKOLNC0Mg1NGFoV l0OPzcmpO2AetZdFafpvbNaToRBIQ7+q2hvUY= X-Received: by 2002:a05:622a:590f:b0:50b:4984:148b with SMTP id d75a77b69052e-50b49841855mr91549561cf.64.1774228660450; Sun, 22 Mar 2026 18:17:40 -0700 (PDT) X-Received: by 2002:a05:622a:590f:b0:50b:4984:148b with SMTP id d75a77b69052e-50b49841855mr91549291cf.64.1774228660031; Sun, 22 Mar 2026 18:17:40 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2853050e7sm2216150e87.61.2026.03.22.18.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 18:17:37 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 03:17:21 +0200 Subject: [PATCH 5/9] interconnect: qcom: define OCMEM bus resource Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-msm8974-icc-v1-5-7892b8d5f2ea@oss.qualcomm.com> References: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> In-Reply-To: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> To: Georgi Djakov , Konrad Dybcio , Bjorn Andersson , Luca Weiss , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1594; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Ya/NJt7pKVR6io1jC1dQy2DY1Rkbk/XPlKWL7mD+Jmo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpwJSeX1baotwnLbuBujDe1jnKIQvBvRRnSisNQ 9ELGzx6MR2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCacCUngAKCRCLPIo+Aiko 1Vo3B/9REU/bTIRSQrxK7GSNxOljj7iZ5OrMDOzjAIf8El8TOMsTuQoNyeL3P4jFS22yNMWE30Q j7I8wQM926EiRQlR7c/JKS/h0qxOlZ+cWApf/rvzULqRw2oV37SFjXBqxYHsZBd66VSZEf0RJuc dAScHpjwQwgveOWBWd6bLsegZD41BcOL5UvA5LSjfYpKUKL4JGsHp4l7abGStklZX8TXHIPACCG HmLSw7/dk6I1P9ZV0h8xwQQO7iQuNxBsOv+4n8Ts8vKe14ECwXd0yCGp78KIuJOuZZCeiiqbKoB +596xD3xubsn7dlsYHL4C1ih9y4MY50SvjMuTV6EehoWm2jt X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAwOCBTYWx0ZWRfX3hr2Zm6n10Zm XpASR0NFcKdtTTf1pBKi6Doae/1euwAmkZJtPefm+HvXdfE/PFPIH3bj9IpqkbR5KtKTECf1GOl ufhDcpfUILzDE/48MrLXohHzf3VKGxaQNqtcJU2NMIGh3dHbDsJYJ7xclShNb+6Jn9a83SpWvQX nNRva9uxFoPyLS6yzpjxrZYUWY8qKPz6eG1ux5ZKcgKIX7BpClWitbvzmu2rwkzYELhp2ygaqmW aZxUE+8whtVTGeuSKpOPJ/WKyhOUjymCYCFkuTZLCg5mIIknEeNL1K50FZQZ2QRZvhAJdALum8p rvHt47mMPnGX4SpqUt8xSQUCBACHmPcI9M1lXirI/0lLlrVLtM6Mt1qZG9fYi2JFWlZniWjRnch 8LUU/FBfro41jCDlZfhjOs0kYIqYDw4GfYDIH3GLjasu99vCM1hAo8CF/XhmgTRGjHesuIDd+OW 7Aj//zQH4bCKH7Pf47g== X-Proofpoint-ORIG-GUID: ark4CJZfgwF-Pg4YeqmMsvZWF-duhj_S X-Authority-Analysis: v=2.4 cv=Q4DfIo2a c=1 sm=1 tr=0 ts=69c094b5 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=zOyvSeg7rOUdy7vhyckA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-GUID: ark4CJZfgwF-Pg4YeqmMsvZWF-duhj_S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-22_07,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230008 Some of the platforms (MSM8974, MSM8x26) require voting on the OCMEM clock. Add new resource for that clock. Signed-off-by: Dmitry Baryshkov Reviewed-by: Brian Masney Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpm-clocks.c | 6 ++++++ drivers/interconnect/qcom/icc-rpm.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/interconnect/qcom/icc-rpm-clocks.c b/drivers/interconn= ect/qcom/icc-rpm-clocks.c index ac1677de7dfd..69846e26f46a 100644 --- a/drivers/interconnect/qcom/icc-rpm-clocks.c +++ b/drivers/interconnect/qcom/icc-rpm-clocks.c @@ -31,6 +31,12 @@ const struct rpm_clk_resource mem_1_clk =3D { }; EXPORT_SYMBOL_GPL(mem_1_clk); =20 +const struct rpm_clk_resource gpu_mem_2_clk =3D { + .resource_type =3D QCOM_SMD_RPM_MEM_CLK, + .clock_id =3D 2, +}; +EXPORT_SYMBOL_GPL(gpu_mem_2_clk); + const struct rpm_clk_resource bus_0_clk =3D { .resource_type =3D QCOM_SMD_RPM_BUS_CLK, .clock_id =3D 0, diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qco= m/icc-rpm.h index cbf0a365839d..ad554c63967b 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -151,6 +151,7 @@ extern const struct rpm_clk_resource bimc_clk; extern const struct rpm_clk_resource bus_0_clk; extern const struct rpm_clk_resource bus_1_clk; extern const struct rpm_clk_resource bus_2_clk; +extern const struct rpm_clk_resource gpu_mem_2_clk; extern const struct rpm_clk_resource mem_1_clk; extern const struct rpm_clk_resource mmaxi_0_clk; extern const struct rpm_clk_resource mmaxi_1_clk; --=20 2.47.3 From nobody Fri Apr 3 22:13:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A5531B424F for ; Mon, 23 Mar 2026 01:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228667; cv=none; b=qYi6qZX6IIyVp3TZqrUNWJ5ZH4VCbv6pxSyMmJvI6fXOv1J6pv8VK02k2sY7eLIzGJNFXT1eJ221OCKFDZa53ky6EKGDqdxYRuRMs0AI02IEzI11KcdByWbbDGwFtogD/iCuRDx/h6bfhhS0KEUL3DfMiavOeET9cC/ylFwSTK0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228667; c=relaxed/simple; bh=baPUH0igjJNSAnKp/z9q/Mft9PpLQiCQHPwVsNkTz04=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ijTgvqp9GZHozJ7tsP9P7QJjyeu7Vj21QDLOgZM8Usyh8Glg8DDuOlLN7hGp2P26zHCReOF51cAqYZOAFfC2r6Uu6bJQmJuBbHF0rARuScP1GQjj5Z4pS6hMyFq4TR9vBuadh8JiXTOBLp+WdMi6mTvieDILe3tZJOb1ruipSfU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LWqA7EyW; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=WEUY50VA; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LWqA7EyW"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="WEUY50VA" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62MDmavJ3769023 for ; Mon, 23 Mar 2026 01:17:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= /t8SuqPVuhwUVvBRrLk1Dc1LxggO0aNoDGEAzNHrMwY=; b=LWqA7EyWPoIlDTJd cltDGAVCAGwfQo9jH2HK45UOLY1b9QRajzYyu5W044ec9DtRpi1DwmY25ExDfRjH 5htAAY/A8nZ3Wjy7oYOiIDrEF2aWV/+LhXMVlikXkLX+VZgGNU1/HNSNoLkPY6x1 9d1dDZJA7xvAiH1LsjdLQGLNRtUu41hi3M6Hjih0pR31P80mSPbvKrbXWJi9gaQf wzueF8A32Z9Zq2/D8GNg5DVnKjxMhuFqSY6Y56nbxgovtT1x8/24+XzcEef5xQiw MLAdjM+W8MH0v5qr9/NUXr3xtcsH024+dGoIkAu5bnu1ngPltiPQAyggK0AKaKO2 odH9pA== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d1jwvka05-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Mar 2026 01:17:45 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-50937cf66b5so35454501cf.3 for ; Sun, 22 Mar 2026 18:17:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774228665; x=1774833465; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/t8SuqPVuhwUVvBRrLk1Dc1LxggO0aNoDGEAzNHrMwY=; b=WEUY50VATJiUV0Rd2WTS1k30mUM2w+C0W+/EayXHI4SWxz75gZSLYs54FyaguTMDby s7aqC4rPhLPeskCK82Pef0eeEt96de4s7rGuihHUA4y+fkE80+C20mISo2JXEOR3HUhO RqPhRwBrqzcSlsMmgM9u2SkymYlcs4Nf+hiQMC8PfSAjO5QTBTvPtJGrgicbhAbOCjjy L0DWAaPRAPuKBaISTf+t2SfxGum8/17kkNANyiopeBRz0WgiqlgXSmcXvkWspXO5Yj9G BBUXFg5dGb7T8KyqyF8aW1lFA73e8zi6bj5dDalA1u62P1WNpAcyzfS/0+8GZ2IjD8sF 1ojA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774228665; x=1774833465; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=/t8SuqPVuhwUVvBRrLk1Dc1LxggO0aNoDGEAzNHrMwY=; b=ZNmgot2VZASps567yAKDiy/rIY8RDhDdHbj+3LbFe8hQd+9ra32gHBI6MaJ+cIuc+b 7wT6Co/WG9iEgrGfsiZxMIsfSnUvH+X/n7DFjrZ5eBJ2m9kA2mvKRO1N8AUI4CXIgZxB RCQjY73+KsVcWcO95qPdbRoKKroPnVUqF7mmb1g2dm+OGkZaRM/gGvAuak6T2+4r4FxI RWO70+HfkXs3vA+LTTFPmJZNK9ZjpaPJx46i7ocK8bsW0azKUIwkpYPK5f32HQpvJxmS nxHCDRUID7g5+yA7AFIDVS2dJCWBdmBitrv6uGGKgtRPGr55IpYH1KbHtHNGTyS6B64p na5A== X-Forwarded-Encrypted: i=1; AJvYcCXEEhws4839QdbT2dHRwyAdsA70+/dTygpbg4JGfP//LhgK0qN3SQr1qIt8k4y9VsOHpDy4jvPHWXdBPj8=@vger.kernel.org X-Gm-Message-State: AOJu0Yx60h/VpSPT2nTq+oks4VViUuJsrr4BlOQCMlFaKq0lY9uBmju/ GrfqfWvub5XDAJaxGezGkigToUcnmXTtJHLqz3ivGHPOpErdqJuBAOSM0RsY6cJJC5gT3xbIc92 lhHBh4i6k5BFhXBgh3LwpJpJ7q0++Zd+8dnjp63g1sPrdZxk5rL2vYx3SOd15AeTDUxU= X-Gm-Gg: ATEYQzyLaq5pGJ9UQMDeJgQzNZjU3F3Ow2iZpaKWORD3v66J5kThVc98zKUuiocoiVS 4Iyx0StSaHYroGUzExBd11hwURq4VwbLkWP30Z1EeyKlOglkI+9ZBJtmAXPT/vCsU/0o/LptafU n7Wv6oe8hJW2qT6lCPVY9exStwZWqJyUEKto2HwItKWSXq6jimu3FcGkQEtGB2RnKWD9ISOduPS iiJpi1N0Z+yeqDuQ9e0JN1+QY+dtZPeiWBhm7qp+6Tfm99MQzliAD7aLA28+FD7ha88rEADlMLo k5vVFgfHQMlAC+4HdCpzTDjdOtJadQLz3CRU4NXx8WhQaawVQT4KFILFsexDE2zkqrzUCL0PXZv hpRj16egBriMXmq0G1BG+GH62b42Kfj0aWj0fIbKqD1tw6cd7oN+EErSGs6ATy5qrWZimud/eXH e9eX/qN6XjVHPcp6/qSdKYbLwbgj+NctiwViI= X-Received: by 2002:a05:622a:1e0c:b0:50b:3ff3:f4a7 with SMTP id d75a77b69052e-50b3ff3f592mr140884001cf.35.1774228664615; Sun, 22 Mar 2026 18:17:44 -0700 (PDT) X-Received: by 2002:a05:622a:1e0c:b0:50b:3ff3:f4a7 with SMTP id d75a77b69052e-50b3ff3f592mr140883661cf.35.1774228664204; Sun, 22 Mar 2026 18:17:44 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2853050e7sm2216150e87.61.2026.03.22.18.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 18:17:41 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 03:17:22 +0200 Subject: [PATCH 6/9] interconnect: qcom: let platforms declare their bugginess Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-msm8974-icc-v1-6-7892b8d5f2ea@oss.qualcomm.com> References: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> In-Reply-To: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> To: Georgi Djakov , Konrad Dybcio , Bjorn Andersson , Luca Weiss , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3957; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=baPUH0igjJNSAnKp/z9q/Mft9PpLQiCQHPwVsNkTz04=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpwJSfDBkeGmEtVasiV4Gql28ow9equeUMsxQR7 lfteiyKvuGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCacCUnwAKCRCLPIo+Aiko 1a6yB/9limDxU+rsTOQYqO6zFcA33pv3UVDDPBkZ3Io1fw6LtmbqOP2iSihUjzcvKE+4IU0OriG oNrZVtHmsA9zpYz9LxYRgqRwB3lbhKXrjV/i9yV/1q9H41Q1g5Mrb+7p3aDCCfq5IlesEr8Hcw8 J/XVqfYoWdsdwKh9xrbU+dcn7230zUgt1nXMaSu0wDARWkZ8MawuDILju0Ie3BO975E+7YPCQ9r V2w26bHIEBlzEk2d/JWTDDkPSf7eWnguBd0mJP0ZsYbPA2Mfs/3FNcG5HSlHX+rRywZ5tKrBn3Q hAJGKyrHFZ485vmAv8Ms7GpqzO3boMlY7QZ4PQBwf1tNMdim X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAwOCBTYWx0ZWRfXzrt3Uw4IThg2 6yOzxorjrnKFyQXXVeKtWEi9BGHc/9DGoZnoHPEMYIJXz3cyfT7nG6uXi5hBTgvV0JnW9RkezwW PvSOwvFQ3VOGyVL3YObkKQ0dqrWqsLDXaGZ+PhL3xMi4S2DZl/ZES6ZGdc+D1KYBTo7xhq+tRXO RnkbNztAGC0nlN3gOsXpmeGLBAoQapoQyK5PMM26ooN3TiDA5L1H6cW6pgwiwQmN/wf/4i4/Vc0 +aMccoIx4PGeS0COixler84b7qlZl6sMm3h6/iYyLkjd7/dGEyCiCVsjM4AHCjtYfTAd+M9wWxP Irq2qPsCySQd/405L4K0U+Vq/nUt8A94JN1cGu+Su+uDJDLwvnD6ELITkPopGr9y9b1m2ZU+Ckf 67tFs3o2AXSOHL9qlYZBQvi3cQVEJIdNBFYUOB6WO4IxQcqpTwsJwoC8E7jqoBMK/4z98vqQYM/ nLXOsIJneTz1OJ0HTsQ== X-Authority-Analysis: v=2.4 cv=bcdmkePB c=1 sm=1 tr=0 ts=69c094b9 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=PYMLbkgk4Fc5e-Gbr9wA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: k33LlfFuj8S0Jv1xM6KPK7a77IJgDQ-7 X-Proofpoint-GUID: k33LlfFuj8S0Jv1xM6KPK7a77IJgDQ-7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-22_07,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230008 On MSM8974 programming some of the RPM resources results in the "resource does not exist" messages from the firmware. This occurs even with the downstream bus driver, which happily ignores the errors. My assumption is that these resources existed in the earlier firmware revisions but were later switched to be programmed differently (for the later platforms corresponding nodes use qos.ap_owned, which prevents those resources from being programmed. In preparation for conversion of the MSM8974 driver (which doesn't have QoS code yet) to the main icc-rpm set of helpers, let the driver declare that those -ENXIO errors must be ignored (for now). Later, when the QoS programming is sorted out (and more interconnects are added to the DT), this quirk might be removed. Signed-off-by: Dmitry Baryshkov Reviewed-by: Brian Masney Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpm.c | 17 ++++++++++------- drivers/interconnect/qcom/icc-rpm.h | 3 +++ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qco= m/icc-rpm.c index aec2f84cd56f..23a1d116e79a 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -204,7 +204,7 @@ static int qcom_icc_qos_set(struct icc_node *node) } } =20 -static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u64 *bw) +static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u64 *bw, bool ignore= _enxio) { int ret, rpm_ctx =3D 0; u64 bw_bps; @@ -222,8 +222,9 @@ static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u= 64 *bw) bw_bps); if (ret) { pr_err("qcom_icc_rpm_smd_send mas %d error %d\n", - qn->mas_rpm_id, ret); - return ret; + qn->mas_rpm_id, ret); + if (ret !=3D -ENXIO || !ignore_enxio) + return ret; } } =20 @@ -234,8 +235,9 @@ static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u= 64 *bw) bw_bps); if (ret) { pr_err("qcom_icc_rpm_smd_send slv %d error %d\n", - qn->slv_rpm_id, ret); - return ret; + qn->slv_rpm_id, ret); + if (ret !=3D -ENXIO || !ignore_enxio) + return ret; } } } @@ -361,12 +363,12 @@ static int qcom_icc_set(struct icc_node *src, struct = icc_node *dst) active_rate =3D agg_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE]; sleep_rate =3D agg_clk_rate[QCOM_SMD_RPM_SLEEP_STATE]; =20 - ret =3D qcom_icc_rpm_set(src_qn, src_qn->sum_avg); + ret =3D qcom_icc_rpm_set(src_qn, src_qn->sum_avg, qp->ignore_enxio); if (ret) return ret; =20 if (dst_qn) { - ret =3D qcom_icc_rpm_set(dst_qn, dst_qn->sum_avg); + ret =3D qcom_icc_rpm_set(dst_qn, dst_qn->sum_avg, qp->ignore_enxio); if (ret) return ret; } @@ -509,6 +511,7 @@ int qnoc_probe(struct platform_device *pdev) for (i =3D 0; i < cd_num; i++) qp->intf_clks[i].id =3D cds[i]; =20 + qp->ignore_enxio =3D desc->ignore_enxio; qp->keep_alive =3D desc->keep_alive; qp->type =3D desc->type; qp->qos_offset =3D desc->qos_offset; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qco= m/icc-rpm.h index ad554c63967b..7d1cb2efa9ee 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -51,6 +51,7 @@ struct rpm_clk_resource { * @bus_clk: a pointer to a HLOS-owned bus clock * @intf_clks: a clk_bulk_data array of interface clocks * @keep_alive: whether to always keep a minimum vote on the bus clocks + * @ignore_enxio: whether to ignore ENXIO errors (for MSM8974) */ struct qcom_icc_provider { struct icc_provider provider; @@ -65,6 +66,7 @@ struct qcom_icc_provider { struct clk *bus_clk; struct clk_bulk_data *intf_clks; bool keep_alive; + bool ignore_enxio; }; =20 /** @@ -136,6 +138,7 @@ struct qcom_icc_desc { u16 ab_coeff; u16 ib_coeff; int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak); + bool ignore_enxio; }; =20 /* Valid for all bus types */ --=20 2.47.3 From nobody Fri Apr 3 22:13:48 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8030213E7A for ; Mon, 23 Mar 2026 01:17:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228672; cv=none; b=rp3FXCHAD+ge7C3kN/rm/Xv1U/i7kZeQFBN/r9FatfjrCUeSnJv1l7idNp8b3rLFxBbvX38XnJQBw04g8rTEgdw296fILzN/kN8ugII+bkSrlppa7KC4jFj0su0k9i1S7lSt0Pd6EUHRHWLynS5KHkE2w11vSNp2tSbSg6S7bxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228672; c=relaxed/simple; bh=1CMXLbBF5UJ1cF+lSQJT+spR7IYKrLBQpcODBY+BLHA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PAiBsAL9IvrHqYuXfBkfBVqBEzIMXEzrcMmvcIFINpdBx7btUKQwGmD49JBJ2qa27Ix2dNFjBMJIBDcINXf+f1HP6t/6KN8le6VxIIt9GeaveEC3MBad/4CjnAXsp+J5K2kbsG2yTpjkv+q9J5frBs2M5OuPpUeVtHjtab1EdZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=pV8fEx9i; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=JmjH3wzK; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="pV8fEx9i"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="JmjH3wzK" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62M7D6t13737936 for ; Mon, 23 Mar 2026 01:17:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jPZTPpjSRm+LRjpe7M/zsGj1EfuwzS03w8ciKVNoS8s=; b=pV8fEx9iHVR2wMGR 5+jO8MBMAQYTn9ALjYXUPjRh3gNc7MShSz82EB4elDmFAuYafeGLbnfckBHKlZw7 CFAZQRDbCGtyYm1c2cNf9hkelTCNWew+f5TSzIy6ekQDVWVAdfPrtiWkI8YlPnTK ftdtS6BAJo1HkZ/Q5Cgi8zo7u1Ys6f+m3buomm6t+511N6sCzWXH8VbP1e/0a3+m UdV8Y+qzKaQReWGb2h5DP50/dd1X5HNWtVhraY4kcXMPsgRPUfoAyTtQLqGPaI9t qkBdFkY8B3WvKg9Y+DqRzkRIpiSGL36+rcuHZPlkofNeWVp2OpTeJYIYc8vMpuKd YShATg== Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d1mghb4vr-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Mar 2026 01:17:50 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-50b34223670so57094971cf.0 for ; Sun, 22 Mar 2026 18:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774228669; x=1774833469; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jPZTPpjSRm+LRjpe7M/zsGj1EfuwzS03w8ciKVNoS8s=; b=JmjH3wzKG0nCp+bsHTrlzD6Hw9uIHdrTLolng95l+v2SP1fSBe0Z4WOhF+54L5uYBO ecAvc4nxM8mXGQH7OCZudGzSCwf5Et7QE0qe8D0pmrO8C7HzRrpaswBfJFLMBlvD0YXi hVAVGjUjegZbNYM5kcW8HH3t/g+yuFSz9ouguiv/Ap7JY7BEYMd7PqfzvF8tubt6IhS3 LGudBDnLRTsOkbFuHku5qyXPiySICbjkrz+I0lSKUyufDKfZWM4H0RStjYB2IZLZkjC6 BGcKaLJRSD6NWG9VS1vkeCWcwjLQRfk8XR8njKuhGYIE1XFD0agDKCKcSmQuoMtywQ4Z Y1Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774228669; x=1774833469; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=jPZTPpjSRm+LRjpe7M/zsGj1EfuwzS03w8ciKVNoS8s=; b=cZOR+U0IQrHnhMJwZpQ1uNns9VDJzF9u9MeMETjhZEDg9MoyohaRVwaF+koZ06vWge YspHCO3GWXKV6aLO9iIEIGptrcn3sM0OYH2Fd2a4G0Pj8n8J4gaaEGh+J7eYFw+sWahh IbrglzGVq6yg4yHiNBEDoem2lNZUC6cRPkETerQKE3brBTi76x54nWTPRC1ILrPq8i0h rCt3SO8+c1t9tuhHdVuJ8veHL6vKX3fYZJCTHqVvRRc6xH8uP4B2cvUoqszZglSf8Svx oSYSSajitd0Jzvd/Iz0Np+8GX7k85k26txa/d79Y72I2SlfoTUdlPAOcujWnlp6VCvJh IDYQ== X-Forwarded-Encrypted: i=1; AJvYcCWOdQKbUMIHCvBP37l0vJUuG7v45DjcYlcw+x0FmJ8/Ch+0hfKboBEdWbpjz55dHK4mdk3SSSvPwbhElPY=@vger.kernel.org X-Gm-Message-State: AOJu0Yw1KekTSY5HUteSA3bQjcww/akGvkcJCUPta1k1EZx0n3vd+gfT NTff8z4sS/TkxBgDg4IQeocbz03vJpRIegaq/f+0k/bzGEtJDnkDDiEhck+mZ9RWjCJo/s1363M vWdUJh1GzU+K+6ewnFrXe9AhajavUJRamBINCe40fQio4I2upgYs60va4s3kvrARs0Kg= X-Gm-Gg: ATEYQzxeW6tvc8nnlYiiyFPLHrTC2YOPGPO/xALCjxeMWNtPPGnPH6svtSB2jwoLHqp 7fKZrHZz/RHbShK2V9yl7pFSv0tsUqqp6RWKKiTTdpOm7qrXioVx7Mp5FFCW0RWXFbj04CPGnVt S+WDzlLaQpMsTGcfKRNQ7ut3ZTmiySedFUjsRHqW3XAtBFfksTgZpYMi3iFrCFBYKZUUV6zhp2p axqb0Dn3JEYFbSAwSus2eoRxRQ02Z7v1OjYue5ByT6/6ce0SIFuxjYActYep2N1VU8g+Pj9xuXI mDZd4JpwNxI7nWUmx2vaAA6/qJNKQlM3+9hp0BnssEwo9JGjWj77UGeVpqa/Bjk5o0AemU7MWaA X7Q4tIebnmpHdRBrut+IS0tV3rwhPfTUGxOgR3RKa7PSwMWeysw9hA1EJPrT2+BUq/sdZUXyIJL 6mXCNdAb1qfqWfiNOBxpJXKpltQUMc5InAq+0= X-Received: by 2002:a05:622a:354:b0:506:9bea:3229 with SMTP id d75a77b69052e-50b375d6367mr161626301cf.69.1774228668905; Sun, 22 Mar 2026 18:17:48 -0700 (PDT) X-Received: by 2002:a05:622a:354:b0:506:9bea:3229 with SMTP id d75a77b69052e-50b375d6367mr161626041cf.69.1774228668407; Sun, 22 Mar 2026 18:17:48 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2853050e7sm2216150e87.61.2026.03.22.18.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 18:17:45 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 03:17:23 +0200 Subject: [PATCH 7/9] interconnect: qcom: msm8974: switch to the main icc-rpm driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-msm8974-icc-v1-7-7892b8d5f2ea@oss.qualcomm.com> References: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> In-Reply-To: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> To: Georgi Djakov , Konrad Dybcio , Bjorn Andersson , Luca Weiss , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=14953; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=1CMXLbBF5UJ1cF+lSQJT+spR7IYKrLBQpcODBY+BLHA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpwJSfcqH9q4hqksniaVw3TkffTaoBRbGsdYMym yzj3x92n2SJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCacCUnwAKCRCLPIo+Aiko 1dKnB/47uptj5qPHeglDhgs+zIlZCaeXPkeZ8t1oYqK/GVg39eVz4yqwd1rqdvz6LdN32jq96OB fhJcYQ1eCadti6DlbtJ1aZL+GGj35B6U29LmPoBGPY0CdnOR5U8rog/YuPDrakMZgp5ZiBOgyXO 2odW+7yWaWrxWrjijkfkJhVd0u3HErUQEgA4zMIxkhjFYDeyBPO3vALR0sed0IcDiHmjGRzjCPV SEEkcc1XJx272XM7b6DnZyZnEi7gyiDE6YqOUkbwYtguR4xHoQKX+ImFg7Y6mku9qAbjUhR6yrp +DGY8LEF1chuDvv4h0ZOu6LN6PYsu9IkGfPKEDoVHeIHvrbN X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=HI7O14tv c=1 sm=1 tr=0 ts=69c094be cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=vNxNlsk0RTatv9OKPSEA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: -Bn8nBCWVPIsKIWxIiphae1vtg2LI3wQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAwOCBTYWx0ZWRfX5AEAVCh9nD5f PTiqpPLfWqCtyOgur4e0GRQsarIOlb6EJ48EK5USLvFtKk5K05M8WmB/m/qVTuMPvk3GV01D+0R KLIrEGcK6RJ18xuij8F8CKGnaOSFA+LjIhrScVvBnefNRpMAU4vuB65Af76hWeSAq49oS/K5e6a 8nWK1uvd70Vy6Ft1B/ZjgKkduXfetrmDzpaO7s5U4HTwza9A3Q2o+T+CnqFI+ScCKRaQQmnyYqf 3gNn87XsqZ5nh1myK9FZS8eO3WTjMV+mKJMg0KIFpErUfUoGccG3luFsqaSQfnVR+yNFitNvnmY SuwQv2z1/71opGavR1t/k0rCzZjRjQ/HBS9Eqx0xDd/IqPLPtAUQ7vIrBAFx+zzxU1h+Z/IuDd0 GFIwO+xmeX2zbJ9WtyB7BnyNhRMzW2ZDrN1RwPXYPz/TfNGkW6alQTVi9GXZFvrOGbI6C0nbdxw K3pF5nvhkRAcxslKyHw== X-Proofpoint-GUID: -Bn8nBCWVPIsKIWxIiphae1vtg2LI3wQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-22_07,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 phishscore=0 malwarescore=0 bulkscore=0 impostorscore=0 suspectscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230008 In preparation to restoring the ability of MSM8974 driver to work with the modern kernels, switch the driver to the main icc-rpm set of helper code. As platform-specific workarounds, set the get_bw callback (returning 0) to prevent initial setup from programming INT_MAX into the RPM (which otherwise might hang the platform) and tell RPM programming code to ignore -ENXIO errors from the firmware (until the QoS programming is sorted out). Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/msm8974.c | 304 +++++---------------------------= ---- 1 file changed, 43 insertions(+), 261 deletions(-) diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qco= m/msm8974.c index 3239edc37f02..144f225ec885 100644 --- a/drivers/interconnect/qcom/msm8974.c +++ b/drivers/interconnect/qcom/msm8974.c @@ -173,65 +173,27 @@ enum { MSM8974_SNOC_SLV_QDSS_STM, }; =20 -#define to_msm8974_icc_provider(_provider) \ - container_of(_provider, struct msm8974_icc_provider, provider) - -static const struct clk_bulk_data msm8974_icc_bus_clocks[] =3D { - { .id =3D "bus" }, - { .id =3D "bus_a" }, -}; - -/** - * struct msm8974_icc_provider - Qualcomm specific interconnect provider - * @provider: generic interconnect provider - * @bus_clks: the clk_bulk_data table of bus clocks - * @num_clks: the total number of clk_bulk_data entries - */ -struct msm8974_icc_provider { - struct icc_provider provider; - struct clk_bulk_data *bus_clks; - int num_clks; -}; - -#define MSM8974_ICC_MAX_LINKS 3 - -/** - * struct msm8974_icc_node - Qualcomm specific interconnect nodes - * @name: the node name used in debugfs - * @id: a unique node identifier - * @links: an array of nodes where we can go next while traversing - * @num_links: the total number of @links - * @buswidth: width of the interconnect between a node and the bus (bytes) - * @mas_rpm_id: RPM ID for devices that are bus masters - * @slv_rpm_id: RPM ID for devices that are bus slaves - * @rate: current bus clock rate in Hz - */ -struct msm8974_icc_node { - unsigned char *name; - u16 id; - u16 links[MSM8974_ICC_MAX_LINKS]; - u16 num_links; - u16 buswidth; - int mas_rpm_id; - int slv_rpm_id; - u64 rate; -}; +static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak) +{ + *avg =3D 0; + *peak =3D 0; =20 -struct msm8974_icc_desc { - struct msm8974_icc_node * const *nodes; - size_t num_nodes; + return 0; }; =20 #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ ...) \ - static struct msm8974_icc_node _name =3D { \ + static const u16 _name ## _links[] =3D { \ + __VA_ARGS__ \ + }; \ + static struct qcom_icc_node _name =3D { \ .name =3D #_name, \ .id =3D _id, \ .buswidth =3D _buswidth, \ .mas_rpm_id =3D _mas_rpm_id, \ .slv_rpm_id =3D _slv_rpm_id, \ - .num_links =3D COUNT_ARGS(__VA_ARGS__), \ - .links =3D { __VA_ARGS__ }, \ + .num_links =3D ARRAY_SIZE(_name ## _links), \ + .links =3D _name ## _links, \ } =20 DEFINE_QNODE(mas_ampss_m0, MSM8974_BIMC_MAS_AMPSS_M0, 8, 0, -1); @@ -242,7 +204,7 @@ DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, = 2, MSM8974_SNOC_TO_BIMC, DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0); DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1); =20 -static struct msm8974_icc_node * const msm8974_bimc_nodes[] =3D { +static struct qcom_icc_node * const msm8974_bimc_nodes[] =3D { [BIMC_MAS_AMPSS_M0] =3D &mas_ampss_m0, [BIMC_MAS_AMPSS_M1] =3D &mas_ampss_m1, [BIMC_MAS_MSS_PROC] =3D &mas_mss_proc, @@ -252,9 +214,12 @@ static struct msm8974_icc_node * const msm8974_bimc_no= des[] =3D { [BIMC_SLV_AMPSS_L2] =3D &slv_ampss_l2, }; =20 -static const struct msm8974_icc_desc msm8974_bimc =3D { +static const struct qcom_icc_desc msm8974_bimc =3D { .nodes =3D msm8974_bimc_nodes, .num_nodes =3D ARRAY_SIZE(msm8974_bimc_nodes), + .bus_clk_desc =3D &bimc_clk, + .get_bw =3D msm8974_get_bw, + .ignore_enxio =3D true, }; =20 DEFINE_QNODE(mas_rpm_inst, MSM8974_CNOC_MAS_RPM_INST, 8, 45, -1); @@ -295,7 +260,7 @@ DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PH= Y_CFG, 8, -1, 73); DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74); DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76); =20 -static struct msm8974_icc_node * const msm8974_cnoc_nodes[] =3D { +static struct qcom_icc_node * const msm8974_cnoc_nodes[] =3D { [CNOC_MAS_RPM_INST] =3D &mas_rpm_inst, [CNOC_MAS_RPM_DATA] =3D &mas_rpm_data, [CNOC_MAS_RPM_SYS] =3D &mas_rpm_sys, @@ -335,9 +300,12 @@ static struct msm8974_icc_node * const msm8974_cnoc_no= des[] =3D { [CNOC_SLV_SERVICE_CNOC] =3D &slv_service_cnoc, }; =20 -static const struct msm8974_icc_desc msm8974_cnoc =3D { +static const struct qcom_icc_desc msm8974_cnoc =3D { .nodes =3D msm8974_cnoc_nodes, .num_nodes =3D ARRAY_SIZE(msm8974_cnoc_nodes), + .bus_clk_desc =3D &bus_2_clk, + .get_bw =3D msm8974_get_bw, + .ignore_enxio =3D true, }; =20 DEFINE_QNODE(mas_graphics_3d, MSM8974_MNOC_MAS_GRAPHICS_3D, 16, 6, -1, MSM= 8974_MNOC_TO_BIMC); @@ -363,7 +331,7 @@ DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MP= U_CFG, 16, -1, 14); DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15); DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17); =20 -static struct msm8974_icc_node * const msm8974_mnoc_nodes[] =3D { +static struct qcom_icc_node * const msm8974_mnoc_nodes[] =3D { [MNOC_MAS_GRAPHICS_3D] =3D &mas_graphics_3d, [MNOC_MAS_JPEG] =3D &mas_jpeg, [MNOC_MAS_MDP_PORT0] =3D &mas_mdp_port0, @@ -388,9 +356,11 @@ static struct msm8974_icc_node * const msm8974_mnoc_no= des[] =3D { [MNOC_SLV_SERVICE_MNOC] =3D &slv_service_mnoc, }; =20 -static const struct msm8974_icc_desc msm8974_mnoc =3D { +static const struct qcom_icc_desc msm8974_mnoc =3D { .nodes =3D msm8974_mnoc_nodes, .num_nodes =3D ARRAY_SIZE(msm8974_mnoc_nodes), + .get_bw =3D msm8974_get_bw, + .ignore_enxio =3D true, }; =20 DEFINE_QNODE(ocmem_noc_to_ocmem_vnoc, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, 16,= 54, 78, MSM8974_OCMEM_SLV_OCMEM); @@ -408,7 +378,7 @@ DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_= OCMEM_NOC, 16, 56, 79, MS DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80); DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, M= SM8974_OCMEM_VNOC_TO_OCMEM_NOC); =20 -static struct msm8974_icc_node * const msm8974_onoc_nodes[] =3D { +static struct qcom_icc_node * const msm8974_onoc_nodes[] =3D { [OCMEM_NOC_TO_OCMEM_VNOC] =3D &ocmem_noc_to_ocmem_vnoc, [OCMEM_MAS_JPEG_OCMEM] =3D &mas_jpeg_ocmem, [OCMEM_MAS_MDP_OCMEM] =3D &mas_mdp_ocmem, @@ -423,9 +393,12 @@ static struct msm8974_icc_node * const msm8974_onoc_no= des[] =3D { [OCMEM_SLV_OCMEM] =3D &slv_ocmem, }; =20 -static const struct msm8974_icc_desc msm8974_onoc =3D { +static const struct qcom_icc_desc msm8974_onoc =3D { .nodes =3D msm8974_onoc_nodes, .num_nodes =3D ARRAY_SIZE(msm8974_onoc_nodes), + .bus_clk_desc =3D &gpu_mem_2_clk, + .get_bw =3D msm8974_get_bw, + .ignore_enxio =3D true, }; =20 DEFINE_QNODE(mas_pnoc_cfg, MSM8974_PNOC_MAS_PNOC_CFG, 8, 43, -1); @@ -456,7 +429,7 @@ DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MP= U_CFG, 8, -1, 43); DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_S= NOC); DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46); =20 -static struct msm8974_icc_node * const msm8974_pnoc_nodes[] =3D { +static struct qcom_icc_node * const msm8974_pnoc_nodes[] =3D { [PNOC_MAS_PNOC_CFG] =3D &mas_pnoc_cfg, [PNOC_MAS_SDCC_1] =3D &mas_sdcc_1, [PNOC_MAS_SDCC_3] =3D &mas_sdcc_3, @@ -486,9 +459,13 @@ static struct msm8974_icc_node * const msm8974_pnoc_no= des[] =3D { [PNOC_SLV_SERVICE_PNOC] =3D &slv_service_pnoc, }; =20 -static const struct msm8974_icc_desc msm8974_pnoc =3D { +static const struct qcom_icc_desc msm8974_pnoc =3D { .nodes =3D msm8974_pnoc_nodes, .num_nodes =3D ARRAY_SIZE(msm8974_pnoc_nodes), + .bus_clk_desc =3D &bus_0_clk, + .get_bw =3D msm8974_get_bw, + .keep_alive =3D true, + .ignore_enxio =3D true, }; =20 DEFINE_QNODE(mas_lpass_ahb, MSM8974_SNOC_MAS_LPASS_AHB, 8, 18, -1); @@ -516,7 +493,7 @@ DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCME= M, 8, -1, 27); DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29); DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30); =20 -static struct msm8974_icc_node * const msm8974_snoc_nodes[] =3D { +static struct qcom_icc_node * const msm8974_snoc_nodes[] =3D { [SNOC_MAS_LPASS_AHB] =3D &mas_lpass_ahb, [SNOC_MAS_QDSS_BAM] =3D &mas_qdss_bam, [SNOC_MAS_SNOC_CFG] =3D &mas_snoc_cfg, @@ -543,209 +520,14 @@ static struct msm8974_icc_node * const msm8974_snoc_= nodes[] =3D { [SNOC_SLV_QDSS_STM] =3D &slv_qdss_stm, }; =20 -static const struct msm8974_icc_desc msm8974_snoc =3D { +static const struct qcom_icc_desc msm8974_snoc =3D { .nodes =3D msm8974_snoc_nodes, .num_nodes =3D ARRAY_SIZE(msm8974_snoc_nodes), + .bus_clk_desc =3D &bus_1_clk, + .get_bw =3D msm8974_get_bw, + .ignore_enxio =3D true, }; =20 -static void msm8974_icc_rpm_smd_send(struct device *dev, int rsc_type, - char *name, int id, u64 val) -{ - int ret; - - if (id =3D=3D -1) - return; - - /* - * Setting the bandwidth requests for some nodes fails and this same - * behavior occurs on the downstream MSM 3.4 kernel sources based on - * errors like this in that kernel: - * - * msm_rpm_get_error_from_ack(): RPM NACK Unsupported resource - * AXI: msm_bus_rpm_req(): RPM: Ack failed - * AXI: msm_bus_rpm_commit_arb(): RPM: Req fail: mas:32, bw:240000000 - * - * Since there's no publicly available documentation for this hardware, - * and the bandwidth for some nodes in the path can be set properly, - * let's not return an error. - */ - ret =3D qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, rsc_type, id, - val); - if (ret) - dev_dbg(dev, "Cannot set bandwidth for node %s (%d): %d\n", - name, id, ret); -} - -static int msm8974_icc_set(struct icc_node *src, struct icc_node *dst) -{ - struct msm8974_icc_node *src_qn, *dst_qn; - struct msm8974_icc_provider *qp; - u64 sum_bw, max_peak_bw, rate; - u32 agg_avg =3D 0, agg_peak =3D 0; - struct icc_provider *provider; - struct icc_node *n; - int ret, i; - - src_qn =3D src->data; - dst_qn =3D dst->data; - provider =3D src->provider; - qp =3D to_msm8974_icc_provider(provider); - - list_for_each_entry(n, &provider->nodes, node_list) - provider->aggregate(n, 0, n->avg_bw, n->peak_bw, - &agg_avg, &agg_peak); - - sum_bw =3D icc_units_to_bps(agg_avg); - max_peak_bw =3D icc_units_to_bps(agg_peak); - - /* Set bandwidth on source node */ - msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ, - src_qn->name, src_qn->mas_rpm_id, sum_bw); - - msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ, - src_qn->name, src_qn->slv_rpm_id, sum_bw); - - /* Set bandwidth on destination node */ - msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ, - dst_qn->name, dst_qn->mas_rpm_id, sum_bw); - - msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ, - dst_qn->name, dst_qn->slv_rpm_id, sum_bw); - - rate =3D max(sum_bw, max_peak_bw); - - do_div(rate, src_qn->buswidth); - - rate =3D min_t(u32, rate, INT_MAX); - - if (src_qn->rate =3D=3D rate) - return 0; - - for (i =3D 0; i < qp->num_clks; i++) { - ret =3D clk_set_rate(qp->bus_clks[i].clk, rate); - if (ret) { - dev_err(provider->dev, "%s clk_set_rate error: %d\n", - qp->bus_clks[i].id, ret); - ret =3D 0; - } - } - - src_qn->rate =3D rate; - - return 0; -} - -static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak) -{ - *avg =3D 0; - *peak =3D 0; - - return 0; -} - -static int msm8974_icc_probe(struct platform_device *pdev) -{ - const struct msm8974_icc_desc *desc; - struct msm8974_icc_node * const *qnodes; - struct msm8974_icc_provider *qp; - struct device *dev =3D &pdev->dev; - struct icc_onecell_data *data; - struct icc_provider *provider; - struct icc_node *node; - size_t num_nodes, i; - int ret; - - /* wait for the RPM proxy */ - if (!qcom_icc_rpm_smd_available()) - return -EPROBE_DEFER; - - desc =3D of_device_get_match_data(dev); - if (!desc) - return -EINVAL; - - qnodes =3D desc->nodes; - num_nodes =3D desc->num_nodes; - - qp =3D devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL); - if (!qp) - return -ENOMEM; - - data =3D devm_kzalloc(dev, struct_size(data, nodes, num_nodes), - GFP_KERNEL); - if (!data) - return -ENOMEM; - data->num_nodes =3D num_nodes; - - qp->bus_clks =3D devm_kmemdup(dev, msm8974_icc_bus_clocks, - sizeof(msm8974_icc_bus_clocks), GFP_KERNEL); - if (!qp->bus_clks) - return -ENOMEM; - - qp->num_clks =3D ARRAY_SIZE(msm8974_icc_bus_clocks); - ret =3D devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); - if (ret) - return ret; - - ret =3D clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks); - if (ret) - return ret; - - provider =3D &qp->provider; - provider->dev =3D dev; - provider->set =3D msm8974_icc_set; - provider->aggregate =3D icc_std_aggregate; - provider->xlate =3D of_icc_xlate_onecell; - provider->data =3D data; - provider->get_bw =3D msm8974_get_bw; - - icc_provider_init(provider); - - for (i =3D 0; i < num_nodes; i++) { - size_t j; - - node =3D icc_node_create(qnodes[i]->id); - if (IS_ERR(node)) { - ret =3D PTR_ERR(node); - goto err_remove_nodes; - } - - node->name =3D qnodes[i]->name; - node->data =3D qnodes[i]; - icc_node_add(node, provider); - - dev_dbg(dev, "registered node %s\n", node->name); - - /* populate links */ - for (j =3D 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); - - data->nodes[i] =3D node; - } - - ret =3D icc_provider_register(provider); - if (ret) - goto err_remove_nodes; - - platform_set_drvdata(pdev, qp); - - return 0; - -err_remove_nodes: - icc_nodes_remove(provider); - clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); - - return ret; -} - -static void msm8974_icc_remove(struct platform_device *pdev) -{ - struct msm8974_icc_provider *qp =3D platform_get_drvdata(pdev); - - icc_provider_deregister(&qp->provider); - icc_nodes_remove(&qp->provider); - clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); -} - static const struct of_device_id msm8974_noc_of_match[] =3D { { .compatible =3D "qcom,msm8974-bimc", .data =3D &msm8974_bimc}, { .compatible =3D "qcom,msm8974-cnoc", .data =3D &msm8974_cnoc}, @@ -758,8 +540,8 @@ static const struct of_device_id msm8974_noc_of_match[]= =3D { MODULE_DEVICE_TABLE(of, msm8974_noc_of_match); =20 static struct platform_driver msm8974_noc_driver =3D { - .probe =3D msm8974_icc_probe, - .remove =3D msm8974_icc_remove, + .probe =3D qnoc_probe, + .remove =3D qnoc_remove, .driver =3D { .name =3D "qnoc-msm8974", .of_match_table =3D msm8974_noc_of_match, --=20 2.47.3 From nobody Fri Apr 3 22:13:48 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5088F1B424F for ; Mon, 23 Mar 2026 01:17:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228679; cv=none; b=TN6sKxF9lvlTeL8ImHM/IEJjQEnYqhQvSxg2+pesEWXD2tmymraBjztuVANeV6pj3s4QYAJ9hG6Ll0+J6IV3xS9oUxZsK8el/60E5eNdq6q6kHyjIlJFFrtN10FG+db5H8jiJQWz+9xycEs3+w0XPHx6xqyHZXWU+NtGL9LVsRM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228679; c=relaxed/simple; bh=xlgANSYz1nVuAn+eEd8ORnd+MmVt2YDubhoEruEPI8k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Et6BJC6O040E22Bu0Amze/CdL8y6MC6dmwIylpCGJV8Xo5rXaBnDbnmk2UDXqbANo3qGiYFmx8WmOM8zdFMjS+BVT6RzUbVfG4pFPjpSXk69uD/X0IlYBNOEXQm3RmhwkXIdGaGqS52DxY8VW+hoBmcGX+UsFV1Bf520BKT2f+o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=FbYVYGPx; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ch8ZXMg7; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="FbYVYGPx"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ch8ZXMg7" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62MNms3w1231689 for ; Mon, 23 Mar 2026 01:17:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= G9LTxh8oFF0MTnQoxhWBFdZ1ygvExjdzayTcMvG/8ts=; b=FbYVYGPxUpc+l0EO Qtjw6wr/sUjP7j0qnKKoFQkjb6PwaApYNDyen284U2cmQP0uRPa+JUAJf4qszN47 yedAegX5VqqAG13ovsMzmF/7AjKGEd8xgBXr8kSSucbwggqLh5Mncwc8HxX9Cm3v OHsH6m+yKcv2MAAhhd4sFJpMvxddcIvf+BY4lcnlJIVMQbaMCZ6RxisrIV4UfXdp X9y/Y+Zjv5WDllOG/xZH1dFCyaOcob+tcxRq2CSTJsJUjJLpVp1lSr3u35eNfDiX dvxl/UL+jjQZgVzbZxZwH/WxyAG522woz5jjNsqYzcvpxS60nB7QoQVDqaph3JGg d2o2+Q== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d1j9rb9vk-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Mar 2026 01:17:54 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-50937cf66b5so35477091cf.3 for ; Sun, 22 Mar 2026 18:17:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774228673; x=1774833473; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=G9LTxh8oFF0MTnQoxhWBFdZ1ygvExjdzayTcMvG/8ts=; b=ch8ZXMg7ZmsY3RhkgDcGWQ1R6fMbYQWdoUwa3KcCgfGWc/nuWgMNf44IZk+OwO9DXH EAS1tTRaBbU0rfQ4DfJaj+rtcLWNVtAzdBWFSf5ffuQ6OJXcqYc6qR1yzcNzXeqJJ0CA X78B8ZUfWXUKG7+FRNVZjk6i48kFDpfdbX/m6/DxsQw8XSHpfUjEY7d9mA2jvPJ/DCyJ +nKbDLKDXPQygRJdPzwHEjmvpAym2E07zXDlnRCPZgsYhdFsOHji5zwtq9AC4OV656S0 bx3gMIpSeOBxJILwWLw2FhzhV8neoOy0jR7mIrfKKf6xYPzsSoYO4aluDpujAvnBUrsb Kd9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774228673; x=1774833473; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=G9LTxh8oFF0MTnQoxhWBFdZ1ygvExjdzayTcMvG/8ts=; b=WfQKR0mnu0/K8gVqXCvJMuWE4tZTdDZ4PzIcnjL0vIpKee1gvTx4Bom+QbjBwC1NC/ hOfGLFu8p9heMLP0t/dnTfY0hSL+q0q6UDdxcxwOy4J+PeTPZ2yBtNXXErUvkfu3KJlM cMLHoCfEYayg1k4JGOhv89t2ccNqpiwliNTSZ9PRSAZoC2UbxSC4+GiqOy8+r/ffOcm/ Az6Knj0uWjqseTRdd+zOLiWqF+AsE3NG3cjWypzw7kmd1ugSkVE5gGYMgrds5x6A2I6i LveMZkXrWFeA+hUqQ5ikZORO3bV/d9rNlP5qXOpP4QXJWbWvz8eCPRXI9vTWLLd8YYN2 PbKQ== X-Forwarded-Encrypted: i=1; AJvYcCUjeDp8x2nhcHrnzAmOmC9Dfse78KzIPCJibphext3evxRAJ6hH4IAzKy6GrHEUwdiZOYgleHC691fNUzU=@vger.kernel.org X-Gm-Message-State: AOJu0YyiUpGZjTXSL8xRuoydXAcDeIM7CFPweDXnCgx6zhQF5TPR3jf1 PiBYkiOn+evImnU6bDSpQ0JLpE0iXNiHtgVaFZ7Bm56d9VmTnYB7y6ZBRmCXhohglDF/a7hBl+W gNB4aV9hmFOtDjczx+dQw9YBrvDqQbmxB/gA9JAiUOueby8DupMInDRZK+E2kI0vV3W8= X-Gm-Gg: ATEYQzyeb+U90XZJazTYD1BtdlHUzByVQPgS1FzLrEuWncoqWVR4TOL2yS9bvPgpyYJ mcEkausTMADFr2gldhv4LMFz4ULzAWdvpt8JPLb17FmyEs1aKDuCzclI1GRwhToO5/v7/9JdGBH HfGTfuoqgSy2bxT6NTYaqZzu+Hfjt07OVLILRESTtWOtx27ONOVaG0OhwmLsFJ1AB1LyAfoPmCT EeFoz/QYxvPw5/ZiHHExrRd4j0ym40yaB1ZtAeGY9rW8r1hUPKiLOOsib1yz1kqN05+ErU+vSaq tBOaaEi6ErmmSgquTV9WTHSnEj728ORVGQPS8qZZrZe0RSwrWAxrubylwwNcgvWndkf/vbwza2D +V61brHIrTaXF/2dvfTvMtRDTcl+hk3aTvOT6o8kdbm6W/pT7It1oxTbeLnbUXDeKsBQc4/vnWB YzbLuBIPwrgs7UGliPEH8/mWNUT2x6uyBVWvw= X-Received: by 2002:a05:622a:8c4:b0:509:2527:d789 with SMTP id d75a77b69052e-50b373bdd66mr181422361cf.6.1774228673139; Sun, 22 Mar 2026 18:17:53 -0700 (PDT) X-Received: by 2002:a05:622a:8c4:b0:509:2527:d789 with SMTP id d75a77b69052e-50b373bdd66mr181421841cf.6.1774228672517; Sun, 22 Mar 2026 18:17:52 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2853050e7sm2216150e87.61.2026.03.22.18.17.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 18:17:50 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 03:17:24 +0200 Subject: [PATCH 8/9] interconnect: qcom: msm8974: expand DEFINE_QNODE macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-msm8974-icc-v1-8-7892b8d5f2ea@oss.qualcomm.com> References: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> In-Reply-To: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> To: Georgi Djakov , Konrad Dybcio , Bjorn Andersson , Luca Weiss , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=39567; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=xlgANSYz1nVuAn+eEd8ORnd+MmVt2YDubhoEruEPI8k=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpwJSfmpZhiiic1ahhJPUH6MjVOvgCX8qqMprOK LfKm7fiGn2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCacCUnwAKCRCLPIo+Aiko 1Qj3B/9Cg/TDyLrWwF27sRNrwFllBexpv014AQKruFBM3+5sGSo/tc1aSh9wo/c4J/Hbwqyfpj/ De4tEuxCpjK+hGQcfNIB2MTxnN/06ly5HxquOFUHGZ9qe6ZSexfOzRwKUi+/bZsSXpPvuc3IH0C AjBtOo+8FF+jCWVX20nzR6u0JkfsY0Vf/JkQDNwrMLrfc1utVyXldK7xSpuaocrW6LNCh9YBULM z75sLbtUyjrXiOs00mTha6XL1OtmOM/xtiM9asZAOTk+st+xvGsiN5rkr+pZ10GZ0K4epQBkPPt mchBBb8r493aTmOxwBhQXJRDcQlXrTPtgqLDExU8XmmKchKp X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: ZkRyvor2cjX-O6Yg944VPjKJKDei20xd X-Authority-Analysis: v=2.4 cv=ZPDaWH7b c=1 sm=1 tr=0 ts=69c094c2 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=gU3Gd9FrbIblE3rB6ncA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAwOCBTYWx0ZWRfX9E6G/qZjsrn3 jkLn3PtqJ8JqjiU82XnffcWAw1EF9FhItA1y+GM1cQt3a8i2joNswDugfapC+ZYV+/it1IdCTxx uv3/ImF8I7hO/vqGzseIbvgFUZAcATPUveNKPoDG3puwWHwqS7v5UeJ2yKLdotAMsnfQpbiffu1 yu6mOQpagOnUjy1es4exq0BCuseG6U4wb7+S9Q+jWChLJFgQizp1FeYrhzG3Y8WlfzkhS5Z6doD NxoUm+X3XCNoipZs06AxeTA4u5XwByV3/DY9rlM9xc6CT6uaJxNiEc6VN8eNC9M8Iz3zQlxTt4f dsGuS/wAuz75l2ZJxxcvmNmTBNT4pjMLpgdwsEGrVpfL5xMRxlL7gRUp4lbZ1BGMKx7/wPjqr9/ 5+CWecTxtsOOmNe3lU0lPgLGjbHFOfdSTX24ihKjwYRTAdIobeL5CwGziQFdXopDQF42s4b83xm ExYqwqZkv2vJCjaGFhw== X-Proofpoint-GUID: ZkRyvor2cjX-O6Yg944VPjKJKDei20xd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-22_07,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 impostorscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230008 The rest of Qualcomm Interconnect drivers have stopped using DEFINE_QNODE long ago for the sake of readability. Stop using it inside the msm8974 interconnect driver too. Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio --- drivers/interconnect/qcom/msm8974.c | 1335 +++++++++++++++++++++++++++++++= ---- 1 file changed, 1191 insertions(+), 144 deletions(-) diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qco= m/msm8974.c index 144f225ec885..c020c61126ca 100644 --- a/drivers/interconnect/qcom/msm8974.c +++ b/drivers/interconnect/qcom/msm8974.c @@ -181,28 +181,75 @@ static int msm8974_get_bw(struct icc_node *node, u32 = *avg, u32 *peak) return 0; }; =20 -#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ - ...) \ - static const u16 _name ## _links[] =3D { \ - __VA_ARGS__ \ - }; \ - static struct qcom_icc_node _name =3D { \ - .name =3D #_name, \ - .id =3D _id, \ - .buswidth =3D _buswidth, \ - .mas_rpm_id =3D _mas_rpm_id, \ - .slv_rpm_id =3D _slv_rpm_id, \ - .num_links =3D ARRAY_SIZE(_name ## _links), \ - .links =3D _name ## _links, \ - } - -DEFINE_QNODE(mas_ampss_m0, MSM8974_BIMC_MAS_AMPSS_M0, 8, 0, -1); -DEFINE_QNODE(mas_ampss_m1, MSM8974_BIMC_MAS_AMPSS_M1, 8, 0, -1); -DEFINE_QNODE(mas_mss_proc, MSM8974_BIMC_MAS_MSS_PROC, 8, 1, -1); -DEFINE_QNODE(bimc_to_mnoc, MSM8974_BIMC_TO_MNOC, 8, 2, -1, MSM8974_BIMC_SL= V_EBI_CH0); -DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, 2, MSM8974_SNOC_TO_= BIMC, MSM8974_BIMC_SLV_EBI_CH0, MSM8974_BIMC_MAS_AMPSS_M0); -DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0); -DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1); +static struct qcom_icc_node mas_ampss_m0 =3D { + .name =3D "mas_ampss_m0", + .id =3D MSM8974_BIMC_MAS_AMPSS_M0, + .buswidth =3D 8, + .mas_rpm_id =3D 0, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_ampss_m1 =3D { + .name =3D "mas_ampss_m1", + .id =3D MSM8974_BIMC_MAS_AMPSS_M1, + .buswidth =3D 8, + .mas_rpm_id =3D 0, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_mss_proc =3D { + .name =3D "mas_mss_proc", + .id =3D MSM8974_BIMC_MAS_MSS_PROC, + .buswidth =3D 8, + .mas_rpm_id =3D 1, + .slv_rpm_id =3D -1, +}; + +static const u16 bimc_to_mnoc_links[] =3D { + MSM8974_BIMC_SLV_EBI_CH0 +}; + +static struct qcom_icc_node bimc_to_mnoc =3D { + .name =3D "bimc_to_mnoc", + .id =3D MSM8974_BIMC_TO_MNOC, + .buswidth =3D 8, + .mas_rpm_id =3D 2, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(bimc_to_mnoc_links), + .links =3D bimc_to_mnoc_links, +}; + +static const u16 bimc_to_snoc_links[] =3D { + MSM8974_SNOC_TO_BIMC, + MSM8974_BIMC_SLV_EBI_CH0, + MSM8974_BIMC_MAS_AMPSS_M0 +}; + +static struct qcom_icc_node bimc_to_snoc =3D { + .name =3D "bimc_to_snoc", + .id =3D MSM8974_BIMC_TO_SNOC, + .buswidth =3D 8, + .mas_rpm_id =3D 3, + .slv_rpm_id =3D 2, + .num_links =3D ARRAY_SIZE(bimc_to_snoc_links), + .links =3D bimc_to_snoc_links, +}; + +static struct qcom_icc_node slv_ebi_ch0 =3D { + .name =3D "slv_ebi_ch0", + .id =3D MSM8974_BIMC_SLV_EBI_CH0, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 0, +}; + +static struct qcom_icc_node slv_ampss_l2 =3D { + .name =3D "slv_ampss_l2", + .id =3D MSM8974_BIMC_SLV_AMPSS_L2, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 1, +}; =20 static struct qcom_icc_node * const msm8974_bimc_nodes[] =3D { [BIMC_MAS_AMPSS_M0] =3D &mas_ampss_m0, @@ -222,43 +269,301 @@ static const struct qcom_icc_desc msm8974_bimc =3D { .ignore_enxio =3D true, }; =20 -DEFINE_QNODE(mas_rpm_inst, MSM8974_CNOC_MAS_RPM_INST, 8, 45, -1); -DEFINE_QNODE(mas_rpm_data, MSM8974_CNOC_MAS_RPM_DATA, 8, 46, -1); -DEFINE_QNODE(mas_rpm_sys, MSM8974_CNOC_MAS_RPM_SYS, 8, 47, -1); -DEFINE_QNODE(mas_dehr, MSM8974_CNOC_MAS_DEHR, 8, 48, -1); -DEFINE_QNODE(mas_qdss_dap, MSM8974_CNOC_MAS_QDSS_DAP, 8, 49, -1); -DEFINE_QNODE(mas_spdm, MSM8974_CNOC_MAS_SPDM, 8, 50, -1); -DEFINE_QNODE(mas_tic, MSM8974_CNOC_MAS_TIC, 8, 51, -1); -DEFINE_QNODE(slv_clk_ctl, MSM8974_CNOC_SLV_CLK_CTL, 8, -1, 47); -DEFINE_QNODE(slv_cnoc_mss, MSM8974_CNOC_SLV_CNOC_MSS, 8, -1, 48); -DEFINE_QNODE(slv_security, MSM8974_CNOC_SLV_SECURITY, 8, -1, 49); -DEFINE_QNODE(slv_tcsr, MSM8974_CNOC_SLV_TCSR, 8, -1, 50); -DEFINE_QNODE(slv_tlmm, MSM8974_CNOC_SLV_TLMM, 8, -1, 51); -DEFINE_QNODE(slv_crypto_0_cfg, MSM8974_CNOC_SLV_CRYPTO_0_CFG, 8, -1, 52); -DEFINE_QNODE(slv_crypto_1_cfg, MSM8974_CNOC_SLV_CRYPTO_1_CFG, 8, -1, 53); -DEFINE_QNODE(slv_imem_cfg, MSM8974_CNOC_SLV_IMEM_CFG, 8, -1, 54); -DEFINE_QNODE(slv_message_ram, MSM8974_CNOC_SLV_MESSAGE_RAM, 8, -1, 55); -DEFINE_QNODE(slv_bimc_cfg, MSM8974_CNOC_SLV_BIMC_CFG, 8, -1, 56); -DEFINE_QNODE(slv_boot_rom, MSM8974_CNOC_SLV_BOOT_ROM, 8, -1, 57); -DEFINE_QNODE(slv_pmic_arb, MSM8974_CNOC_SLV_PMIC_ARB, 8, -1, 59); -DEFINE_QNODE(slv_spdm_wrapper, MSM8974_CNOC_SLV_SPDM_WRAPPER, 8, -1, 60); -DEFINE_QNODE(slv_dehr_cfg, MSM8974_CNOC_SLV_DEHR_CFG, 8, -1, 61); -DEFINE_QNODE(slv_mpm, MSM8974_CNOC_SLV_MPM, 8, -1, 62); -DEFINE_QNODE(slv_qdss_cfg, MSM8974_CNOC_SLV_QDSS_CFG, 8, -1, 63); -DEFINE_QNODE(slv_rbcpr_cfg, MSM8974_CNOC_SLV_RBCPR_CFG, 8, -1, 64); -DEFINE_QNODE(slv_rbcpr_qdss_apu_cfg, MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, = 8, -1, 65); -DEFINE_QNODE(cnoc_to_snoc, MSM8974_CNOC_TO_SNOC, 8, 52, 75); -DEFINE_QNODE(slv_cnoc_onoc_cfg, MSM8974_CNOC_SLV_CNOC_ONOC_CFG, 8, -1, 68); -DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, = 8, -1, 58); -DEFINE_QNODE(slv_cnoc_mnoc_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_CFG, 8, -1, 66); -DEFINE_QNODE(slv_pnoc_cfg, MSM8974_CNOC_SLV_PNOC_CFG, 8, -1, 69); -DEFINE_QNODE(slv_snoc_mpu_cfg, MSM8974_CNOC_SLV_SNOC_MPU_CFG, 8, -1, 67); -DEFINE_QNODE(slv_snoc_cfg, MSM8974_CNOC_SLV_SNOC_CFG, 8, -1, 70); -DEFINE_QNODE(slv_ebi1_dll_cfg, MSM8974_CNOC_SLV_EBI1_DLL_CFG, 8, -1, 71); -DEFINE_QNODE(slv_phy_apu_cfg, MSM8974_CNOC_SLV_PHY_APU_CFG, 8, -1, 72); -DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PHY_CFG, 8, -1, 73); -DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74); -DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76); +static struct qcom_icc_node mas_rpm_inst =3D { + .name =3D "mas_rpm_inst", + .id =3D MSM8974_CNOC_MAS_RPM_INST, + .buswidth =3D 8, + .mas_rpm_id =3D 45, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_rpm_data =3D { + .name =3D "mas_rpm_data", + .id =3D MSM8974_CNOC_MAS_RPM_DATA, + .buswidth =3D 8, + .mas_rpm_id =3D 46, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_rpm_sys =3D { + .name =3D "mas_rpm_sys", + .id =3D MSM8974_CNOC_MAS_RPM_SYS, + .buswidth =3D 8, + .mas_rpm_id =3D 47, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_dehr =3D { + .name =3D "mas_dehr", + .id =3D MSM8974_CNOC_MAS_DEHR, + .buswidth =3D 8, + .mas_rpm_id =3D 48, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_qdss_dap =3D { + .name =3D "mas_qdss_dap", + .id =3D MSM8974_CNOC_MAS_QDSS_DAP, + .buswidth =3D 8, + .mas_rpm_id =3D 49, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_spdm =3D { + .name =3D "mas_spdm", + .id =3D MSM8974_CNOC_MAS_SPDM, + .buswidth =3D 8, + .mas_rpm_id =3D 50, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_tic =3D { + .name =3D "mas_tic", + .id =3D MSM8974_CNOC_MAS_TIC, + .buswidth =3D 8, + .mas_rpm_id =3D 51, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node slv_clk_ctl =3D { + .name =3D "slv_clk_ctl", + .id =3D MSM8974_CNOC_SLV_CLK_CTL, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 47, +}; + +static struct qcom_icc_node slv_cnoc_mss =3D { + .name =3D "slv_cnoc_mss", + .id =3D MSM8974_CNOC_SLV_CNOC_MSS, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 48, +}; + +static struct qcom_icc_node slv_security =3D { + .name =3D "slv_security", + .id =3D MSM8974_CNOC_SLV_SECURITY, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 49, +}; + +static struct qcom_icc_node slv_tcsr =3D { + .name =3D "slv_tcsr", + .id =3D MSM8974_CNOC_SLV_TCSR, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 50, +}; + +static struct qcom_icc_node slv_tlmm =3D { + .name =3D "slv_tlmm", + .id =3D MSM8974_CNOC_SLV_TLMM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 51, +}; + +static struct qcom_icc_node slv_crypto_0_cfg =3D { + .name =3D "slv_crypto_0_cfg", + .id =3D MSM8974_CNOC_SLV_CRYPTO_0_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 52, +}; + +static struct qcom_icc_node slv_crypto_1_cfg =3D { + .name =3D "slv_crypto_1_cfg", + .id =3D MSM8974_CNOC_SLV_CRYPTO_1_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 53, +}; + +static struct qcom_icc_node slv_imem_cfg =3D { + .name =3D "slv_imem_cfg", + .id =3D MSM8974_CNOC_SLV_IMEM_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 54, +}; + +static struct qcom_icc_node slv_message_ram =3D { + .name =3D "slv_message_ram", + .id =3D MSM8974_CNOC_SLV_MESSAGE_RAM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 55, +}; + +static struct qcom_icc_node slv_bimc_cfg =3D { + .name =3D "slv_bimc_cfg", + .id =3D MSM8974_CNOC_SLV_BIMC_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 56, +}; + +static struct qcom_icc_node slv_boot_rom =3D { + .name =3D "slv_boot_rom", + .id =3D MSM8974_CNOC_SLV_BOOT_ROM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 57, +}; + +static struct qcom_icc_node slv_pmic_arb =3D { + .name =3D "slv_pmic_arb", + .id =3D MSM8974_CNOC_SLV_PMIC_ARB, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 59, +}; + +static struct qcom_icc_node slv_spdm_wrapper =3D { + .name =3D "slv_spdm_wrapper", + .id =3D MSM8974_CNOC_SLV_SPDM_WRAPPER, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 60, +}; + +static struct qcom_icc_node slv_dehr_cfg =3D { + .name =3D "slv_dehr_cfg", + .id =3D MSM8974_CNOC_SLV_DEHR_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 61, +}; + +static struct qcom_icc_node slv_mpm =3D { + .name =3D "slv_mpm", + .id =3D MSM8974_CNOC_SLV_MPM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 62, +}; + +static struct qcom_icc_node slv_qdss_cfg =3D { + .name =3D "slv_qdss_cfg", + .id =3D MSM8974_CNOC_SLV_QDSS_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 63, +}; + +static struct qcom_icc_node slv_rbcpr_cfg =3D { + .name =3D "slv_rbcpr_cfg", + .id =3D MSM8974_CNOC_SLV_RBCPR_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 64, +}; + +static struct qcom_icc_node slv_rbcpr_qdss_apu_cfg =3D { + .name =3D "slv_rbcpr_qdss_apu_cfg", + .id =3D MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 65, +}; + +static struct qcom_icc_node cnoc_to_snoc =3D { + .name =3D "cnoc_to_snoc", + .id =3D MSM8974_CNOC_TO_SNOC, + .buswidth =3D 8, + .mas_rpm_id =3D 52, + .slv_rpm_id =3D 75, +}; + +static struct qcom_icc_node slv_cnoc_onoc_cfg =3D { + .name =3D "slv_cnoc_onoc_cfg", + .id =3D MSM8974_CNOC_SLV_CNOC_ONOC_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 68, +}; + +static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg =3D { + .name =3D "slv_cnoc_mnoc_mmss_cfg", + .id =3D MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 58, +}; + +static struct qcom_icc_node slv_cnoc_mnoc_cfg =3D { + .name =3D "slv_cnoc_mnoc_cfg", + .id =3D MSM8974_CNOC_SLV_CNOC_MNOC_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 66, +}; + +static struct qcom_icc_node slv_pnoc_cfg =3D { + .name =3D "slv_pnoc_cfg", + .id =3D MSM8974_CNOC_SLV_PNOC_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 69, +}; + +static struct qcom_icc_node slv_snoc_mpu_cfg =3D { + .name =3D "slv_snoc_mpu_cfg", + .id =3D MSM8974_CNOC_SLV_SNOC_MPU_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 67, +}; + +static struct qcom_icc_node slv_snoc_cfg =3D { + .name =3D "slv_snoc_cfg", + .id =3D MSM8974_CNOC_SLV_SNOC_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 70, +}; + +static struct qcom_icc_node slv_ebi1_dll_cfg =3D { + .name =3D "slv_ebi1_dll_cfg", + .id =3D MSM8974_CNOC_SLV_EBI1_DLL_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 71, +}; + +static struct qcom_icc_node slv_phy_apu_cfg =3D { + .name =3D "slv_phy_apu_cfg", + .id =3D MSM8974_CNOC_SLV_PHY_APU_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 72, +}; + +static struct qcom_icc_node slv_ebi1_phy_cfg =3D { + .name =3D "slv_ebi1_phy_cfg", + .id =3D MSM8974_CNOC_SLV_EBI1_PHY_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 73, +}; + +static struct qcom_icc_node slv_rpm =3D { + .name =3D "slv_rpm", + .id =3D MSM8974_CNOC_SLV_RPM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 74, +}; + +static struct qcom_icc_node slv_service_cnoc =3D { + .name =3D "slv_service_cnoc", + .id =3D MSM8974_CNOC_SLV_SERVICE_CNOC, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 76, +}; =20 static struct qcom_icc_node * const msm8974_cnoc_nodes[] =3D { [CNOC_MAS_RPM_INST] =3D &mas_rpm_inst, @@ -308,28 +613,211 @@ static const struct qcom_icc_desc msm8974_cnoc =3D { .ignore_enxio =3D true, }; =20 -DEFINE_QNODE(mas_graphics_3d, MSM8974_MNOC_MAS_GRAPHICS_3D, 16, 6, -1, MSM= 8974_MNOC_TO_BIMC); -DEFINE_QNODE(mas_jpeg, MSM8974_MNOC_MAS_JPEG, 16, 7, -1, MSM8974_MNOC_TO_B= IMC); -DEFINE_QNODE(mas_mdp_port0, MSM8974_MNOC_MAS_MDP_PORT0, 16, 8, -1, MSM8974= _MNOC_TO_BIMC); -DEFINE_QNODE(mas_video_p0, MSM8974_MNOC_MAS_VIDEO_P0, 16, 9, -1); -DEFINE_QNODE(mas_video_p1, MSM8974_MNOC_MAS_VIDEO_P1, 16, 10, -1); -DEFINE_QNODE(mas_vfe, MSM8974_MNOC_MAS_VFE, 16, 11, -1, MSM8974_MNOC_TO_BI= MC); -DEFINE_QNODE(mnoc_to_cnoc, MSM8974_MNOC_TO_CNOC, 16, 4, -1); -DEFINE_QNODE(mnoc_to_bimc, MSM8974_MNOC_TO_BIMC, 16, -1, 16, MSM8974_BIMC_= TO_MNOC); -DEFINE_QNODE(slv_camera_cfg, MSM8974_MNOC_SLV_CAMERA_CFG, 16, -1, 3); -DEFINE_QNODE(slv_display_cfg, MSM8974_MNOC_SLV_DISPLAY_CFG, 16, -1, 4); -DEFINE_QNODE(slv_ocmem_cfg, MSM8974_MNOC_SLV_OCMEM_CFG, 16, -1, 5); -DEFINE_QNODE(slv_cpr_cfg, MSM8974_MNOC_SLV_CPR_CFG, 16, -1, 6); -DEFINE_QNODE(slv_cpr_xpu_cfg, MSM8974_MNOC_SLV_CPR_XPU_CFG, 16, -1, 7); -DEFINE_QNODE(slv_misc_cfg, MSM8974_MNOC_SLV_MISC_CFG, 16, -1, 8); -DEFINE_QNODE(slv_misc_xpu_cfg, MSM8974_MNOC_SLV_MISC_XPU_CFG, 16, -1, 9); -DEFINE_QNODE(slv_venus_cfg, MSM8974_MNOC_SLV_VENUS_CFG, 16, -1, 10); -DEFINE_QNODE(slv_graphics_3d_cfg, MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, 16, -1= , 11); -DEFINE_QNODE(slv_mmss_clk_cfg, MSM8974_MNOC_SLV_MMSS_CLK_CFG, 16, -1, 12); -DEFINE_QNODE(slv_mmss_clk_xpu_cfg, MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, 16, = -1, 13); -DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MPU_CFG, 16, -1, 14); -DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15); -DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17); +static const u16 mas_graphics_3d_links[] =3D { + MSM8974_MNOC_TO_BIMC +}; + +static struct qcom_icc_node mas_graphics_3d =3D { + .name =3D "mas_graphics_3d", + .id =3D MSM8974_MNOC_MAS_GRAPHICS_3D, + .buswidth =3D 16, + .mas_rpm_id =3D 6, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_graphics_3d_links), + .links =3D mas_graphics_3d_links, +}; + +static const u16 mas_jpeg_links[] =3D { + MSM8974_MNOC_TO_BIMC +}; + +static struct qcom_icc_node mas_jpeg =3D { + .name =3D "mas_jpeg", + .id =3D MSM8974_MNOC_MAS_JPEG, + .buswidth =3D 16, + .mas_rpm_id =3D 7, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_jpeg_links), + .links =3D mas_jpeg_links, +}; + +static const u16 mas_mdp_port0_links[] =3D { + MSM8974_MNOC_TO_BIMC +}; + +static struct qcom_icc_node mas_mdp_port0 =3D { + .name =3D "mas_mdp_port0", + .id =3D MSM8974_MNOC_MAS_MDP_PORT0, + .buswidth =3D 16, + .mas_rpm_id =3D 8, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_mdp_port0_links), + .links =3D mas_mdp_port0_links, +}; + +static struct qcom_icc_node mas_video_p0 =3D { + .name =3D "mas_video_p0", + .id =3D MSM8974_MNOC_MAS_VIDEO_P0, + .buswidth =3D 16, + .mas_rpm_id =3D 9, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_video_p1 =3D { + .name =3D "mas_video_p1", + .id =3D MSM8974_MNOC_MAS_VIDEO_P1, + .buswidth =3D 16, + .mas_rpm_id =3D 10, + .slv_rpm_id =3D -1, +}; + +static const u16 mas_vfe_links[] =3D { + MSM8974_MNOC_TO_BIMC +}; + +static struct qcom_icc_node mas_vfe =3D { + .name =3D "mas_vfe", + .id =3D MSM8974_MNOC_MAS_VFE, + .buswidth =3D 16, + .mas_rpm_id =3D 11, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_vfe_links), + .links =3D mas_vfe_links, +}; + +static struct qcom_icc_node mnoc_to_cnoc =3D { + .name =3D "mnoc_to_cnoc", + .id =3D MSM8974_MNOC_TO_CNOC, + .buswidth =3D 16, + .mas_rpm_id =3D 4, + .slv_rpm_id =3D -1, +}; + +static const u16 mnoc_to_bimc_links[] =3D { + MSM8974_BIMC_TO_MNOC +}; + +static struct qcom_icc_node mnoc_to_bimc =3D { + .name =3D "mnoc_to_bimc", + .id =3D MSM8974_MNOC_TO_BIMC, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 16, + .num_links =3D ARRAY_SIZE(mnoc_to_bimc_links), + .links =3D mnoc_to_bimc_links, +}; + +static struct qcom_icc_node slv_camera_cfg =3D { + .name =3D "slv_camera_cfg", + .id =3D MSM8974_MNOC_SLV_CAMERA_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 3, +}; + +static struct qcom_icc_node slv_display_cfg =3D { + .name =3D "slv_display_cfg", + .id =3D MSM8974_MNOC_SLV_DISPLAY_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 4, +}; + +static struct qcom_icc_node slv_ocmem_cfg =3D { + .name =3D "slv_ocmem_cfg", + .id =3D MSM8974_MNOC_SLV_OCMEM_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 5, +}; + +static struct qcom_icc_node slv_cpr_cfg =3D { + .name =3D "slv_cpr_cfg", + .id =3D MSM8974_MNOC_SLV_CPR_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 6, +}; + +static struct qcom_icc_node slv_cpr_xpu_cfg =3D { + .name =3D "slv_cpr_xpu_cfg", + .id =3D MSM8974_MNOC_SLV_CPR_XPU_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 7, +}; + +static struct qcom_icc_node slv_misc_cfg =3D { + .name =3D "slv_misc_cfg", + .id =3D MSM8974_MNOC_SLV_MISC_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 8, +}; + +static struct qcom_icc_node slv_misc_xpu_cfg =3D { + .name =3D "slv_misc_xpu_cfg", + .id =3D MSM8974_MNOC_SLV_MISC_XPU_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 9, +}; + +static struct qcom_icc_node slv_venus_cfg =3D { + .name =3D "slv_venus_cfg", + .id =3D MSM8974_MNOC_SLV_VENUS_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 10, +}; + +static struct qcom_icc_node slv_graphics_3d_cfg =3D { + .name =3D "slv_graphics_3d_cfg", + .id =3D MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 11, +}; + +static struct qcom_icc_node slv_mmss_clk_cfg =3D { + .name =3D "slv_mmss_clk_cfg", + .id =3D MSM8974_MNOC_SLV_MMSS_CLK_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 12, +}; + +static struct qcom_icc_node slv_mmss_clk_xpu_cfg =3D { + .name =3D "slv_mmss_clk_xpu_cfg", + .id =3D MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 13, +}; + +static struct qcom_icc_node slv_mnoc_mpu_cfg =3D { + .name =3D "slv_mnoc_mpu_cfg", + .id =3D MSM8974_MNOC_SLV_MNOC_MPU_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 14, +}; + +static struct qcom_icc_node slv_onoc_mpu_cfg =3D { + .name =3D "slv_onoc_mpu_cfg", + .id =3D MSM8974_MNOC_SLV_ONOC_MPU_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 15, +}; + +static struct qcom_icc_node slv_service_mnoc =3D { + .name =3D "slv_service_mnoc", + .id =3D MSM8974_MNOC_SLV_SERVICE_MNOC, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 17, +}; =20 static struct qcom_icc_node * const msm8974_mnoc_nodes[] =3D { [MNOC_MAS_GRAPHICS_3D] =3D &mas_graphics_3d, @@ -363,20 +851,121 @@ static const struct qcom_icc_desc msm8974_mnoc =3D { .ignore_enxio =3D true, }; =20 -DEFINE_QNODE(ocmem_noc_to_ocmem_vnoc, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, 16,= 54, 78, MSM8974_OCMEM_SLV_OCMEM); -DEFINE_QNODE(mas_jpeg_ocmem, MSM8974_OCMEM_MAS_JPEG_OCMEM, 16, 13, -1); -DEFINE_QNODE(mas_mdp_ocmem, MSM8974_OCMEM_MAS_MDP_OCMEM, 16, 14, -1); -DEFINE_QNODE(mas_video_p0_ocmem, MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, 16, 15,= -1); -DEFINE_QNODE(mas_video_p1_ocmem, MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, 16, 16,= -1); -DEFINE_QNODE(mas_vfe_ocmem, MSM8974_OCMEM_MAS_VFE_OCMEM, 16, 17, -1); -DEFINE_QNODE(mas_cnoc_onoc_cfg, MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, 16, 12, -= 1); -DEFINE_QNODE(slv_service_onoc, MSM8974_OCMEM_SLV_SERVICE_ONOC, 16, -1, 19); -DEFINE_QNODE(slv_ocmem, MSM8974_OCMEM_SLV_OCMEM, 16, -1, 18); +static const u16 ocmem_noc_to_ocmem_vnoc_links[] =3D { + MSM8974_OCMEM_SLV_OCMEM +}; + +static struct qcom_icc_node ocmem_noc_to_ocmem_vnoc =3D { + .name =3D "ocmem_noc_to_ocmem_vnoc", + .id =3D MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, + .buswidth =3D 16, + .mas_rpm_id =3D 54, + .slv_rpm_id =3D 78, + .num_links =3D ARRAY_SIZE(ocmem_noc_to_ocmem_vnoc_links), + .links =3D ocmem_noc_to_ocmem_vnoc_links, +}; + +static struct qcom_icc_node mas_jpeg_ocmem =3D { + .name =3D "mas_jpeg_ocmem", + .id =3D MSM8974_OCMEM_MAS_JPEG_OCMEM, + .buswidth =3D 16, + .mas_rpm_id =3D 13, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_mdp_ocmem =3D { + .name =3D "mas_mdp_ocmem", + .id =3D MSM8974_OCMEM_MAS_MDP_OCMEM, + .buswidth =3D 16, + .mas_rpm_id =3D 14, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_video_p0_ocmem =3D { + .name =3D "mas_video_p0_ocmem", + .id =3D MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, + .buswidth =3D 16, + .mas_rpm_id =3D 15, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_video_p1_ocmem =3D { + .name =3D "mas_video_p1_ocmem", + .id =3D MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, + .buswidth =3D 16, + .mas_rpm_id =3D 16, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_vfe_ocmem =3D { + .name =3D "mas_vfe_ocmem", + .id =3D MSM8974_OCMEM_MAS_VFE_OCMEM, + .buswidth =3D 16, + .mas_rpm_id =3D 17, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_cnoc_onoc_cfg =3D { + .name =3D "mas_cnoc_onoc_cfg", + .id =3D MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, + .buswidth =3D 16, + .mas_rpm_id =3D 12, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node slv_service_onoc =3D { + .name =3D "slv_service_onoc", + .id =3D MSM8974_OCMEM_SLV_SERVICE_ONOC, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 19, +}; + +static struct qcom_icc_node slv_ocmem =3D { + .name =3D "slv_ocmem", + .id =3D MSM8974_OCMEM_SLV_OCMEM, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 18, +}; =20 /* Virtual NoC is needed for connection to OCMEM */ -DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 16, 56, = 79, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC); -DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80); -DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, M= SM8974_OCMEM_VNOC_TO_OCMEM_NOC); +static const u16 ocmem_vnoc_to_onoc_links[] =3D { + MSM8974_OCMEM_NOC_TO_OCMEM_VNOC +}; + +static struct qcom_icc_node ocmem_vnoc_to_onoc =3D { + .name =3D "ocmem_vnoc_to_onoc", + .id =3D MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, + .buswidth =3D 16, + .mas_rpm_id =3D 56, + .slv_rpm_id =3D 79, + .num_links =3D ARRAY_SIZE(ocmem_vnoc_to_onoc_links), + .links =3D ocmem_vnoc_to_onoc_links, +}; + +static struct qcom_icc_node ocmem_vnoc_to_snoc =3D { + .name =3D "ocmem_vnoc_to_snoc", + .id =3D MSM8974_OCMEM_VNOC_TO_SNOC, + .buswidth =3D 8, + .mas_rpm_id =3D 57, + .slv_rpm_id =3D 80, +}; + +static const u16 mas_v_ocmem_gfx3d_links[] =3D { + MSM8974_OCMEM_VNOC_TO_OCMEM_NOC +}; + +static struct qcom_icc_node mas_v_ocmem_gfx3d =3D { + .name =3D "mas_v_ocmem_gfx3d", + .id =3D MSM8974_OCMEM_VNOC_MAS_GFX3D, + .buswidth =3D 8, + .mas_rpm_id =3D 55, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_v_ocmem_gfx3d_links), + .links =3D mas_v_ocmem_gfx3d_links, +}; + =20 static struct qcom_icc_node * const msm8974_onoc_nodes[] =3D { [OCMEM_NOC_TO_OCMEM_VNOC] =3D &ocmem_noc_to_ocmem_vnoc, @@ -401,33 +990,288 @@ static const struct qcom_icc_desc msm8974_onoc =3D { .ignore_enxio =3D true, }; =20 -DEFINE_QNODE(mas_pnoc_cfg, MSM8974_PNOC_MAS_PNOC_CFG, 8, 43, -1); -DEFINE_QNODE(mas_sdcc_1, MSM8974_PNOC_MAS_SDCC_1, 8, 33, -1, MSM8974_PNOC_= TO_SNOC); -DEFINE_QNODE(mas_sdcc_3, MSM8974_PNOC_MAS_SDCC_3, 8, 34, -1, MSM8974_PNOC_= TO_SNOC); -DEFINE_QNODE(mas_sdcc_4, MSM8974_PNOC_MAS_SDCC_4, 8, 36, -1, MSM8974_PNOC_= TO_SNOC); -DEFINE_QNODE(mas_sdcc_2, MSM8974_PNOC_MAS_SDCC_2, 8, 35, -1, MSM8974_PNOC_= TO_SNOC); -DEFINE_QNODE(mas_tsif, MSM8974_PNOC_MAS_TSIF, 8, 37, -1, MSM8974_PNOC_TO_S= NOC); -DEFINE_QNODE(mas_bam_dma, MSM8974_PNOC_MAS_BAM_DMA, 8, 38, -1); -DEFINE_QNODE(mas_blsp_2, MSM8974_PNOC_MAS_BLSP_2, 8, 39, -1, MSM8974_PNOC_= TO_SNOC); -DEFINE_QNODE(mas_usb_hsic, MSM8974_PNOC_MAS_USB_HSIC, 8, 40, -1, MSM8974_P= NOC_TO_SNOC); -DEFINE_QNODE(mas_blsp_1, MSM8974_PNOC_MAS_BLSP_1, 8, 41, -1, MSM8974_PNOC_= TO_SNOC); -DEFINE_QNODE(mas_usb_hs, MSM8974_PNOC_MAS_USB_HS, 8, 42, -1, MSM8974_PNOC_= TO_SNOC); -DEFINE_QNODE(pnoc_to_snoc, MSM8974_PNOC_TO_SNOC, 8, 44, 45, MSM8974_SNOC_T= O_PNOC, MSM8974_PNOC_SLV_PRNG); -DEFINE_QNODE(slv_sdcc_1, MSM8974_PNOC_SLV_SDCC_1, 8, -1, 31); -DEFINE_QNODE(slv_sdcc_3, MSM8974_PNOC_SLV_SDCC_3, 8, -1, 32); -DEFINE_QNODE(slv_sdcc_2, MSM8974_PNOC_SLV_SDCC_2, 8, -1, 33); -DEFINE_QNODE(slv_sdcc_4, MSM8974_PNOC_SLV_SDCC_4, 8, -1, 34); -DEFINE_QNODE(slv_tsif, MSM8974_PNOC_SLV_TSIF, 8, -1, 35); -DEFINE_QNODE(slv_bam_dma, MSM8974_PNOC_SLV_BAM_DMA, 8, -1, 36); -DEFINE_QNODE(slv_blsp_2, MSM8974_PNOC_SLV_BLSP_2, 8, -1, 37); -DEFINE_QNODE(slv_usb_hsic, MSM8974_PNOC_SLV_USB_HSIC, 8, -1, 38); -DEFINE_QNODE(slv_blsp_1, MSM8974_PNOC_SLV_BLSP_1, 8, -1, 39); -DEFINE_QNODE(slv_usb_hs, MSM8974_PNOC_SLV_USB_HS, 8, -1, 40); -DEFINE_QNODE(slv_pdm, MSM8974_PNOC_SLV_PDM, 8, -1, 41); -DEFINE_QNODE(slv_periph_apu_cfg, MSM8974_PNOC_SLV_PERIPH_APU_CFG, 8, -1, 4= 2); -DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MPU_CFG, 8, -1, 43); -DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_S= NOC); -DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46); +static struct qcom_icc_node mas_pnoc_cfg =3D { + .name =3D "mas_pnoc_cfg", + .id =3D MSM8974_PNOC_MAS_PNOC_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D 43, + .slv_rpm_id =3D -1, +}; + +static const u16 mas_sdcc_1_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node mas_sdcc_1 =3D { + .name =3D "mas_sdcc_1", + .id =3D MSM8974_PNOC_MAS_SDCC_1, + .buswidth =3D 8, + .mas_rpm_id =3D 33, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_sdcc_1_links), + .links =3D mas_sdcc_1_links, +}; + +static const u16 mas_sdcc_3_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node mas_sdcc_3 =3D { + .name =3D "mas_sdcc_3", + .id =3D MSM8974_PNOC_MAS_SDCC_3, + .buswidth =3D 8, + .mas_rpm_id =3D 34, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_sdcc_3_links), + .links =3D mas_sdcc_3_links, +}; + +static const u16 mas_sdcc_4_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node mas_sdcc_4 =3D { + .name =3D "mas_sdcc_4", + .id =3D MSM8974_PNOC_MAS_SDCC_4, + .buswidth =3D 8, + .mas_rpm_id =3D 36, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_sdcc_4_links), + .links =3D mas_sdcc_4_links, +}; + +static const u16 mas_sdcc_2_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node mas_sdcc_2 =3D { + .name =3D "mas_sdcc_2", + .id =3D MSM8974_PNOC_MAS_SDCC_2, + .buswidth =3D 8, + .mas_rpm_id =3D 35, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_sdcc_2_links), + .links =3D mas_sdcc_2_links, +}; + +static const u16 mas_tsif_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node mas_tsif =3D { + .name =3D "mas_tsif", + .id =3D MSM8974_PNOC_MAS_TSIF, + .buswidth =3D 8, + .mas_rpm_id =3D 37, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_tsif_links), + .links =3D mas_tsif_links, +}; + +static struct qcom_icc_node mas_bam_dma =3D { + .name =3D "mas_bam_dma", + .id =3D MSM8974_PNOC_MAS_BAM_DMA, + .buswidth =3D 8, + .mas_rpm_id =3D 38, + .slv_rpm_id =3D -1, +}; + +static const u16 mas_blsp_2_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node mas_blsp_2 =3D { + .name =3D "mas_blsp_2", + .id =3D MSM8974_PNOC_MAS_BLSP_2, + .buswidth =3D 8, + .mas_rpm_id =3D 39, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_blsp_2_links), + .links =3D mas_blsp_2_links, +}; + +static const u16 mas_usb_hsic_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node mas_usb_hsic =3D { + .name =3D "mas_usb_hsic", + .id =3D MSM8974_PNOC_MAS_USB_HSIC, + .buswidth =3D 8, + .mas_rpm_id =3D 40, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_usb_hsic_links), + .links =3D mas_usb_hsic_links, +}; + +static const u16 mas_blsp_1_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node mas_blsp_1 =3D { + .name =3D "mas_blsp_1", + .id =3D MSM8974_PNOC_MAS_BLSP_1, + .buswidth =3D 8, + .mas_rpm_id =3D 41, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_blsp_1_links), + .links =3D mas_blsp_1_links, +}; + +static const u16 mas_usb_hs_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node mas_usb_hs =3D { + .name =3D "mas_usb_hs", + .id =3D MSM8974_PNOC_MAS_USB_HS, + .buswidth =3D 8, + .mas_rpm_id =3D 42, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_usb_hs_links), + .links =3D mas_usb_hs_links, +}; + +static const u16 pnoc_to_snoc_links[] =3D { + MSM8974_SNOC_TO_PNOC, + MSM8974_PNOC_SLV_PRNG +}; + +static struct qcom_icc_node pnoc_to_snoc =3D { + .name =3D "pnoc_to_snoc", + .id =3D MSM8974_PNOC_TO_SNOC, + .buswidth =3D 8, + .mas_rpm_id =3D 44, + .slv_rpm_id =3D 45, + .num_links =3D ARRAY_SIZE(pnoc_to_snoc_links), + .links =3D pnoc_to_snoc_links, +}; + +static struct qcom_icc_node slv_sdcc_1 =3D { + .name =3D "slv_sdcc_1", + .id =3D MSM8974_PNOC_SLV_SDCC_1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 31, +}; + +static struct qcom_icc_node slv_sdcc_3 =3D { + .name =3D "slv_sdcc_3", + .id =3D MSM8974_PNOC_SLV_SDCC_3, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 32, +}; + +static struct qcom_icc_node slv_sdcc_2 =3D { + .name =3D "slv_sdcc_2", + .id =3D MSM8974_PNOC_SLV_SDCC_2, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 33, +}; + +static struct qcom_icc_node slv_sdcc_4 =3D { + .name =3D "slv_sdcc_4", + .id =3D MSM8974_PNOC_SLV_SDCC_4, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 34, +}; + +static struct qcom_icc_node slv_tsif =3D { + .name =3D "slv_tsif", + .id =3D MSM8974_PNOC_SLV_TSIF, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 35, +}; + +static struct qcom_icc_node slv_bam_dma =3D { + .name =3D "slv_bam_dma", + .id =3D MSM8974_PNOC_SLV_BAM_DMA, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 36, +}; + +static struct qcom_icc_node slv_blsp_2 =3D { + .name =3D "slv_blsp_2", + .id =3D MSM8974_PNOC_SLV_BLSP_2, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 37, +}; + +static struct qcom_icc_node slv_usb_hsic =3D { + .name =3D "slv_usb_hsic", + .id =3D MSM8974_PNOC_SLV_USB_HSIC, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 38, +}; + +static struct qcom_icc_node slv_blsp_1 =3D { + .name =3D "slv_blsp_1", + .id =3D MSM8974_PNOC_SLV_BLSP_1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 39, +}; + +static struct qcom_icc_node slv_usb_hs =3D { + .name =3D "slv_usb_hs", + .id =3D MSM8974_PNOC_SLV_USB_HS, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 40, +}; + +static struct qcom_icc_node slv_pdm =3D { + .name =3D "slv_pdm", + .id =3D MSM8974_PNOC_SLV_PDM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 41, +}; + +static struct qcom_icc_node slv_periph_apu_cfg =3D { + .name =3D "slv_periph_apu_cfg", + .id =3D MSM8974_PNOC_SLV_PERIPH_APU_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 42, +}; + +static struct qcom_icc_node slv_pnoc_mpu_cfg =3D { + .name =3D "slv_pnoc_mpu_cfg", + .id =3D MSM8974_PNOC_SLV_PNOC_MPU_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 43, +}; + +static const u16 slv_prng_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node slv_prng =3D { + .name =3D "slv_prng", + .id =3D MSM8974_PNOC_SLV_PRNG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 44, + .num_links =3D ARRAY_SIZE(slv_prng_links), + .links =3D slv_prng_links, +}; + +static struct qcom_icc_node slv_service_pnoc =3D { + .name =3D "slv_service_pnoc", + .id =3D MSM8974_PNOC_SLV_SERVICE_PNOC, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 46, +}; =20 static struct qcom_icc_node * const msm8974_pnoc_nodes[] =3D { [PNOC_MAS_PNOC_CFG] =3D &mas_pnoc_cfg, @@ -468,30 +1312,233 @@ static const struct qcom_icc_desc msm8974_pnoc =3D { .ignore_enxio =3D true, }; =20 -DEFINE_QNODE(mas_lpass_ahb, MSM8974_SNOC_MAS_LPASS_AHB, 8, 18, -1); -DEFINE_QNODE(mas_qdss_bam, MSM8974_SNOC_MAS_QDSS_BAM, 8, 19, -1); -DEFINE_QNODE(mas_snoc_cfg, MSM8974_SNOC_MAS_SNOC_CFG, 8, 20, -1); -DEFINE_QNODE(snoc_to_bimc, MSM8974_SNOC_TO_BIMC, 8, 21, 24, MSM8974_BIMC_T= O_SNOC); -DEFINE_QNODE(snoc_to_cnoc, MSM8974_SNOC_TO_CNOC, 8, 22, 25); -DEFINE_QNODE(snoc_to_pnoc, MSM8974_SNOC_TO_PNOC, 8, 29, 28, MSM8974_PNOC_T= O_SNOC); -DEFINE_QNODE(snoc_to_ocmem_vnoc, MSM8974_SNOC_TO_OCMEM_VNOC, 8, 53, 77, MS= M8974_OCMEM_VNOC_TO_OCMEM_NOC); -DEFINE_QNODE(mas_crypto_core0, MSM8974_SNOC_MAS_CRYPTO_CORE0, 8, 23, -1, M= SM8974_SNOC_TO_BIMC); -DEFINE_QNODE(mas_crypto_core1, MSM8974_SNOC_MAS_CRYPTO_CORE1, 8, 24, -1); -DEFINE_QNODE(mas_lpass_proc, MSM8974_SNOC_MAS_LPASS_PROC, 8, 25, -1, MSM89= 74_SNOC_TO_OCMEM_VNOC); -DEFINE_QNODE(mas_mss, MSM8974_SNOC_MAS_MSS, 8, 26, -1); -DEFINE_QNODE(mas_mss_nav, MSM8974_SNOC_MAS_MSS_NAV, 8, 27, -1); -DEFINE_QNODE(mas_ocmem_dma, MSM8974_SNOC_MAS_OCMEM_DMA, 8, 28, -1); -DEFINE_QNODE(mas_wcss, MSM8974_SNOC_MAS_WCSS, 8, 30, -1); -DEFINE_QNODE(mas_qdss_etr, MSM8974_SNOC_MAS_QDSS_ETR, 8, 31, -1); -DEFINE_QNODE(mas_usb3, MSM8974_SNOC_MAS_USB3, 8, 32, -1, MSM8974_SNOC_TO_B= IMC); -DEFINE_QNODE(slv_ampss, MSM8974_SNOC_SLV_AMPSS, 8, -1, 20); -DEFINE_QNODE(slv_lpass, MSM8974_SNOC_SLV_LPASS, 8, -1, 21); -DEFINE_QNODE(slv_usb3, MSM8974_SNOC_SLV_USB3, 8, -1, 22); -DEFINE_QNODE(slv_wcss, MSM8974_SNOC_SLV_WCSS, 8, -1, 23); -DEFINE_QNODE(slv_ocimem, MSM8974_SNOC_SLV_OCIMEM, 8, -1, 26); -DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCMEM, 8, -1, 27); -DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29); -DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30); +static struct qcom_icc_node mas_lpass_ahb =3D { + .name =3D "mas_lpass_ahb", + .id =3D MSM8974_SNOC_MAS_LPASS_AHB, + .buswidth =3D 8, + .mas_rpm_id =3D 18, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_qdss_bam =3D { + .name =3D "mas_qdss_bam", + .id =3D MSM8974_SNOC_MAS_QDSS_BAM, + .buswidth =3D 8, + .mas_rpm_id =3D 19, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_snoc_cfg =3D { + .name =3D "mas_snoc_cfg", + .id =3D MSM8974_SNOC_MAS_SNOC_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D 20, + .slv_rpm_id =3D -1, +}; + +static const u16 snoc_to_bimc_links[] =3D { + MSM8974_BIMC_TO_SNOC +}; + +static struct qcom_icc_node snoc_to_bimc =3D { + .name =3D "snoc_to_bimc", + .id =3D MSM8974_SNOC_TO_BIMC, + .buswidth =3D 8, + .mas_rpm_id =3D 21, + .slv_rpm_id =3D 24, + .num_links =3D ARRAY_SIZE(snoc_to_bimc_links), + .links =3D snoc_to_bimc_links, +}; + +static struct qcom_icc_node snoc_to_cnoc =3D { + .name =3D "snoc_to_cnoc", + .id =3D MSM8974_SNOC_TO_CNOC, + .buswidth =3D 8, + .mas_rpm_id =3D 22, + .slv_rpm_id =3D 25, +}; + +static const u16 snoc_to_pnoc_links[] =3D { + MSM8974_PNOC_TO_SNOC +}; + +static struct qcom_icc_node snoc_to_pnoc =3D { + .name =3D "snoc_to_pnoc", + .id =3D MSM8974_SNOC_TO_PNOC, + .buswidth =3D 8, + .mas_rpm_id =3D 29, + .slv_rpm_id =3D 28, + .num_links =3D ARRAY_SIZE(snoc_to_pnoc_links), + .links =3D snoc_to_pnoc_links, +}; + +static const u16 snoc_to_ocmem_vnoc_links[] =3D { + MSM8974_OCMEM_VNOC_TO_OCMEM_NOC +}; + +static struct qcom_icc_node snoc_to_ocmem_vnoc =3D { + .name =3D "snoc_to_ocmem_vnoc", + .id =3D MSM8974_SNOC_TO_OCMEM_VNOC, + .buswidth =3D 8, + .mas_rpm_id =3D 53, + .slv_rpm_id =3D 77, + .num_links =3D ARRAY_SIZE(snoc_to_ocmem_vnoc_links), + .links =3D snoc_to_ocmem_vnoc_links, +}; + +static const u16 mas_crypto_core0_links[] =3D { + MSM8974_SNOC_TO_BIMC +}; + +static struct qcom_icc_node mas_crypto_core0 =3D { + .name =3D "mas_crypto_core0", + .id =3D MSM8974_SNOC_MAS_CRYPTO_CORE0, + .buswidth =3D 8, + .mas_rpm_id =3D 23, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_crypto_core0_links), + .links =3D mas_crypto_core0_links, +}; + +static struct qcom_icc_node mas_crypto_core1 =3D { + .name =3D "mas_crypto_core1", + .id =3D MSM8974_SNOC_MAS_CRYPTO_CORE1, + .buswidth =3D 8, + .mas_rpm_id =3D 24, + .slv_rpm_id =3D -1, +}; + +static const u16 mas_lpass_proc_links[] =3D { + MSM8974_SNOC_TO_OCMEM_VNOC +}; + +static struct qcom_icc_node mas_lpass_proc =3D { + .name =3D "mas_lpass_proc", + .id =3D MSM8974_SNOC_MAS_LPASS_PROC, + .buswidth =3D 8, + .mas_rpm_id =3D 25, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_lpass_proc_links), + .links =3D mas_lpass_proc_links, +}; + +static struct qcom_icc_node mas_mss =3D { + .name =3D "mas_mss", + .id =3D MSM8974_SNOC_MAS_MSS, + .buswidth =3D 8, + .mas_rpm_id =3D 26, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_mss_nav =3D { + .name =3D "mas_mss_nav", + .id =3D MSM8974_SNOC_MAS_MSS_NAV, + .buswidth =3D 8, + .mas_rpm_id =3D 27, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_ocmem_dma =3D { + .name =3D "mas_ocmem_dma", + .id =3D MSM8974_SNOC_MAS_OCMEM_DMA, + .buswidth =3D 8, + .mas_rpm_id =3D 28, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_wcss =3D { + .name =3D "mas_wcss", + .id =3D MSM8974_SNOC_MAS_WCSS, + .buswidth =3D 8, + .mas_rpm_id =3D 30, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node mas_qdss_etr =3D { + .name =3D "mas_qdss_etr", + .id =3D MSM8974_SNOC_MAS_QDSS_ETR, + .buswidth =3D 8, + .mas_rpm_id =3D 31, + .slv_rpm_id =3D -1, +}; + +static const u16 mas_usb3_links[] =3D { + MSM8974_SNOC_TO_BIMC +}; + +static struct qcom_icc_node mas_usb3 =3D { + .name =3D "mas_usb3", + .id =3D MSM8974_SNOC_MAS_USB3, + .buswidth =3D 8, + .mas_rpm_id =3D 32, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_usb3_links), + .links =3D mas_usb3_links, +}; + +static struct qcom_icc_node slv_ampss =3D { + .name =3D "slv_ampss", + .id =3D MSM8974_SNOC_SLV_AMPSS, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 20, +}; + +static struct qcom_icc_node slv_lpass =3D { + .name =3D "slv_lpass", + .id =3D MSM8974_SNOC_SLV_LPASS, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 21, +}; + +static struct qcom_icc_node slv_usb3 =3D { + .name =3D "slv_usb3", + .id =3D MSM8974_SNOC_SLV_USB3, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 22, +}; + +static struct qcom_icc_node slv_wcss =3D { + .name =3D "slv_wcss", + .id =3D MSM8974_SNOC_SLV_WCSS, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 23, +}; + +static struct qcom_icc_node slv_ocimem =3D { + .name =3D "slv_ocimem", + .id =3D MSM8974_SNOC_SLV_OCIMEM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 26, +}; + +static struct qcom_icc_node slv_snoc_ocmem =3D { + .name =3D "slv_snoc_ocmem", + .id =3D MSM8974_SNOC_SLV_SNOC_OCMEM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 27, +}; + +static struct qcom_icc_node slv_service_snoc =3D { + .name =3D "slv_service_snoc", + .id =3D MSM8974_SNOC_SLV_SERVICE_SNOC, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 29, +}; + +static struct qcom_icc_node slv_qdss_stm =3D { + .name =3D "slv_qdss_stm", + .id =3D MSM8974_SNOC_SLV_QDSS_STM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 30, +}; =20 static struct qcom_icc_node * const msm8974_snoc_nodes[] =3D { [SNOC_MAS_LPASS_AHB] =3D &mas_lpass_ahb, --=20 2.47.3 From nobody Fri Apr 3 22:13:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F20721A447 for ; Mon, 23 Mar 2026 01:17:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228679; cv=none; b=jbzzafBn9a3g9lBRQI7gM0zRbBloxkEo9VlWtVBfkCZsx92LT2uwU08gsOMCFYP23WX41R1D4q7aJTAnaC5b+ukvN5prfqaTx8QpmPHjlVC4Gb0jUjrZL8FJW34zq4n3tvfkXRDu0gd3cGUNwWYea+IvqBQZUnCFmLoh8VKRdQ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774228679; c=relaxed/simple; bh=+S0IFBZw92HGwmKPKSp5T6BC3eDkzODFf2LEmOeC4hU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=acSq6ctH3V5EqEl/h53L6TYsm40ceiubgQmjqrHseSe5d9Xun/LcaL2xcX3Wboa7VNe2CRSqTW+p2dCH8vOk7tSQrsuVIie2c/LPhvlAFDE/Phe5PRE6bLnQk5fbKZC1QxgwGT/lrRhkcvQzeL5QT9hZlTWaL62fVIrwfwUq8gk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=InkhzLxd; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=AvgTEbCP; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="InkhzLxd"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="AvgTEbCP" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62M9DZ9J416066 for ; Mon, 23 Mar 2026 01:17:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= PQ0yY7wANsCbi+N0sJM1csjMHIR4oyLtsNwiNzciyC4=; b=InkhzLxdNrtVKwKD QrrIbsE6dS+ZW7n15JUFXCT7rEEGgO3uMYAMADkAGGl1bCh/xk6JDnlKg+2oO6fo Yd/hriA/t2zhwvQ84sclpaNXhVJfR6IC3LTQ30F+RJGDezEPD5PY6ir8+qw73g/e WZxIFsAJV0O4Z/skjPQbUEI3HebaKw6Ai5jrhp0l0R20YzaS3Kb2GLnGXurieZPb NlDmXPccnUQ8rIY/tZCAW8U5WoIy5fmL7jgLvvgkrN2Q/5GvHjgpIhHFetMQydxL BegyZ38+kooNQupfHYkMOoCDsnPR1ViO2XNJOMZkSzaJLuLtrZJaMJ4mh5LpIec6 cTs8ew== Received: from mail-qt1-f197.google.com (mail-qt1-f197.google.com [209.85.160.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d1kdub8ng-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 23 Mar 2026 01:17:56 +0000 (GMT) Received: by mail-qt1-f197.google.com with SMTP id d75a77b69052e-50b34223670so57105971cf.0 for ; Sun, 22 Mar 2026 18:17:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774228676; x=1774833476; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PQ0yY7wANsCbi+N0sJM1csjMHIR4oyLtsNwiNzciyC4=; b=AvgTEbCPtw66V1+yr2TPDV9ONCNXr0UKPAE61iN2nKqAODZQhBNxqVCk1Uwq134nxW FL0aGF6VhkUo6Q7ofAPi4wLpnr4YIM76zEpRuoIE8nLY7kk+7UJgQLNXzxV9Yx7UGgl1 9tNeOU0LUf7BZXSyk2XhLf1Z6Ja2MgaXOy3uQu2aTv3CpoO+HgAWTNsAN7ax/yWHCzDI SFF0co2F1bSypF9WYpRs8BauwShhc+47IrH+8PMA/dLbPfnJtV78C4jkTquvr/MXAsK6 PPxmPEr1N0/dtnwT6oFCUaJCIR+DN2nnMuQ5hRopGwbxrnaf10Fmt1fw+JpoOZWWecWE G0aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774228676; x=1774833476; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=PQ0yY7wANsCbi+N0sJM1csjMHIR4oyLtsNwiNzciyC4=; b=RkKhhAg4C9NwvQpjetU63pxdOYYO/ntU+L86H2m3KgbAZ+xkmECShFh4NA0XycuRcf Wvaxc5y6ds3+8VqbP3F0DkyjqN4gPcQXOsnbcMcYfZXtV5D3+VoYNNjyhOee7SeKtZ/H ykNHbh6xQ3fJJZOBktua5SxJI77t+yu7qz7pbzB21HP6rFXakUxFZvSMrxkfYuegGQEP paJ/PeTknj24k7QxGvY0A5RgdvP/R/TyjX8uN6p76rPB7mJMJ4of7h16d/CcHTF6XUwE VgdJKUuUphuXuXnG3cFeMwDbQDaQ4GvmP5YvFjkwg63W+UVUXU3bYnVaKQeCM95TG29V 1vSw== X-Forwarded-Encrypted: i=1; AJvYcCXiGzS3kvGbY9UNaPGBrVOm8xFd7kFsuM6W+PldCfmuA9y6Aw/DPRgzOrEkFDfQRMtM8WZ7Q6Fty2mE01k=@vger.kernel.org X-Gm-Message-State: AOJu0Ywy36nF1L0xXfcbbAdJ+k88rNd98N1gNKfOVgbxlwI4WWJN0Aqa fscBvU+XAwDffdU4r8i33cqaJce4cgtEmwWb2MMn5pCiKBJNgauVvzDQqttrxIhO6Sgok5X2Vtk V5J/P1Bjone7Ici6+rpptgWN5F3o1OwLgsOEtZ9TZqaJx+R1Ibm3KF11LZOOSDegPr/A= X-Gm-Gg: ATEYQzyWyk6Ra+lh9Zk1c455l8se9DoZEJQEK5iio03nstVLj7SNh2d+uvM86CDTKI9 VM7cfid887ib6KB6Lan44v+hPJqoh/oTUSIG3BVFcEeZrHyDDY40WMQJ4ojAsyQ6z6dfYCB1vRw Pp5JO0gtwYJ0swYp3U1SE31iBnA+46Sun1WjSnhAZF6CkokDY8No+8WYyQ+h0fhphVAYRu2UKch UknMMdAq3QB7ovVejMSqdlkQsowYh7BLLVsGqtrWijEZxnsuEb1D1ZuP0n1yua8Gf2HQPGtowIi QCtnm+4KGLx4z+eUonZkOAJ5/IP0T1FQ3DBDnqIdrZeJX0JONeZGFBh5OA+boYGUSJkfV/BEIbq YR1RWOPU32YueU87bdTTCZHALMQ4Cefp3VnqUa+Dh8TxGQSd4zAWlSjpOq4K5PW3GAcaWG0kOQp Rv4DWS8c87sTXJKtG8dlpZE5VR67+pXq+JlcY= X-Received: by 2002:a05:622a:1391:b0:50b:1e5d:9930 with SMTP id d75a77b69052e-50b375a89acmr163336861cf.58.1774228675829; Sun, 22 Mar 2026 18:17:55 -0700 (PDT) X-Received: by 2002:a05:622a:1391:b0:50b:1e5d:9930 with SMTP id d75a77b69052e-50b375a89acmr163336671cf.58.1774228675331; Sun, 22 Mar 2026 18:17:55 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a2853050e7sm2216150e87.61.2026.03.22.18.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 18:17:52 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 23 Mar 2026 03:17:25 +0200 Subject: [PATCH 9/9] ARM: dts: qcom: msm8974: Drop RPM bus clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-msm8974-icc-v1-9-7892b8d5f2ea@oss.qualcomm.com> References: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> In-Reply-To: <20260323-msm8974-icc-v1-0-7892b8d5f2ea@oss.qualcomm.com> To: Georgi Djakov , Konrad Dybcio , Bjorn Andersson , Luca Weiss , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2873; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=+S0IFBZw92HGwmKPKSp5T6BC3eDkzODFf2LEmOeC4hU=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ+aBKfMbLu84rLVA3DW2ssnV4f20E9NUJgi/V3rY/T8or aBqUqZnJ6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAmol7P/odfoY+pRSO+LG9b Wt1OTWGzk52alZFmuz6my/Ymp9z/nfj+kdurHfEtAfc8PXJlYp42i6YrKOWd37GvStRNSfqyYqr VT+uDLnL/nBYdZ4q/dFvarfAI06uXKQUZU001Qj+2eUzpWPgh6/eTFz+X/m7ySq7NdJ1jM9nk7N Yf+7LNP/QsEN+uZLhN61SV+VH2pUuFbqyP3f3iXIqej5hWnMdcryOC928YR+enNByetK/iwJwwx gtKRwJ5OexzimR/NHb7C3Qta236XdP2h3XSsSaf3nRHHdf//28Kdj5t+LyPp1wwdvVMq2nnLfmO 3Q/SL0xsfePnI2z+q/hL8jEfpk/JP25nRR/JVlo/9+kDAA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDAwOCBTYWx0ZWRfX0d+jVQjjHqbJ UDIbGQ96itRyJ8FZS697HPcIXCJYewwjW17dR261kUCv6KTqIug6ry3M7fA6FVAmg9KygGKqFjE acjovfQF6lmoCobMRv2WTE4v+WAk+/vARwwNBcVHOMphXpXQMQQe7WpnXfrLJo9zv2UjIZHD8Ir bdcaeWHygqGZSW8feUQavw88wMcWXcE3ezW29NvBfFz6E4h0nt2Q7Mv2yuAJ4OqKdvmO14WHSY3 42foXn8H4QFlobFTZx9XYo1Zs2K3UmdUM+T4vifU2dnTE0a5Via7IzRgh52WqsLeGRE9WZ1Uaw+ miS7hasxjEfnZhD2KSQQtjA10ltMVBQyun1QhT4ky75woS3LxJ8QH8DMCF5Lou36jdqQGkg5lAX rOOYIX6pLmV5Vi9DYON8za8sO5B68kw/HcGWJTutS5A5lEZx06JFAlW6x8a2GnhZ7OUlCnPMwiD 2+8Vdv5WB6rvEo3Hq6w== X-Proofpoint-ORIG-GUID: bQs2GFZS4rtwyfqZYGvJrKjfblHFHHGy X-Authority-Analysis: v=2.4 cv=Q4DfIo2a c=1 sm=1 tr=0 ts=69c094c4 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=h6rqPeke2OkJn0bzelEA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: bQs2GFZS4rtwyfqZYGvJrKjfblHFHHGy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-22_07,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230008 Some nodes are abusingly referencing some of the internal bus clocks, that were recently removed in Linux (because the original implementation did not make much sense), managing them as if they were the only devices on an NoC bus. These clocks are now handled from within the icc framework and are no longer registered from within the CCF. Remove them. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8974.dtsi index 2a82ddce94a2..7060de4fa551 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -1115,9 +1115,6 @@ bimc: interconnect@fc380000 { reg =3D <0xfc380000 0x6a000>; compatible =3D "qcom,msm8974-bimc"; #interconnect-cells =3D <1>; - clock-names =3D "bus", "bus_a"; - clocks =3D <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; }; =20 gcc: clock-controller@fc400000 { @@ -1162,45 +1159,32 @@ snoc: interconnect@fc460000 { reg =3D <0xfc460000 0x4000>; compatible =3D "qcom,msm8974-snoc"; #interconnect-cells =3D <1>; - clock-names =3D "bus", "bus_a"; - clocks =3D <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; }; =20 pnoc: interconnect@fc468000 { reg =3D <0xfc468000 0x4000>; compatible =3D "qcom,msm8974-pnoc"; #interconnect-cells =3D <1>; - clock-names =3D "bus", "bus_a"; - clocks =3D <&rpmcc RPM_SMD_PNOC_CLK>, - <&rpmcc RPM_SMD_PNOC_A_CLK>; }; =20 ocmemnoc: interconnect@fc470000 { reg =3D <0xfc470000 0x4000>; compatible =3D "qcom,msm8974-ocmemnoc"; #interconnect-cells =3D <1>; - clock-names =3D "bus", "bus_a"; - clocks =3D <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; }; =20 mmssnoc: interconnect@fc478000 { reg =3D <0xfc478000 0x4000>; compatible =3D "qcom,msm8974-mmssnoc"; #interconnect-cells =3D <1>; - clock-names =3D "bus", "bus_a"; - clocks =3D <&mmcc MMSS_S0_AXI_CLK>, - <&mmcc MMSS_S0_AXI_CLK>; + clock-names =3D "bus"; + clocks =3D <&mmcc MMSS_S0_AXI_CLK>; }; =20 cnoc: interconnect@fc480000 { reg =3D <0xfc480000 0x4000>; compatible =3D "qcom,msm8974-cnoc"; #interconnect-cells =3D <1>; - clock-names =3D "bus", "bus_a"; - clocks =3D <&rpmcc RPM_SMD_CNOC_CLK>, - <&rpmcc RPM_SMD_CNOC_A_CLK>; }; =20 tsens: thermal-sensor@fc4a9000 { @@ -2223,6 +2207,7 @@ sram@fdd00000 { <0xfec00000 0x180000>; reg-names =3D "ctrl", "mem"; ranges =3D <0 0xfec00000 0x180000>; + // core clock is unused, kept for ABI compliance clocks =3D <&rpmcc RPM_SMD_OCMEMGX_CLK>, <&mmcc OCMEMCX_OCMEMNOC_CLK>; clock-names =3D "core", "iface"; --=20 2.47.3