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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c10b14cadbsm13997886eec.3.2026.03.23.00.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 00:15:37 -0700 (PDT) From: Qiang Yu Date: Mon, 23 Mar 2026 00:15:31 -0700 Subject: [PATCH v2 4/5] phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-glymur_gen5x8_phy_0323-v2-4-ce0fc07f0e52@oss.qualcomm.com> References: <20260323-glymur_gen5x8_phy_0323-v2-0-ce0fc07f0e52@oss.qualcomm.com> In-Reply-To: <20260323-glymur_gen5x8_phy_0323-v2-0-ce0fc07f0e52@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774250130; l=2780; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=ZiGLm9+oSWgzXrpOJ1svwFM4yASEfqBDxFjXKTyaJxM=; b=PcRacB6pSJVxw7Koy22WvzFFIvGHWro7XrJ2AhxlvVYDiL1LNVZe0Fb0bYO2I6mXQ8K2jMqXy vshQ/rNhhaEDJQn0pLSr6qO9UJeUM2FjYeKORjWxlxiDmaA3U/f29UR X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=GNoF0+NK c=1 sm=1 tr=0 ts=69c0e89b cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=OKc3O2-h_waFBcwqEmQA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDA1NCBTYWx0ZWRfXyvsOpmbrR+yv vYQOMjZRRlZRZY9hH+a41tITOD2hbvjAawC15EBlIDUYcYdIdbEm8C9r8iJeyUh8ZYHYPtqXcSv lFcPLg3vANMzz1r3MV5lA5QTztiQOnLEwROcHVT9Gu7odrcnTyJKiNFfN+VfqlPJgiaaq09iUuv eWss2kGt+iSX3m1EkqSNe/kHSaDQJ0L68li0SQXbcpNl2BBwFaBo3x8MaeB4eSkyGoET8jEey2u Z7P5YSYHoayu1oKrBPQKoUX+psGE20q+regO2ScvZt88JTp+iZFYE6AGwBTfDWYDpjL8dYcAk5k We23ngs60YQb4OjlL8DjR041D6K9zCOs6dr6J2om1L7VUTfPXYstC2dIK5iU/iFwIF/mQwGNXsM V2bWfegH1+PtUXxePEHyZTt6m8uGbzvEqxg1D0Nm4HV0BwSgLdlARgi0G8O7A2NOgjsE7K0qrzO WMBmvikVeO8HCqUkzQg== X-Proofpoint-ORIG-GUID: Jr61l2SFJCTcrvh1tqWe8kMbzKAb4Pna X-Proofpoint-GUID: Jr61l2SFJCTcrvh1tqWe8kMbzKAb4Pna X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_02,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230054 The third PCIe controller on Glymur SoC supports 8-lane operation via bifurcation of two PHYs (each requires separate power domian, resets and aux clk). Add dedicated reset/no_csr reset list ("phy_b", "phy_b_nocsr") and clock ("phy_b_aux") required for 8-lane operation. Introduce new glymur_qmp_gen5x8_pciephy_cfg configuration to enable PCIe Gen5 x8 mode. Signed-off-by: Qiang Yu Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 30 ++++++++++++++++++++++++++++= +- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 51db9eea41255bad0034bbcfbfdc36894c2bc95f..e872b50b11da50e6317ce7e1acf= 6385925f92cdb 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3376,7 +3376,7 @@ static inline void qphy_clrbits(void __iomem *base, u= 32 offset, u32 val) =20 /* list of clocks required by phy */ static const char * const qmp_pciephy_clk_l[] =3D { - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "phy_b_aux", }; =20 /* list of regulators */ @@ -3401,6 +3401,14 @@ static const char * const sm8550_pciephy_nocsr_reset= _l[] =3D { "phy_nocsr", }; =20 +static const char * const glymur_pciephy_reset_l[] =3D { + "phy", "phy_b" +}; + +static const char * const glymur_pciephy_nocsr_reset_l[] =3D { + "phy_nocsr", "phy_b_nocsr", +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp =3D { .serdes =3D 0, .pcs =3D 0x1800, @@ -4705,6 +4713,23 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pc= iephy_cfg =3D { .phy_status =3D PHYSTATUS_4_20, }; =20 +static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg =3D { + .lanes =3D 8, + + .offsets =3D &qmp_pcie_offsets_v8_50, + + .reset_list =3D glymur_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(glymur_pciephy_reset_l), + .nocsr_reset_list =3D glymur_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(glymur_pciephy_nocsr_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + + .regs =3D pciephy_v8_50_regs_layout, + + .phy_status =3D PHYSTATUS_4_20, +}; + static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_ph= y_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -5483,6 +5508,9 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy", .data =3D &glymur_qmp_gen5x4_pciephy_cfg, + }, { + .compatible =3D "qcom,glymur-qmp-gen5x8-pcie-phy", + .data =3D &glymur_qmp_gen5x8_pciephy_cfg, }, { .compatible =3D "qcom,ipq6018-qmp-pcie-phy", .data =3D &ipq6018_pciephy_cfg, --=20 2.34.1