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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c10b14cadbsm13997886eec.3.2026.03.23.00.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 00:15:35 -0700 (PDT) From: Qiang Yu Date: Mon, 23 Mar 2026 00:15:30 -0700 Subject: [PATCH v2 3/5] phy: qcom: qmp-pcie: Support multiple nocsr resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-glymur_gen5x8_phy_0323-v2-3-ce0fc07f0e52@oss.qualcomm.com> References: <20260323-glymur_gen5x8_phy_0323-v2-0-ce0fc07f0e52@oss.qualcomm.com> In-Reply-To: <20260323-glymur_gen5x8_phy_0323-v2-0-ce0fc07f0e52@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774250130; l=10138; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=DxC/gzVZbMcfvTcP9R5APmqYjCaKSVBVLpWXzTTw9Eo=; b=hQ0y5v1WwDFOAQr/O8x+Dz+1lSYukKZ5z8dc9CwzbaREjpcD6ua+3b8IT6L34UXwpKX17gbNM rKVMqYsLNtRC5B4Uy5XkDV3idQtD2aJK6tWS8FP0elDb/XJNqm5+RfZ X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDA1NCBTYWx0ZWRfX4tIJa42cjQkH 3Yp2fWsC6kqjMT95Ia05gRcAp1fWWPqCRZZPCT9udSJEY5MP/eRRGJnNEAAHIOPavMpzytEcUoP vdVumStbjGbitQI8KOv5Zi5bOLMZypPLnELQSZUEQPqRKt1Xv5hhiw3iivtTYNtjlUyjGTHZD2r MiX3E6+eQiBMGUlBPC0fFvpx4BMFqV+KV86mnX/OkCCefMPpeqYy0lbUNi7DJi2aiN5hRrZlxXa ozKv3HVSNSqNhOQyCG22Ct5UMQDGQJIGrgg7MN6HhwofU+QBXRgBREVUFSG98SidPiCqGakGRHQ RfEUA33VnOBOCLx6V7v6IvVX12t3yCLfZw5Ju2fthh6ULDA71DvExaxeFWy7jnwutB9nNIStMip EjsmOv6FV3/j+Hwdwi3u84ARLSYRiPdqDicFkDKQ+xj4Dz8Bge83M/5zSOj0DjkXwCWLONoOYfi mm7LOVGz6ZPgHg8kHcg== X-Proofpoint-ORIG-GUID: gBpg4wPLwcuLqEX86USTm6YvtCpVSC-R X-Authority-Analysis: v=2.4 cv=Q4DfIo2a c=1 sm=1 tr=0 ts=69c0e89a cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=wBkCwaD4edhj46uzH8YA:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-GUID: gBpg4wPLwcuLqEX86USTm6YvtCpVSC-R X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_02,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230054 Refactor nocsr reset handling to support multiple nocsr resets required for PHY configurations with bifurcated operation modes. The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in bifurcation, where each PHY requires its own nocsr reset to be controlled simultaneously. The current implementation only supports a single nocsr reset per PHY configuration. Add num_nocsr and nocsr_list fields to struct qmp_phy_cfg to represent the number and names of a group of nocsr reset names. Initialize these fields for all PHYs that have nocsr resets, allowing the driver to correctly acquire multiple nocsr resets during probe and control them as an array by using reset_control_bulk APIs. The refactoring maintains backward compatibility for existing single nocsr reset configurations while enabling support for multi-PHY scenarios like Glymur's 8-lane bifurcation mode. Additionally, introduces x1e80100_qmp_gen3x2_pciephy_cfg as a separate configuration from sm8550_qmp_gen3x2_pciephy_cfg since the x1e80100 Gen3x2 PHY requires nocsr reset support while the sm8550 Gen3x2 PHY does not. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 87 ++++++++++++++++++++++++++++= ---- 1 file changed, 77 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 424c935e27a8766e1e26762bd3d7df527c1520e3..51db9eea41255bad0034bbcfbfd= c36894c2bc95f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3281,6 +3281,11 @@ struct qmp_phy_cfg { /* resets to be requested */ const char * const *reset_list; int num_resets; + + /* nocsr resets to be requested */ + const char * const *nocsr_reset_list; + int num_nocsr_resets; + /* regulators to be requested */ const char * const *vreg_list; int num_vregs; @@ -3327,7 +3332,7 @@ struct qmp_pcie { int num_pipe_clks; =20 struct reset_control_bulk_data *resets; - struct reset_control *nocsr_reset; + struct reset_control_bulk_data *nocsr_reset; struct regulator_bulk_data *vregs; =20 struct phy *phy; @@ -3392,6 +3397,10 @@ static const char * const sdm845_pciephy_reset_l[] = =3D { "phy", }; =20 +static const char * const sm8550_pciephy_nocsr_reset_l[] =3D { + "phy_nocsr", +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp =3D { .serdes =3D 0, .pcs =3D 0x1800, @@ -4348,6 +4357,8 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pci= ephy_cfg =3D { }, .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D sm8550_qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4380,6 +4391,8 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pci= ephy_cfg =3D { }, .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D sm8550_qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(sm8550_qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4480,6 +4493,35 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_p= ciephy_cfg =3D { .phy_status =3D PHYSTATUS_4_20, }; =20 +static const struct qmp_phy_cfg x1e80100_qmp_gen3x2_pciephy_cfg =3D { + .lanes =3D 2, + + .offsets =3D &qmp_pcie_offsets_v5, + + .tbls =3D { + .serdes =3D sm8550_qmp_gen3x2_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), + .tx =3D sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx =3D sm8550_qmp_gen3x2_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), + .pcs =3D sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc =3D sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D pciephy_v5_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, +}; + static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg =3D { .lanes =3D 2, =20 @@ -4502,6 +4544,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_p= ciephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4535,6 +4579,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_p= ciephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4566,6 +4612,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_p= ciephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4581,6 +4629,8 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy= _cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v6_regs_layout, @@ -4609,6 +4659,8 @@ static const struct qmp_phy_cfg qmp_v8_gen3x2_pciephy= _cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v8_regs_layout, @@ -4624,6 +4676,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pci= ephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), =20 @@ -4640,6 +4694,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pci= ephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list =3D sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), =20 @@ -4768,7 +4824,7 @@ static int qmp_pcie_init(struct phy *phy) } } =20 - ret =3D reset_control_assert(qmp->nocsr_reset); + ret =3D reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_reset= ); if (ret) { dev_err(qmp->dev, "no-csr reset assert failed\n"); goto err_assert_reset; @@ -4805,7 +4861,7 @@ static int qmp_pcie_exit(struct phy *phy) const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 if (qmp->nocsr_reset) - reset_control_assert(qmp->nocsr_reset); + reset_control_bulk_assert(cfg->num_nocsr_resets, qmp->nocsr_reset); else reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 @@ -4849,7 +4905,7 @@ static int qmp_pcie_power_on(struct phy *phy) if (ret) return ret; =20 - ret =3D reset_control_deassert(qmp->nocsr_reset); + ret =3D reset_control_bulk_deassert(cfg->num_nocsr_resets, qmp->nocsr_res= et); if (ret) { dev_err(qmp->dev, "no-csr reset deassert failed\n"); goto err_disable_pipe_clk; @@ -4998,14 +5054,25 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) for (i =3D 0; i < cfg->num_resets; i++) qmp->resets[i].id =3D cfg->reset_list[i]; =20 - ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->= resets); + ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, + qmp->resets); if (ret) return dev_err_probe(dev, ret, "failed to get resets\n"); =20 - qmp->nocsr_reset =3D devm_reset_control_get_optional_exclusive(dev, "phy_= nocsr"); - if (IS_ERR(qmp->nocsr_reset)) - return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), - "failed to get no-csr reset\n"); + if (!cfg->num_nocsr_resets) + return 0; + qmp->nocsr_reset =3D devm_kcalloc(dev, cfg->num_nocsr_resets, + sizeof(*qmp->nocsr_reset), GFP_KERNEL); + if (!qmp->nocsr_reset) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_nocsr_resets; i++) + qmp->nocsr_reset[i].id =3D cfg->nocsr_reset_list[i]; + + ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_nocsr_resets, + qmp->nocsr_reset); + if (ret) + return dev_err_probe(dev, ret, "failed to get no-csr reset\n"); =20 return 0; } @@ -5520,7 +5587,7 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { .data =3D &sm8750_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,x1e80100-qmp-gen3x2-pcie-phy", - .data =3D &sm8550_qmp_gen3x2_pciephy_cfg, + .data =3D &x1e80100_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,x1e80100-qmp-gen4x2-pcie-phy", .data =3D &x1e80100_qmp_gen4x2_pciephy_cfg, --=20 2.34.1