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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c10b14cadbsm13997886eec.3.2026.03.23.00.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 00:15:32 -0700 (PDT) From: Qiang Yu Date: Mon, 23 Mar 2026 00:15:28 -0700 Subject: [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-glymur_gen5x8_phy_0323-v2-1-ce0fc07f0e52@oss.qualcomm.com> References: <20260323-glymur_gen5x8_phy_0323-v2-0-ce0fc07f0e52@oss.qualcomm.com> In-Reply-To: <20260323-glymur_gen5x8_phy_0323-v2-0-ce0fc07f0e52@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774250130; l=3719; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=0cxDH4J+ogpnd/2Sh8T/+lD9ulgjspAUfkAYG3Mt/CY=; b=TKbSq0yuYb3Fe94qzlQGwjzQIQDc/sbsearhsGusfuWkOeh/nnkijAoxAlAijPB8IxtkofTtu H56m2yBdqZzC5saTMQ+XMFW2aQ8VEqrKsgWZqw/WsESp2wEuYK0xurU X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-GUID: zhPzIr2W7e-a3G6EseCr1rCJorH_-HNn X-Authority-Analysis: v=2.4 cv=Z5rh3XRA c=1 sm=1 tr=0 ts=69c0e896 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=RFdnLZz7-LqoW1cxMWEA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDA1NCBTYWx0ZWRfX+OAex2kS83aq 7Q7ZUxTCbys7JsapOAlYxx9Hdys6pV7liVCJMXtW4Um8d3DYG2UdC5NUf+ANyNkgRjK4nA6Pzom 39voqQGoeN1iGjoaAQXK5U5/3hXWJWIltadahkIfe0xW2SA7dqEeRI7XS8hCldIWTpzHcGpbDH2 j72RHFaHwEQL3aG8rZ+FVtyg9R6fy+0eSgELdYRni9znMod2WsGUxFtSMvIm0bvkv0uHcVqhdXC kmkQVTQE5+lhAzpc3cntzLRL7uPpLgi5o/ahQHoJh6mQx20djD79Fp0jU8NL38cWLjVTmfBjN5b TzEWXOimSU1mvHCP81ZCOrTnBUwKhpY66i+jNLBynoI13B6XYWBEdJM6m7Fc1bL0lFLnRRo8qHy 3WVyEdCzd7dx7eBXcVksJxODpNcSeCgMAVcGsa2Dh2iQ6Wd6/iEbY2S3kNuCx+fOuLiEXp2E9nS lKdrbyMcHN1qtS2h/UA== X-Proofpoint-ORIG-GUID: zhPzIr2W7e-a3G6EseCr1rCJorH_-HNn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_02,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 suspectscore=0 clxscore=1015 spamscore=0 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230054 The Glymur SoC has pcie3a and pcie3b PHYs that can operate in two modes: 1. Independent 4-lane mode: Each PHY operates as a separate PCIe Gen5 4-lane interface, compatible with qcom,glymur-qmp-gen5x4-pcie-phy 2. Bifurcation mode (8-lane): pcie3a phy acts as leader and pcie3b phy as follower to form a single 8-lane PCIe Gen5 interface In bifurcation mode, the hardware design requires controlling additional resources beyond the standard pcie3a PHY configuration: - pcie3b's aux_clk (phy_b_aux) - pcie3b's phy_gdsc power domain - pcie3b's bcr/nocsr reset Add qcom,glymur-qmp-gen5x8-pcie-phy compatible string to document this 8-lane bifurcation configuration. The phy_b_aux clock is used as the 6th clock instead of pipediv2, requiring the clock-names enum to be extended to support both [phy_b_aux, pipediv2] options at index 5. This follows the existing pattern used for [rchng, refgen] clocks at index 3. Signed-off-by: Qiang Yu --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 45 ++++++++++++++++++= ---- 1 file changed, 37 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 3a35120a77ec0ceb814a1cdcacff32fef32b4f7b..25717bc9be98824e38f3c27c329= 9fbd1f2e7e299 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy @@ -68,20 +69,23 @@ properties: - const: ref - enum: [rchng, refgen] - const: pipe - - const: pipediv2 + - enum: [phy_b_aux, pipediv2] =20 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 resets: minItems: 1 - maxItems: 2 + maxItems: 4 =20 reset-names: minItems: 1 items: - const: phy - const: phy_nocsr + - const: phy_b + - const: phy_b_nocsr =20 vdda-phy-supply: true =20 @@ -183,6 +187,7 @@ allOf: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy @@ -201,6 +206,17 @@ allOf: clock-names: minItems: 6 =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + power-domains: + minItems: 2 + - if: properties: compatible: @@ -223,11 +239,24 @@ allOf: reset-names: minItems: 2 else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 + if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + resets: + minItems: 4 + reset-names: + minItems: 4 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 =20 - if: properties: --=20 2.34.1