From nobody Fri Apr 3 19:06:00 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40DB53E6DDF; Mon, 23 Mar 2026 20:59:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774299563; cv=none; b=LDN/6fwe8kQHIzvCtn01Nbxf++BmwRjESxVlMsSr+CxsBSdL/no4w3KsotPrHaBwiUyVTbozPTCF1tRFLb3cNoWqOBPFGrWtus910Rb+2BUXFh8C38wWeGkCfQ4YunhZx4VzwKnwZ9qNbcHdtenecWZQdrTnJdpHrVoY0pD6W9A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774299563; c=relaxed/simple; bh=hIQCG6aKDRwNVHIvc2POBKg1qdnKUA9L+WNuGruizqA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=amedpGpWaF/0j5a7ycVqzdUmMsBI4ITOKqUNhMknETRqBuN4oshCA2fwLfyl2e3f9KQdcGeyzspYeC9a66WrOTHsVXcjtLq7O/HIgmj+l1AkYl/DM9AoSTZbA918kObKhGLu39yHc5M6GrXOcsxibiDQ4JDs7HyVfWLpyt53J/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ApmGyBTu; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ApmGyBTu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774299562; x=1805835562; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=hIQCG6aKDRwNVHIvc2POBKg1qdnKUA9L+WNuGruizqA=; b=ApmGyBTu7iRHYqLCT1aZdwxrgv9/ia6pg8Tr+DijCIC0oShiQP4idjJb NbqY+YbDDNktelVr58DBFsVm0Ctz7D1mmxZWwcqylpEc1+7AADy+fg4js UppldTQdIIxa1x0qtsRuITuqoSfN8vupOkhocspp+VmYUV4GOhiYb/yuD yP7vuM701IdTONOGfx4V+ewjewX0fiGFGrvrQB07hIRgLlfnYQ590H92Q m6WS3hGfULmnK6YzzZde8u77KA+2rlFRqXZkRSrKzjpIpdWagr2vmzMd4 Ecb4nXbpl3oUjTg4JIoo/JlGIKVvydeKLTb4Fl02mntDSfIGR0jrOn6MU Q==; X-CSE-ConnectionGUID: 5nLgx2c4SOmFDVZLaNBllA== X-CSE-MsgGUID: FGOHuA8oRASq8RlAm0RItA== X-IronPort-AV: E=McAfee;i="6800,10657,11738"; a="74491137" X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="74491137" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:21 -0700 X-CSE-ConnectionGUID: 1zNwAG5gSfOJFL/0V6bXEQ== X-CSE-MsgGUID: OhveJpLVQe23r5QsEyU2hw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="224156857" Received: from vverma7-desk1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.124.221.51]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:20 -0700 From: Vishal Verma Date: Mon, 23 Mar 2026 14:59:04 -0600 Subject: [PATCH v2 1/5] x86/tdx: Move all TDX error defines into Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-fuller_tdx_kexec_support-v2-1-87a36409e051@intel.com> References: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> In-Reply-To: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe , Sean Christopherson , Paolo Bonzini Cc: linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, Vishal Verma , Kiryl Shutsemau , Kiryl Shutsemau X-Mailer: b4 0.16-dev-8c19c X-Developer-Signature: v=1; a=openpgp-sha256; l=5502; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=QtM5LzcN7/8nTW+0OZZ7dh44UAM2aBijSQgkC3ueyKs=; b=owGbwMvMwCXGf25diOft7jLG02pJDJkHVy57ZX1zk07S35asV18PF0WxrjfVLe79Hmmjcm3P0 mtCry5XdJSyMIhxMciKKbL83fOR8Zjc9nyewARHmDmsTCBDGLg4BWAitqsY/tfMbAvVfqnG2Olq wXF216dY7eKtjM2nG+4f3zQ38q3ov5kM/2M0BS2lOufyJHPIf/+rq9sibGjFv/vGb58FrrN6iv7 LcAEA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF From: "Kirill A. Shutemov" Today there are two separate locations where TDX error codes are defined: arch/x86/include/asm/tdx.h arch/x86/kvm/vmx/tdx_errno.h They have some overlap that is already defined similarly. Reduce the duplication and prepare to introduce some helpers for these error codes in the central place by unifying them. Join them at: asm/shared/tdx_errno.h ...and update the headers that contained the duplicated definitions to include the new unified header. "asm/shared" is used for sharing TDX code between the early compressed code and the normal kernel code. While the compressed code for the guest doesn't use these error code header definitions today, it does make the types of calls that return the values they define. So place the defines in "shared" location so that it can, but leave such cleanups for future changes. Also, adjust BITUL() -> _BITULL() to address 32 bit build errors after the move. Signed-off-by: Kirill A. Shutemov [enhance log] Signed-off-by: Rick Edgecombe Signed-off-by: Vishal Verma Reviewed-by: Chao Gao --- arch/x86/include/asm/shared/tdx.h | 1 + .../{kvm/vmx =3D> include/asm/shared}/tdx_errno.h | 28 ++++++++++++++++= +----- arch/x86/include/asm/tdx.h | 21 ---------------- arch/x86/kvm/vmx/tdx.h | 1 - 4 files changed, 23 insertions(+), 28 deletions(-) diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index 8bc074c8d7c6..6a1646fc2b2f 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #define TDX_HYPERCALL_STANDARD 0 =20 diff --git a/arch/x86/kvm/vmx/tdx_errno.h b/arch/x86/include/asm/shared/tdx= _errno.h similarity index 64% rename from arch/x86/kvm/vmx/tdx_errno.h rename to arch/x86/include/asm/shared/tdx_errno.h index 6ff4672c4181..8bf6765cf082 100644 --- a/arch/x86/kvm/vmx/tdx_errno.h +++ b/arch/x86/include/asm/shared/tdx_errno.h @@ -1,14 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* architectural status code for SEAMCALL */ - -#ifndef __KVM_X86_TDX_ERRNO_H -#define __KVM_X86_TDX_ERRNO_H +#ifndef _ASM_X86_SHARED_TDX_ERRNO_H +#define _ASM_X86_SHARED_TDX_ERRNO_H +#include =20 +/* Upper 32 bit of the TDX error code encodes the status */ #define TDX_SEAMCALL_STATUS_MASK 0xFFFFFFFF00000000ULL =20 /* - * TDX SEAMCALL Status Codes (returned in RAX) + * TDX Status Codes (returned in RAX) */ +#define TDX_SUCCESS 0ULL #define TDX_NON_RECOVERABLE_VCPU 0x4000000100000000ULL #define TDX_NON_RECOVERABLE_TD 0x4000000200000000ULL #define TDX_NON_RECOVERABLE_TD_NON_ACCESSIBLE 0x6000000500000000ULL @@ -17,6 +18,7 @@ #define TDX_OPERAND_INVALID 0xC000010000000000ULL #define TDX_OPERAND_BUSY 0x8000020000000000ULL #define TDX_PREVIOUS_TLB_EPOCH_BUSY 0x8000020100000000ULL +#define TDX_RND_NO_ENTROPY 0x8000020300000000ULL #define TDX_PAGE_METADATA_INCORRECT 0xC000030000000000ULL #define TDX_VCPU_NOT_ASSOCIATED 0x8000070200000000ULL #define TDX_KEY_GENERATION_FAILED 0x8000080000000000ULL @@ -28,6 +30,20 @@ #define TDX_EPT_ENTRY_STATE_INCORRECT 0xC0000B0D00000000ULL #define TDX_METADATA_FIELD_NOT_READABLE 0xC0000C0200000000ULL =20 +/* + * SW-defined error codes. + * + * Bits 47:40 =3D=3D 0xFF indicate Reserved status code class that never u= sed by + * TDX module. + */ +#define TDX_ERROR _BITULL(63) +#define TDX_NON_RECOVERABLE _BITULL(62) +#define TDX_SW_ERROR (TDX_ERROR | GENMASK_ULL(47, 40)) +#define TDX_SEAMCALL_VMFAILINVALID (TDX_SW_ERROR | _ULL(0xFFFF0000)) + +#define TDX_SEAMCALL_GP (TDX_SW_ERROR | X86_TRAP_GP) +#define TDX_SEAMCALL_UD (TDX_SW_ERROR | X86_TRAP_UD) + /* * TDX module operand ID, appears in 31:0 part of error code as * detail information @@ -37,4 +53,4 @@ #define TDX_OPERAND_ID_SEPT 0x92 #define TDX_OPERAND_ID_TD_EPOCH 0xa9 =20 -#endif /* __KVM_X86_TDX_ERRNO_H */ +#endif /* _ASM_X86_SHARED_TDX_ERRNO_H */ diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index a149740b24e8..2917b3451491 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -9,29 +9,8 @@ =20 #include #include -#include #include =20 -/* - * SW-defined error codes. - * - * Bits 47:40 =3D=3D 0xFF indicate Reserved status code class that never u= sed by - * TDX module. - */ -#define TDX_ERROR _BITUL(63) -#define TDX_NON_RECOVERABLE _BITUL(62) -#define TDX_SW_ERROR (TDX_ERROR | GENMASK_ULL(47, 40)) -#define TDX_SEAMCALL_VMFAILINVALID (TDX_SW_ERROR | _UL(0xFFFF0000)) - -#define TDX_SEAMCALL_GP (TDX_SW_ERROR | X86_TRAP_GP) -#define TDX_SEAMCALL_UD (TDX_SW_ERROR | X86_TRAP_UD) - -/* - * TDX module SEAMCALL leaf function error codes - */ -#define TDX_SUCCESS 0ULL -#define TDX_RND_NO_ENTROPY 0x8000020300000000ULL - #ifndef __ASSEMBLER__ =20 #include diff --git a/arch/x86/kvm/vmx/tdx.h b/arch/x86/kvm/vmx/tdx.h index b5cd2ffb303e..ac8323a68b16 100644 --- a/arch/x86/kvm/vmx/tdx.h +++ b/arch/x86/kvm/vmx/tdx.h @@ -3,7 +3,6 @@ #define __KVM_X86_VMX_TDX_H =20 #include "tdx_arch.h" -#include "tdx_errno.h" =20 #ifdef CONFIG_KVM_INTEL_TDX #include "common.h" --=20 2.53.0