From nobody Fri Apr 3 17:37:50 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40DB53E6DDF; Mon, 23 Mar 2026 20:59:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774299563; cv=none; b=LDN/6fwe8kQHIzvCtn01Nbxf++BmwRjESxVlMsSr+CxsBSdL/no4w3KsotPrHaBwiUyVTbozPTCF1tRFLb3cNoWqOBPFGrWtus910Rb+2BUXFh8C38wWeGkCfQ4YunhZx4VzwKnwZ9qNbcHdtenecWZQdrTnJdpHrVoY0pD6W9A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774299563; c=relaxed/simple; bh=hIQCG6aKDRwNVHIvc2POBKg1qdnKUA9L+WNuGruizqA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=amedpGpWaF/0j5a7ycVqzdUmMsBI4ITOKqUNhMknETRqBuN4oshCA2fwLfyl2e3f9KQdcGeyzspYeC9a66WrOTHsVXcjtLq7O/HIgmj+l1AkYl/DM9AoSTZbA918kObKhGLu39yHc5M6GrXOcsxibiDQ4JDs7HyVfWLpyt53J/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ApmGyBTu; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ApmGyBTu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774299562; x=1805835562; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=hIQCG6aKDRwNVHIvc2POBKg1qdnKUA9L+WNuGruizqA=; b=ApmGyBTu7iRHYqLCT1aZdwxrgv9/ia6pg8Tr+DijCIC0oShiQP4idjJb NbqY+YbDDNktelVr58DBFsVm0Ctz7D1mmxZWwcqylpEc1+7AADy+fg4js UppldTQdIIxa1x0qtsRuITuqoSfN8vupOkhocspp+VmYUV4GOhiYb/yuD yP7vuM701IdTONOGfx4V+ewjewX0fiGFGrvrQB07hIRgLlfnYQ590H92Q m6WS3hGfULmnK6YzzZde8u77KA+2rlFRqXZkRSrKzjpIpdWagr2vmzMd4 Ecb4nXbpl3oUjTg4JIoo/JlGIKVvydeKLTb4Fl02mntDSfIGR0jrOn6MU Q==; X-CSE-ConnectionGUID: 5nLgx2c4SOmFDVZLaNBllA== X-CSE-MsgGUID: FGOHuA8oRASq8RlAm0RItA== X-IronPort-AV: E=McAfee;i="6800,10657,11738"; a="74491137" X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="74491137" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:21 -0700 X-CSE-ConnectionGUID: 1zNwAG5gSfOJFL/0V6bXEQ== X-CSE-MsgGUID: OhveJpLVQe23r5QsEyU2hw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="224156857" Received: from vverma7-desk1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.124.221.51]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:20 -0700 From: Vishal Verma Date: Mon, 23 Mar 2026 14:59:04 -0600 Subject: [PATCH v2 1/5] x86/tdx: Move all TDX error defines into Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-fuller_tdx_kexec_support-v2-1-87a36409e051@intel.com> References: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> In-Reply-To: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe , Sean Christopherson , Paolo Bonzini Cc: linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, Vishal Verma , Kiryl Shutsemau , Kiryl Shutsemau X-Mailer: b4 0.16-dev-8c19c X-Developer-Signature: v=1; a=openpgp-sha256; l=5502; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=QtM5LzcN7/8nTW+0OZZ7dh44UAM2aBijSQgkC3ueyKs=; b=owGbwMvMwCXGf25diOft7jLG02pJDJkHVy57ZX1zk07S35asV18PF0WxrjfVLe79Hmmjcm3P0 mtCry5XdJSyMIhxMciKKbL83fOR8Zjc9nyewARHmDmsTCBDGLg4BWAitqsY/tfMbAvVfqnG2Olq wXF216dY7eKtjM2nG+4f3zQ38q3ov5kM/2M0BS2lOufyJHPIf/+rq9sibGjFv/vGb58FrrN6iv7 LcAEA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF From: "Kirill A. Shutemov" Today there are two separate locations where TDX error codes are defined: arch/x86/include/asm/tdx.h arch/x86/kvm/vmx/tdx_errno.h They have some overlap that is already defined similarly. Reduce the duplication and prepare to introduce some helpers for these error codes in the central place by unifying them. Join them at: asm/shared/tdx_errno.h ...and update the headers that contained the duplicated definitions to include the new unified header. "asm/shared" is used for sharing TDX code between the early compressed code and the normal kernel code. While the compressed code for the guest doesn't use these error code header definitions today, it does make the types of calls that return the values they define. So place the defines in "shared" location so that it can, but leave such cleanups for future changes. Also, adjust BITUL() -> _BITULL() to address 32 bit build errors after the move. Signed-off-by: Kirill A. Shutemov [enhance log] Signed-off-by: Rick Edgecombe Signed-off-by: Vishal Verma Reviewed-by: Chao Gao --- arch/x86/include/asm/shared/tdx.h | 1 + .../{kvm/vmx =3D> include/asm/shared}/tdx_errno.h | 28 ++++++++++++++++= +----- arch/x86/include/asm/tdx.h | 21 ---------------- arch/x86/kvm/vmx/tdx.h | 1 - 4 files changed, 23 insertions(+), 28 deletions(-) diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index 8bc074c8d7c6..6a1646fc2b2f 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #define TDX_HYPERCALL_STANDARD 0 =20 diff --git a/arch/x86/kvm/vmx/tdx_errno.h b/arch/x86/include/asm/shared/tdx= _errno.h similarity index 64% rename from arch/x86/kvm/vmx/tdx_errno.h rename to arch/x86/include/asm/shared/tdx_errno.h index 6ff4672c4181..8bf6765cf082 100644 --- a/arch/x86/kvm/vmx/tdx_errno.h +++ b/arch/x86/include/asm/shared/tdx_errno.h @@ -1,14 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* architectural status code for SEAMCALL */ - -#ifndef __KVM_X86_TDX_ERRNO_H -#define __KVM_X86_TDX_ERRNO_H +#ifndef _ASM_X86_SHARED_TDX_ERRNO_H +#define _ASM_X86_SHARED_TDX_ERRNO_H +#include =20 +/* Upper 32 bit of the TDX error code encodes the status */ #define TDX_SEAMCALL_STATUS_MASK 0xFFFFFFFF00000000ULL =20 /* - * TDX SEAMCALL Status Codes (returned in RAX) + * TDX Status Codes (returned in RAX) */ +#define TDX_SUCCESS 0ULL #define TDX_NON_RECOVERABLE_VCPU 0x4000000100000000ULL #define TDX_NON_RECOVERABLE_TD 0x4000000200000000ULL #define TDX_NON_RECOVERABLE_TD_NON_ACCESSIBLE 0x6000000500000000ULL @@ -17,6 +18,7 @@ #define TDX_OPERAND_INVALID 0xC000010000000000ULL #define TDX_OPERAND_BUSY 0x8000020000000000ULL #define TDX_PREVIOUS_TLB_EPOCH_BUSY 0x8000020100000000ULL +#define TDX_RND_NO_ENTROPY 0x8000020300000000ULL #define TDX_PAGE_METADATA_INCORRECT 0xC000030000000000ULL #define TDX_VCPU_NOT_ASSOCIATED 0x8000070200000000ULL #define TDX_KEY_GENERATION_FAILED 0x8000080000000000ULL @@ -28,6 +30,20 @@ #define TDX_EPT_ENTRY_STATE_INCORRECT 0xC0000B0D00000000ULL #define TDX_METADATA_FIELD_NOT_READABLE 0xC0000C0200000000ULL =20 +/* + * SW-defined error codes. + * + * Bits 47:40 =3D=3D 0xFF indicate Reserved status code class that never u= sed by + * TDX module. + */ +#define TDX_ERROR _BITULL(63) +#define TDX_NON_RECOVERABLE _BITULL(62) +#define TDX_SW_ERROR (TDX_ERROR | GENMASK_ULL(47, 40)) +#define TDX_SEAMCALL_VMFAILINVALID (TDX_SW_ERROR | _ULL(0xFFFF0000)) + +#define TDX_SEAMCALL_GP (TDX_SW_ERROR | X86_TRAP_GP) +#define TDX_SEAMCALL_UD (TDX_SW_ERROR | X86_TRAP_UD) + /* * TDX module operand ID, appears in 31:0 part of error code as * detail information @@ -37,4 +53,4 @@ #define TDX_OPERAND_ID_SEPT 0x92 #define TDX_OPERAND_ID_TD_EPOCH 0xa9 =20 -#endif /* __KVM_X86_TDX_ERRNO_H */ +#endif /* _ASM_X86_SHARED_TDX_ERRNO_H */ diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index a149740b24e8..2917b3451491 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -9,29 +9,8 @@ =20 #include #include -#include #include =20 -/* - * SW-defined error codes. - * - * Bits 47:40 =3D=3D 0xFF indicate Reserved status code class that never u= sed by - * TDX module. - */ -#define TDX_ERROR _BITUL(63) -#define TDX_NON_RECOVERABLE _BITUL(62) -#define TDX_SW_ERROR (TDX_ERROR | GENMASK_ULL(47, 40)) -#define TDX_SEAMCALL_VMFAILINVALID (TDX_SW_ERROR | _UL(0xFFFF0000)) - -#define TDX_SEAMCALL_GP (TDX_SW_ERROR | X86_TRAP_GP) -#define TDX_SEAMCALL_UD (TDX_SW_ERROR | X86_TRAP_UD) - -/* - * TDX module SEAMCALL leaf function error codes - */ -#define TDX_SUCCESS 0ULL -#define TDX_RND_NO_ENTROPY 0x8000020300000000ULL - #ifndef __ASSEMBLER__ =20 #include diff --git a/arch/x86/kvm/vmx/tdx.h b/arch/x86/kvm/vmx/tdx.h index b5cd2ffb303e..ac8323a68b16 100644 --- a/arch/x86/kvm/vmx/tdx.h +++ b/arch/x86/kvm/vmx/tdx.h @@ -3,7 +3,6 @@ #define __KVM_X86_VMX_TDX_H =20 #include "tdx_arch.h" -#include "tdx_errno.h" =20 #ifdef CONFIG_KVM_INTEL_TDX #include "common.h" --=20 2.53.0 From nobody Fri Apr 3 17:37:50 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9A9C3E6DC1; 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a="74491145" X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="74491145" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:22 -0700 X-CSE-ConnectionGUID: HdZtdTYER86SMMZEokeEMw== X-CSE-MsgGUID: Krm3cOcAS2G3njxUOMqI6A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="224156863" Received: from vverma7-desk1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.124.221.51]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:21 -0700 From: Vishal Verma Date: Mon, 23 Mar 2026 14:59:05 -0600 Subject: [PATCH v2 2/5] x86/virt/tdx: Pull kexec cache flush logic into arch/x86 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-fuller_tdx_kexec_support-v2-2-87a36409e051@intel.com> References: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> In-Reply-To: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe , Sean Christopherson , Paolo Bonzini Cc: linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, Kai Huang , Vishal Verma X-Mailer: b4 0.16-dev-8c19c X-Developer-Signature: v=1; a=openpgp-sha256; l=5080; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=pZWrnyf3cSew4qBVy0JtSlpvCZz6uFzhY0igFGY8cTM=; b=owGbwMvMwCXGf25diOft7jLG02pJDJkHVy6bNcknOHaNZnbpiWM9GXHt+ifTDitJ9fWap2lPK GCyKl/cUcrCIMbFICumyPJ3z0fGY3Lb83kCExxh5rAygQxh4OIUgIl0H2JkmHk6WSCBM3H6GqMX fr36Ksc5IwPnX804k2o9IbnQNr7yLyPDlfqakEkp6YyX3n9N+BTVPs+1ZtvcqU5fLqYrnGJ3jJr CDQA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF From: Rick Edgecombe KVM tries to take care of some required cache flushing earlier in the kexec path in order to be kind to some long standing races that can occur later in the operation. Until recently, VMXOFF was handled within KVM. Since VMX being enabled is required to make a SEAMCALL, it had the best per-cpu scoped operation to plug the flushing into. So it is kicked off from there. This early kexec cache flushing in KVM happens via a syscore shutdown callback. Now that VMX enablement control has moved to arch/x86, which has grown its own syscore shutdown callback, it no longer make sense for it to live in KVM. It fits better with the TDX enablement managing code. In addition, future changes will add a SEAMCALL that happens immediately before VMXOFF, which means the cache flush in KVM will be too late to flush the cache before the last SEAMCALL. So move it to the newly added TDX arch/x86 syscore shutdown handler. Since tdx_cpu_flush_cache_for_kexec() is no longer needed by KVM, make it static and remove the export. Since it is also not part of an operation spread across disparate components, remove the redundant comments and verbose naming. In the existing KVM based code, CPU offline also funnels through tdx_cpu_flush_cache_for_kexec(). So the centralization to the arch/x86 syscore shutdown callback elides this CPU offline time behavior. However, WBINVD is already generally done at CPU offline as matter of course. So don't bother adding TDX specific logic for this, and rely on the normal WBINVD to handle it. Acked-by: Kai Huang Signed-off-by: Rick Edgecombe Signed-off-by: Vishal Verma Acked-by: Kiryl Shutsemau (Meta) Acked-by: Sean Christopherson Reviewed-by: Chao Gao --- arch/x86/include/asm/tdx.h | 6 ------ arch/x86/kvm/vmx/tdx.c | 10 ---------- arch/x86/virt/vmx/tdx/tdx.c | 39 ++++++++++++++++++++------------------- 3 files changed, 20 insertions(+), 35 deletions(-) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 2917b3451491..7674fc530090 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -205,11 +205,5 @@ static inline const char *tdx_dump_mce_info(struct mce= *m) { return NULL; } static inline const struct tdx_sys_info *tdx_get_sysinfo(void) { return NU= LL; } #endif /* CONFIG_INTEL_TDX_HOST */ =20 -#ifdef CONFIG_KEXEC_CORE -void tdx_cpu_flush_cache_for_kexec(void); -#else -static inline void tdx_cpu_flush_cache_for_kexec(void) { } -#endif - #endif /* !__ASSEMBLER__ */ #endif /* _ASM_X86_TDX_H */ diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index b7264b533feb..50a5cfdbd33e 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -440,16 +440,6 @@ void tdx_disable_virtualization_cpu(void) tdx_flush_vp(&arg); } local_irq_restore(flags); - - /* - * Flush cache now if kexec is possible: this is necessary to avoid - * having dirty private memory cachelines when the new kernel boots, - * but WBINVD is a relatively expensive operation and doing it during - * kexec can exacerbate races in native_stop_other_cpus(). Do it - * now, since this is a safe moment and there is going to be no more - * TDX activity on this CPU from this point on. - */ - tdx_cpu_flush_cache_for_kexec(); } =20 #define TDX_SEAMCALL_RETRIES 10000 diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index cb9b3210ab71..0802d0fd18a4 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -224,8 +224,28 @@ static int tdx_offline_cpu(unsigned int cpu) return 0; } =20 +static void tdx_cpu_flush_cache(void) +{ + lockdep_assert_preemption_disabled(); + + if (!this_cpu_read(cache_state_incoherent)) + return; + + wbinvd(); + this_cpu_write(cache_state_incoherent, false); +} + static void tdx_shutdown_cpu(void *ign) { + /* + * Flush cache now if kexec is possible: this is necessary to avoid + * having dirty private memory cachelines when the new kernel boots, + * but WBINVD is a relatively expensive operation and doing it during + * kexec can exacerbate races in native_stop_other_cpus(). Do it + * now, since this is a safe moment and there is going to be no more + * TDX activity on this CPU from this point on. + */ + tdx_cpu_flush_cache(); x86_virt_put_ref(X86_FEATURE_VMX); } =20 @@ -1920,22 +1940,3 @@ u64 tdh_phymem_page_wbinvd_hkid(u64 hkid, struct pag= e *page) return seamcall(TDH_PHYMEM_PAGE_WBINVD, &args); } EXPORT_SYMBOL_FOR_KVM(tdh_phymem_page_wbinvd_hkid); - -#ifdef CONFIG_KEXEC_CORE -void tdx_cpu_flush_cache_for_kexec(void) -{ - lockdep_assert_preemption_disabled(); - - if (!this_cpu_read(cache_state_incoherent)) - return; - - /* - * Private memory cachelines need to be clean at the time of - * kexec. Write them back now, as the caller promises that - * there should be no more SEAMCALLs on this CPU. - */ - wbinvd(); - this_cpu_write(cache_state_incoherent, false); -} -EXPORT_SYMBOL_FOR_KVM(tdx_cpu_flush_cache_for_kexec); -#endif --=20 2.53.0 From nobody Fri Apr 3 17:37:50 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23F623E6DF3; Mon, 23 Mar 2026 20:59:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774299573; cv=none; b=HhbUz9o4Ts7BN7UvozlIl2cHg46oMh9QHlYUospgDYDNwsty14/vuGIqrg5lveDkdTweKt7xZu/dsQte5LC8gOO1MHOTPH4Zldse/FH/Po4ngHmaRTGMmyKHUMc0hkLn4kOAdk5IYl3VzT6jO28uYBKFyKzwMCqCWhnEt8XCAzI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774299573; c=relaxed/simple; bh=P2DVlROBb3MiFEF2zbD3N1sxc8wm0dVtPD3VmuMsna8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Rfns31y4Wrvc3QMpJswtAPJpQxF/6l+TWiJSWqnbbSXvELu0ZAe6i1aHNS/MYuO1AeEE9Ph0/kA9sBQrUCxa0R35njfijLSo08+5c3YPc5a8zSg6wX6as6jr0fDGj0cZS+Lws2faioXiQFQrlDgG1uugd1NIUQSFqoMVzkgh7sI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FGpV5eZ6; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FGpV5eZ6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774299564; x=1805835564; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=P2DVlROBb3MiFEF2zbD3N1sxc8wm0dVtPD3VmuMsna8=; b=FGpV5eZ6sn9sF67aF0xCEIBeVEg7aqkm2F6N5WTSifn8qyx9oxrrtyDS tZ7xNFJSRBQMVB13lpkTKU6ej2u4M08cmQJ7dSzHgpZGM7ec3FR4Ggzki dT1/8UUHkfSFFJ9rC0fRO+3ePGTKJkpUyyPh26Fcb6JGnWjrF+D4vTOmQ 3dbDct7kfW+r3SWRZMp/XQP7ibtocwOvINeLHjOZUEKxGl/ZVbdYX5qIV ljQethuySN03uu7hiORUlhv7yKN5/Et27V04FmPBS7vmogdM4aQK5o240 skY6UOiy8p8elg7rY2OEZnDas+VF9TBjkJKj64Le4MPxzk3tH8rUV5x+7 Q==; X-CSE-ConnectionGUID: IlL2lSmDTzCXRe81hBfnGQ== X-CSE-MsgGUID: VhspFhWuRLyMn7UeI8e/NQ== X-IronPort-AV: E=McAfee;i="6800,10657,11738"; a="74491152" X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="74491152" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:23 -0700 X-CSE-ConnectionGUID: eoWAbyRMQjKofKFqzGUC1g== X-CSE-MsgGUID: IzNA7qE8TfSuzZoaU/t85A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="224156869" Received: from vverma7-desk1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.124.221.51]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:22 -0700 From: Vishal Verma Date: Mon, 23 Mar 2026 14:59:06 -0600 Subject: [PATCH v2 3/5] x86/virt/tdx: Add SEAMCALL wrapper for TDH.SYS.DISABLE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-fuller_tdx_kexec_support-v2-3-87a36409e051@intel.com> References: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> In-Reply-To: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe , Sean Christopherson , Paolo Bonzini Cc: linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, Vishal Verma X-Mailer: b4 0.16-dev-8c19c X-Developer-Signature: v=1; a=openpgp-sha256; l=5650; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=P2DVlROBb3MiFEF2zbD3N1sxc8wm0dVtPD3VmuMsna8=; b=owGbwMvMwCXGf25diOft7jLG02pJDJkHVy7zKHKdy7voQ0KY8yOLLTGbH7rwzu132rt+mf35C UfDebdkdpSyMIhxMciKKbL83fOR8Zjc9nyewARHmDmsTCBDGLg4BWAiryUZ/lkcmzDn5U3Tfxtu zbiXKWPcwr7aL+t7pL6GXn/7t9Wf791nZNhb8GGO4ZtTphLpkw7YdKat6y/7U/k2y/vfZ3bJrXX 6z3kA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Some early TDX-capable platforms have an erratum where a partial write to TDX private memory can cause a machine check on a subsequent read. On these platforms, kexec and kdump have been disabled in these cases, because the old kernel cannot safely hand off TDX state to the new kernel. Later TDX modules support the TDH.SYS.DISABLE SEAMCALL, which provides a way to cleanly disable TDX and allow kexec to proceed. The new SEAMCALL has an enumeration bit, but that is ignored. It is expected that users will be using the latest TDX module, and the failure mode for running the missing SEAMCALL on an older module is not fatal. This can be a long running operation, and the time needed largely depends on the amount of memory that has been allocated to TDs. If all TDs have been destroyed prior to the sys_disable call, then it is fast, with only needing to override the TDX module memory. After the SEAMCALL completes, the TDX module is disabled and all memory resources allocated to TDX are freed and reset. The next kernel can then re-initialize the TDX module from scratch via the normal TDX bring-up sequence. The SEAMCALL can return two different error codes that expect a retry. - TDX_INTERRUPTED_RESUMABLE can be returned in the case of a host interrupt. However, it will not return until it makes some forward progress, so we can expect to complete even in the case of interrupt storms. - TDX_SYS_BUSY will be returned on contention with other TDH.SYS.* SEAMCALLs, however a side effect of TDH.SYS.DISABLE is that it will block other SEAMCALLs once it gets going. So this contention will be short lived. So loop infinitely on either of these error codes, until success or other error. Co-developed-by: Rick Edgecombe Signed-off-by: Rick Edgecombe Signed-off-by: Vishal Verma Acked-by: Kai Huang Reviewed-by: Chao Gao Reviewed-by: Kiryl Shutsemau (Meta) --- arch/x86/include/asm/shared/tdx_errno.h | 1 + arch/x86/include/asm/tdx.h | 3 +++ arch/x86/virt/vmx/tdx/tdx.h | 1 + arch/x86/virt/vmx/tdx/tdx.c | 28 ++++++++++++++++++++++++++++ 4 files changed, 33 insertions(+) diff --git a/arch/x86/include/asm/shared/tdx_errno.h b/arch/x86/include/asm= /shared/tdx_errno.h index 8bf6765cf082..246b4fd54a48 100644 --- a/arch/x86/include/asm/shared/tdx_errno.h +++ b/arch/x86/include/asm/shared/tdx_errno.h @@ -15,6 +15,7 @@ #define TDX_NON_RECOVERABLE_TD_NON_ACCESSIBLE 0x6000000500000000ULL #define TDX_NON_RECOVERABLE_TD_WRONG_APIC_MODE 0x6000000700000000ULL #define TDX_INTERRUPTED_RESUMABLE 0x8000000300000000ULL +#define TDX_SYS_BUSY 0x8000020200000000ULL #define TDX_OPERAND_INVALID 0xC000010000000000ULL #define TDX_OPERAND_BUSY 0x8000020000000000ULL #define TDX_PREVIOUS_TLB_EPOCH_BUSY 0x8000020100000000ULL diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 7674fc530090..a0a4a15142fc 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -172,6 +172,8 @@ static inline int pg_level_to_tdx_sept_level(enum pg_le= vel level) return level - 1; } =20 +void tdx_sys_disable(void); + u64 tdh_vp_enter(struct tdx_vp *vp, struct tdx_module_args *args); u64 tdh_mng_addcx(struct tdx_td *td, struct page *tdcs_page); u64 tdh_mem_page_add(struct tdx_td *td, u64 gpa, struct page *page, struct= page *source, u64 *ext_err1, u64 *ext_err2); @@ -203,6 +205,7 @@ static inline void tdx_init(void) { } static inline u32 tdx_get_nr_guest_keyids(void) { return 0; } static inline const char *tdx_dump_mce_info(struct mce *m) { return NULL; } static inline const struct tdx_sys_info *tdx_get_sysinfo(void) { return NU= LL; } +static inline void tdx_sys_disable(void) { } #endif /* CONFIG_INTEL_TDX_HOST */ =20 #endif /* !__ASSEMBLER__ */ diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index dde219c823b4..e2cf2dd48755 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -46,6 +46,7 @@ #define TDH_PHYMEM_PAGE_WBINVD 41 #define TDH_VP_WR 43 #define TDH_SYS_CONFIG 45 +#define TDH_SYS_DISABLE 69 =20 /* * SEAMCALL leaf: diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 0802d0fd18a4..3a76000dec7a 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -1940,3 +1941,30 @@ u64 tdh_phymem_page_wbinvd_hkid(u64 hkid, struct pag= e *page) return seamcall(TDH_PHYMEM_PAGE_WBINVD, &args); } EXPORT_SYMBOL_FOR_KVM(tdh_phymem_page_wbinvd_hkid); + +void tdx_sys_disable(void) +{ + struct tdx_module_args args =3D {}; + u64 ret; + + /* + * Don't loop forever. + * - TDX_INTERRUPTED_RESUMABLE guarantees forward progress between + * calls. + * - TDX_SYS_BUSY could transiently contend with TDH.SYS.* SEAMCALLs, + * but will lock out future ones. + * + * This is a 'destructive' SEAMCALL, in that no other SEAMCALL can be + * run after this until a full reinitialization is done. + */ + do { + ret =3D seamcall(TDH_SYS_DISABLE, &args); + } while (ret =3D=3D TDX_INTERRUPTED_RESUMABLE || ret =3D=3D TDX_SYS_BUSY); + + /* + * Print SEAMCALL failures, but not SW-defined error codes + * (SEAMCALL faulted with #GP/#UD, TDX not supported). + */ + if (ret && (ret & TDX_SW_ERROR) !=3D TDX_SW_ERROR) + pr_err("TDH.SYS.DISABLE failed: 0x%016llx\n", ret); +} --=20 2.53.0 From nobody Fri Apr 3 17:37:50 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A7EC3E5EC6; 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a="74491159" X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="74491159" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:24 -0700 X-CSE-ConnectionGUID: KjKJ7GB5TiOX1EVfyw1BZg== X-CSE-MsgGUID: zIFc9fmvTPSl0LWM8Q/QGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="224156874" Received: from vverma7-desk1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.124.221.51]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:23 -0700 From: Vishal Verma Date: Mon, 23 Mar 2026 14:59:07 -0600 Subject: [PATCH v2 4/5] x86/tdx: Disable the TDX module during kexec and kdump Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-fuller_tdx_kexec_support-v2-4-87a36409e051@intel.com> References: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> In-Reply-To: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe , Sean Christopherson , Paolo Bonzini Cc: linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, Vishal Verma X-Mailer: b4 0.16-dev-8c19c X-Developer-Signature: v=1; a=openpgp-sha256; l=3582; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=pZPF5E66mGJD0tGfn+qRQzAoVevdL7wcW2+5+5knpfQ=; b=owGbwMvMwCXGf25diOft7jLG02pJDJkHVy5j3npot2jw3deyu12XHC6//abyG1t5oXRqYOX75 3EtnaxvOkpZGMS4GGTFFFn+7vnIeExuez5PYIIjzBxWJpAhDFycAjCRhwwMv1l++6lNqGzTe8T0 YJ8Is0u+DtPnBqFHCz9m5cg2Je8PXc7IsC8nd7XrcdEXM9QOG8VU8hxVU+TdHMR51mLNmhhz+5S pnAA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Use the TDH.SYS.DISABLE SEAMCALL, which disables the TDX module, reclaims all memory resources assigned to TDX, and clears any partial-write induced poison, to allow kexec and kdump on platforms with the partial write errata. On TDX-capable platforms with the partial write erratum, kexec has been disabled because the new kernel could hit a machine check reading a previously poisoned memory location. Later TDX modules support TDH.SYS.DISABLE, which disables the module and reclaims all TDX memory resources, allowing the new kernel to re-initialize TDX from scratch. This operation also clears the old memory, cleaning up any poison. Add tdx_sys_disable() to tdx_shutdown(), which is called in the syscore_shutdown path for kexec. This is done just before tdx_shutdown() disables VMX on all CPUs. For kdump, call tdx_sys_disable() in the crash path before x86_virt_emergency_disable_virtualization_cpu() does VMXOFF. Since this clears any poison on TDX-managed memory, remove the X86_BUG_TDX_PW_MCE check in machine_kexec() that blocked kexec on partial write errata platforms. Co-developed-by: Rick Edgecombe Signed-off-by: Rick Edgecombe Signed-off-by: Vishal Verma Acked-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) --- arch/x86/kernel/crash.c | 2 ++ arch/x86/kernel/machine_kexec_64.c | 16 ---------------- arch/x86/virt/vmx/tdx/tdx.c | 1 + 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c index cd796818d94d..623d4474631a 100644 --- a/arch/x86/kernel/crash.c +++ b/arch/x86/kernel/crash.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -112,6 +113,7 @@ void native_machine_crash_shutdown(struct pt_regs *regs) =20 crash_smp_send_stop(); =20 + tdx_sys_disable(); x86_virt_emergency_disable_virtualization_cpu(); =20 /* diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_k= exec_64.c index 0590d399d4f1..c3f4a389992d 100644 --- a/arch/x86/kernel/machine_kexec_64.c +++ b/arch/x86/kernel/machine_kexec_64.c @@ -347,22 +347,6 @@ int machine_kexec_prepare(struct kimage *image) unsigned long reloc_end =3D (unsigned long)__relocate_kernel_end; int result; =20 - /* - * Some early TDX-capable platforms have an erratum. A kernel - * partial write (a write transaction of less than cacheline - * lands at memory controller) to TDX private memory poisons that - * memory, and a subsequent read triggers a machine check. - * - * On those platforms the old kernel must reset TDX private - * memory before jumping to the new kernel otherwise the new - * kernel may see unexpected machine check. For simplicity - * just fail kexec/kdump on those platforms. - */ - if (boot_cpu_has_bug(X86_BUG_TDX_PW_MCE)) { - pr_info_once("Not allowed on platform with tdx_pw_mce bug\n"); - return -EOPNOTSUPP; - } - /* Setup the identity mapped 64bit page table */ result =3D init_pgtable(image, __pa(control_page)); if (result) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 3a76000dec7a..aaf22a87717a 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -252,6 +252,7 @@ static void tdx_shutdown_cpu(void *ign) =20 static void tdx_shutdown(void *ign) { + tdx_sys_disable(); on_each_cpu(tdx_shutdown_cpu, NULL, 1); } =20 --=20 2.53.0 From nobody Fri Apr 3 17:37:50 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AF683E7152; Mon, 23 Mar 2026 20:59:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774299573; cv=none; b=DjEBK4jQyKSS/CB+ztN3OwrhPw8dTcbrePXmC1JJBxDWf9JiiRzHi9R8NVxoXZB8Boti2PI89m4rI5mfxe2+bj1pYllI71GdWENTldzx1c0dZmohFV9MiHDnxYjjAFy117+aJ4Gg8hHOYm+FMiVERyhMpkSTfweIYEc6gFqGE6s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774299573; c=relaxed/simple; bh=xmYUcXvNPSne4xx5aF8gVsTVubD4qSP5Sa6svWKJhE8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NzJMmCNdsDbuK9d4jWAYEBfpr1xIX28Mpb06IwnWpdygHm805OpDjonATVTdEuGrbt8Fv+YlbXCwNsZYp5NGJsX6UXPLio0hAaCnVGdBtYyPqn70vMFTBFzU9FBHv5x9cTK/Ubyfh6ng2cpo8leP/FcTdiueLY5J3ha9DxF9JBo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JaAVlhMr; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JaAVlhMr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774299566; x=1805835566; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=xmYUcXvNPSne4xx5aF8gVsTVubD4qSP5Sa6svWKJhE8=; b=JaAVlhMreivDyuQiJH1MnUcU1/uxIDkjQ4BKqQJFRZcSl507xeTQjZEG BevyH7uAZvSW4UuVKDlcx65MkB3sw57as6dN2yH0fvoJPcBQi9ZLksLlL 8Hyob0K6gXegazpgNOaFQ1XJ0XdfUdRBp4vubHWGoYcX0vTQLIm/BN1RV cCxyskYcb5bE+UK37viW1stiFLqMQAXEz2wrc7iogktKfnzLhpKthcSjy CKpjNiSo/vO/sA00E5rNbmhGkXIjkQuaCMYVsiw4WNhxNgT5+XsqbTEbz SpsnyViSfnPhOW8otpFZdg1RawOeHIzht204DDytdthkOM1Ohv50MdZt9 Q==; X-CSE-ConnectionGUID: qy5FrGWoSISEgtB9ZVq7iQ== X-CSE-MsgGUID: 8uvvNEN3RvS6hQvw/dPzWw== X-IronPort-AV: E=McAfee;i="6800,10657,11738"; a="74491166" X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="74491166" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:25 -0700 X-CSE-ConnectionGUID: BjoZ1WcRSiudasIkKU8PuQ== X-CSE-MsgGUID: 7agm+4TxT0qVDZ+w/HTbzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,137,1770624000"; d="scan'208";a="224156879" Received: from vverma7-desk1.amr.corp.intel.com (HELO [192.168.1.200]) ([10.124.221.51]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 13:59:24 -0700 From: Vishal Verma Date: Mon, 23 Mar 2026 14:59:08 -0600 Subject: [PATCH v2 5/5] x86/virt/tdx: Remove kexec docs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-fuller_tdx_kexec_support-v2-5-87a36409e051@intel.com> References: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> In-Reply-To: <20260323-fuller_tdx_kexec_support-v2-0-87a36409e051@intel.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe , Sean Christopherson , Paolo Bonzini Cc: linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, Vishal Verma X-Mailer: b4 0.16-dev-8c19c X-Developer-Signature: v=1; a=openpgp-sha256; l=1264; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=/Bi8M4/fivZYl7NEWzkuzL9MCY3LYD9P0Q0j44q9A4c=; b=owGbwMvMwCXGf25diOft7jLG02pJDJkHVy4r2/5zadLeKYUaPJnfVu6Ye/FYAD+7/tULGzvKj 5wK+FlyuqOUhUGMi0FWTJHl756PjMfktufzBCY4wsxhZQIZwsDFKQATefSD4X/i3cI5b6+5mGS4 m7vtt5ljYfkvKN5RV77It0HH4PilrNUM/1PXdDB0xe3yuhk2bfF+2Y7gm8ZbBIKE906tqZtnbrY 5kxUA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF From: Rick Edgecombe Recent changes have removed the hard limitations for using kexec and TDX together. So remove the section in the TDX docs. Users on partial write erratums will need an updated TDX module to handle the rare edge cases. The docs do not currently provide any guidance on recommended TDX module versions, so don't keep a whole section around to document this interaction. Signed-off-by: Rick Edgecombe Signed-off-by: Vishal Verma Acked-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) --- Documentation/arch/x86/tdx.rst | 7 ------- 1 file changed, 7 deletions(-) diff --git a/Documentation/arch/x86/tdx.rst b/Documentation/arch/x86/tdx.rst index ff6b110291bc..1a3b5bac1021 100644 --- a/Documentation/arch/x86/tdx.rst +++ b/Documentation/arch/x86/tdx.rst @@ -138,13 +138,6 @@ If the platform has such erratum, the kernel prints ad= ditional message in machine check handler to tell user the machine check may be caused by kernel bug on TDX private memory. =20 -Kexec -~~~~~~~ - -Currently kexec doesn't work on the TDX platforms with the aforementioned -erratum. It fails when loading the kexec kernel image. Otherwise it -works normally. - Interaction vs S3 and deeper states ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ =20 --=20 2.53.0