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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50b36e34f8bsm108249661cf.15.2026.03.23.10.25.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 10:25:45 -0700 (PDT) From: Brian Masney Date: Mon, 23 Mar 2026 13:24:58 -0400 Subject: [PATCH v7 7/8] clk: divider: test: introduce additional test case showing v2 rate change + LCM parent Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-clk-scaling-v7-7-8e7193dc9405@redhat.com> References: <20260323-clk-scaling-v7-0-8e7193dc9405@redhat.com> In-Reply-To: <20260323-clk-scaling-v7-0-8e7193dc9405@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4963; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=xpGnRJHb7iFtNaWnVivX5OL5Ase55p/rrd+OZZm4p/o=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDIPlneVrBf/anbxvLrp4fWXtaXPbHPpk1uQ+983Mirm5 M6fyg4iHaUsDGJcDLJiiixLco0KIlJX2d67o8kCM4eVCWQIAxenAEykiZXhfyDPpICi5rtNFU/y ZG9++SojKlKuoV7fXash830X2+Jl4YwMe/MZr91KfrCH66DAQZY2iUOsJVdXXGVf+Gyd5I9shgO ebAA= X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Add a test case that uses the clk divider with the v2 rate negotiation logic, plus the Lowest Common Multiple (LCM) to calculate the optimal parent rate. The test ensures that the parent clk rate is set to a rate that's acceptable to both children, and the sibling clock is not affected. The test in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. child1 requests 32 MHz, and the tree ends up with the correct state: parent 96 MHz / \ child1 child2 32 MHz 24 MHz Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk-divider_test.c | 54 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c index 95a55835a29065fede0426f1c15ec158e8a703c1..a16c04d5d8a86952b42750d326f= 88754fbc91eb7 100644 --- a/drivers/clk/clk-divider_test.c +++ b/drivers/clk/clk-divider_test.c @@ -110,6 +110,18 @@ clk_rate_change_divider_test_lcm_ops_v1_params[] =3D { KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_lcm_ops_v1, clk_rate_change_divider_test_lcm_ops_v1_params, desc) =20 +static const struct clk_rate_change_divider_test_param +clk_rate_change_divider_test_regular_ops_v2_params[] =3D { + { + .desc =3D "regular_ops_v2", + .ops =3D &clk_dummy_div_ops, + .extra_child_flags =3D CLK_V2_RATE_NEGOTIATION, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_regular_ops_v2, + clk_rate_change_divider_test_regular_ops_v2_params, desc) + static int clk_rate_change_divider_test_init(struct kunit *test) { const struct clk_rate_change_divider_test_param *param =3D test->param_va= lue; @@ -196,6 +208,11 @@ static void clk_test_rate_change_divider_1(struct kuni= t *test) KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); } =20 +static inline bool __clk_has_v2_negotiation(struct clk *clk) +{ + return clk_hw_get_flags(__clk_get_hw(clk)) & CLK_V2_RATE_NEGOTIATION; +} + /* * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT * set and one requests a rate incompatible with the existing parent rate,= the @@ -265,6 +282,39 @@ static void clk_test_rate_change_divider_3_v1(struct k= unit *test) KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); } =20 +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is not affected, and maintains it's rate when the v2 rate + * negotiation logic is used. + */ +static void clk_test_rate_change_divider_4_v2(struct kunit *test) +{ + struct clk_rate_change_divider_context *ctx =3D test->priv; + int ret; + + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + KUNIT_ASSERT_TRUE(test, __clk_has_v2_negotiation(ctx->child1_clk)); + KUNIT_ASSERT_TRUE(test, __clk_has_v2_negotiation(ctx->child2_clk)); + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * With LCM-based parent + v2 rate changes, the parent should be at + * 96 MHz (LCM of 32 and 24), child1 at 32 MHz, and child2 at 24 MHz. + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 96 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 3); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 4); +} + static struct kunit_case clk_rate_change_divider_cases[] =3D { KUNIT_CASE_PARAM(clk_test_rate_change_divider_1, clk_rate_change_divider_test_regular_ops_gen_params), @@ -272,6 +322,10 @@ static struct kunit_case clk_rate_change_divider_cases= [] =3D { clk_rate_change_divider_test_regular_ops_gen_params), KUNIT_CASE_PARAM(clk_test_rate_change_divider_3_v1, clk_rate_change_divider_test_lcm_ops_v1_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_divider_1, + clk_rate_change_divider_test_regular_ops_v2_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_divider_4_v2, + clk_rate_change_divider_test_regular_ops_v2_gen_params), {} }; =20 --=20 2.53.0