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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50b36e34f8bsm108249661cf.15.2026.03.23.10.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 10:25:37 -0700 (PDT) From: Brian Masney Date: Mon, 23 Mar 2026 13:24:53 -0400 Subject: [PATCH v7 2/8] clk: divider: introduce divider kunit tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260323-clk-scaling-v7-2-8e7193dc9405@redhat.com> References: <20260323-clk-scaling-v7-0-8e7193dc9405@redhat.com> In-Reply-To: <20260323-clk-scaling-v7-0-8e7193dc9405@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10994; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=CgZwb7h0Lrx3Ro3dOuYbsmKBBaRIB98siIpf9VE69j8=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDIPlrdl1V2do+MlynX/s2RngMx7+USWYu/wVZoa1p/Xz GeXcFzYUcrCIMbFICumyLIk16ggInWV7b07miwwc1iZQIYwcHEKwER05jIyrH7LuG3SRmOn4DKX mMXL5CpOlRxO70u6vPk3/2Ph2b/4dzL8D0mMd+pwlP/9mCtylr+3Jk+2R4xo2sILC+3yhBarf3/ MAQA= X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Introduce some kunit tests for the generic clk-divider.c implementation. This test suite demonstrates the current behavior of how a clock can unknowingly change the rate of it's siblings. Some boards are unknowingly dependent on this behavior, and per discussions at the 2025 Linux Plumbers Conference in Tokyo, we can't break the existing behavior. So let's add kunit tests with the current behavior so that we can be made aware if that functionality changes in the future. The tests in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. For consistency with clk-fixed-rate_test.c and drivers/clk/clk-gate_test.c, the divider tests are setup as it's own separate kernel module. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/.kunitconfig | 1 + drivers/clk/Kconfig | 7 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-divider_test.c | 226 +++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 235 insertions(+) diff --git a/drivers/clk/.kunitconfig b/drivers/clk/.kunitconfig index 8a0ea41934a2100e1bb1521ce3ad490baec76ec2..ea05b9a28c8000c647c76c4adf8= 13da97c500ab6 100644 --- a/drivers/clk/.kunitconfig +++ b/drivers/clk/.kunitconfig @@ -4,6 +4,7 @@ CONFIG_OF=3Dy CONFIG_OF_OVERLAY=3Dy CONFIG_COMMON_CLK=3Dy CONFIG_CLK_KUNIT_TEST=3Dy +CONFIG_CLK_DIVIDER_KUNIT_TEST=3Dy CONFIG_CLK_FIXED_RATE_KUNIT_TEST=3Dy CONFIG_CLK_GATE_KUNIT_TEST=3Dy CONFIG_CLK_FD_KUNIT_TEST=3Dy diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 8cc300b90b5fd9fb38ce94fcb1098810c3f52c36..ba4af56949e39249652fc414eb2= 3b44aee1d37f5 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -550,6 +550,13 @@ config CLK_KUNIT_TEST help Kunit tests for the common clock framework. =20 +config CLK_DIVIDER_KUNIT_TEST + tristate "Basic divider clk type KUnit test" if !KUNIT_ALL_TESTS + depends on KUNIT && CLK_KUNIT_TEST + default KUNIT_ALL_TESTS + help + KUnit tests for the basic divider clk type. + config CLK_FIXED_RATE_KUNIT_TEST tristate "Basic fixed rate clk type KUnit test" if !KUNIT_ALL_TESTS depends on KUNIT diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f52cf3ac64fcce7e20f3fd91f837c5096375521a..f11d37cb09423b914d7653fa4c3= fa17370430aa7 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,6 +21,7 @@ clk-test-y :=3D clk_test.o \ kunit_clk_hw_get_dev_of_node.dtbo.o \ kunit_clk_parent_data_test.dtbo.o obj-$(CONFIG_COMMON_CLK) +=3D clk-divider.o +obj-$(CONFIG_CLK_DIVIDER_KUNIT_TEST) +=3D clk-divider_test.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-rate.o obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) +=3D clk-fixed-rate-test.o diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c new file mode 100644 index 0000000000000000000000000000000000000000..2a01b0201e9d919c36bb70eeb21= c9f4ae113254e --- /dev/null +++ b/drivers/clk/clk-divider_test.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Kunit tests for clk divider + */ +#include +#include +#include +#include + +#include +#include + +/* 4 ought to be enough for anybody */ +#define CLK_DUMMY_DIV_WIDTH 4 +#define CLK_DUMMY_DIV_FLAGS (CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLO= SEST) + +struct clk_dummy_div { + struct clk_hw hw; + unsigned int div; +}; + +static unsigned long clk_dummy_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_dummy_div *div =3D container_of(hw, struct clk_dummy_div, hw); + + return divider_recalc_rate(hw, parent_rate, div->div, NULL, + CLK_DUMMY_DIV_FLAGS, CLK_DUMMY_DIV_WIDTH); +} + +static int clk_dummy_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && req->best_parent_rat= e < req->rate) + return -EINVAL; + + return divider_determine_rate(hw, req, NULL, CLK_DUMMY_DIV_WIDTH, CLK_DUM= MY_DIV_FLAGS); +} + +static int clk_dummy_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_dummy_div *div =3D container_of(hw, struct clk_dummy_div, hw); + + div->div =3D divider_get_val(rate, parent_rate, NULL, CLK_DUMMY_DIV_WIDTH, + CLK_DUMMY_DIV_FLAGS); + + return 0; +} + +static const struct clk_ops clk_dummy_div_ops =3D { + .recalc_rate =3D clk_dummy_div_recalc_rate, + .determine_rate =3D clk_dummy_div_determine_rate, + .set_rate =3D clk_dummy_div_set_rate, +}; + +struct clk_rate_change_divider_context { + struct clk_dummy_context parent; + struct clk_dummy_div child1, child2; + struct clk *parent_clk, *child1_clk, *child2_clk; +}; + +struct clk_rate_change_divider_test_param { + const char *desc; + const struct clk_ops *ops; + unsigned int extra_child_flags; +}; + +static const struct clk_rate_change_divider_test_param +clk_rate_change_divider_test_regular_ops_params[] =3D { + { + .desc =3D "regular_ops", + .ops =3D &clk_dummy_div_ops, + .extra_child_flags =3D 0, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_regular_ops, + clk_rate_change_divider_test_regular_ops_params, desc) + +static int clk_rate_change_divider_test_init(struct kunit *test) +{ + const struct clk_rate_change_divider_test_param *param =3D test->param_va= lue; + struct clk_rate_change_divider_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + test->priv =3D ctx; + + ctx->parent.hw.init =3D CLK_HW_INIT_NO_PARENT("parent", &clk_dummy_rate_o= ps, 0); + ctx->parent.rate =3D 24 * HZ_PER_MHZ; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->parent.hw); + if (ret) + return ret; + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", &ctx->parent.hw, + param->ops, + CLK_SET_RATE_PARENT | param->extra_child_flags); + ctx->child1.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ret; + + ctx->child2.hw.init =3D CLK_HW_INIT_HW("child2", &ctx->parent.hw, + param->ops, + CLK_SET_RATE_PARENT | param->extra_child_flags); + ctx->child2.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child2.hw); + if (ret) + return ret; + + ctx->parent_clk =3D clk_hw_get_clk(&ctx->parent.hw, NULL); + ret =3D clk_prepare_enable(ctx->parent_clk); + if (ret) + return ret; + + ctx->child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + clk_prepare_enable(ctx->child1_clk); + if (ret) + return ret; + + ctx->child2_clk =3D clk_hw_get_clk(&ctx->child2.hw, NULL); + clk_prepare_enable(ctx->child2_clk); + if (ret) + return ret; + + return 0; +} + +static void clk_rate_change_divider_test_exit(struct kunit *test) +{ + struct clk_rate_change_divider_context *ctx =3D test->priv; + + clk_put(ctx->parent_clk); + clk_put(ctx->child1_clk); + clk_put(ctx->child2_clk); +} + +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT set + * and one requests a rate compatible with the existing parent rate, the p= arent and + * sibling rates are not affected. + */ +static void clk_test_rate_change_divider_1(struct kunit *test) +{ + struct clk_rate_change_divider_context *ctx =3D test->priv; + int ret; + + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + + ret =3D clk_set_rate(ctx->child1_clk, 6 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 6 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 4); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); +} + +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is also affected. This preserves existing behavior in the = clk + * core that some drivers may be unknowingly dependent on. + */ +static void clk_test_rate_change_divider_2_v1(struct kunit *test) +{ + struct clk_rate_change_divider_context *ctx =3D test->priv; + int ret; + + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * The last sibling rate change is the one that was successful, and + * wins. The parent, and two children are all changed to 32 MHz. This + * keeps the long-standing behavior of the clk core that some drivers + * may be unknowingly dependent on. + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); +} + +static struct kunit_case clk_rate_change_divider_cases[] =3D { + KUNIT_CASE_PARAM(clk_test_rate_change_divider_1, + clk_rate_change_divider_test_regular_ops_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_divider_2_v1, + clk_rate_change_divider_test_regular_ops_gen_params), + {} +}; + +/* + * Test suite that creates a parent with two divider-only children, and + * documents the behavior of what happens to the sibling clock when one ch= ild + * changes its rate. + */ +static struct kunit_suite clk_rate_change_divider_test_suite =3D { + .name =3D "clk-rate-change-divider", + .init =3D clk_rate_change_divider_test_init, + .exit =3D clk_rate_change_divider_test_exit, + .test_cases =3D clk_rate_change_divider_cases, +}; + +kunit_test_suites( + &clk_rate_change_divider_test_suite, +); + +MODULE_DESCRIPTION("Kunit tests for clk divider"); +MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING"); +MODULE_LICENSE("GPL"); --=20 2.53.0