From nobody Fri Apr 3 23:43:48 2026 Received: from hall.aurel32.net (hall.aurel32.net [195.154.119.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2990737F74D; Sun, 22 Mar 2026 20:34:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.154.119.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774211656; cv=none; b=dnCQkPMaQQUorScfHPjEbkeCUx1GeAXVYOGFYTZSmWgq/Al2yWTX8cIILzUdp3/stKxUOUJsjo7QTfUDdUbjYAOvx49vDKldFtTxdERYMNNZmdBQLq1i9EzYMZIJOQuuj3U2WwDzYvxz8MmYOHTdZCfxNQTqfhugFay6rl4nADU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774211656; c=relaxed/simple; bh=hXtOE/S/BD2vKjhdLlu+s5UL9v4tk7IWjKSM57AF9c8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BCaNeYJ90TgrIBmQPgAKrPUiuPuxPdS4g1+x3B0xEnwGKC03k1hdJUTDJGTrnRMklBAIYm+xv/KJWXrbiC92Z33HS+KDHLU1x2RV6mrVP6UUCY9DBLjYBaegkVicKHhRsstcfPhBMvPCDO5pnE/KVXLHQqNnqPE0kUnluy9C5PY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net; spf=pass smtp.mailfrom=aurel32.net; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b=z2FEIz/a; arc=none smtp.client-ip=195.154.119.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aurel32.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b="z2FEIz/a" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Content-Type:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=h2XgC87QhZKmEL4LkPO3nDr8p/ZxtRxNQZuSqKpeYJM=; b=z2FEIz/aZkvVPsY+4chklYQSqG 1zReuu4agcLAYpOn3ZCy5IuZfOtmhvYyPv8UUUb+JZK0Zk5cBfuwczkp9pF5C5I/ARmp0n+zvRVR/ CeeMZOLEI5svyOAqG1/z9B8ULt7LUMykz41/+MRiMJTJ+M8liim3bZAzrgQLnLVOcyVfWs/WdofEv c2FVVC5YOl5xOg1n84N8holWP03pE+9an5satwv8n/sNkiSHXqtfuOSH+QkEzjzTam1ELTnmoXYs+ 7bs9pH+eENW1clTkVdq7Z6QExVIvrd/cyyqxCOf8lTVLIp3SeMcVsUxZndipaDMdcvRume/MKp1z1 eN/lSsgA==; Received: from authenticated user by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w4PUz-0000000AsfJ-2PHS; Sun, 22 Mar 2026 21:34:13 +0100 From: Aurelien Jarno To: linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Aurelien Jarno , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-riscv@lists.infradead.org (open list:RISC-V SPACEMIT SoC Support), spacemit@lists.linux.dev (open list:RISC-V SPACEMIT SoC Support) Subject: [PATCH 6/6] riscv: dts: spacemit: enable PCIe ports on Milk-V Jupiter Date: Sun, 22 Mar 2026 21:28:37 +0100 Message-ID: <20260322203356.2206927-7-aurelien@aurel32.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260322203356.2206927-1-aurelien@aurel32.net> References: <20260322203356.2206927-1-aurelien@aurel32.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the two PCIe controller along with and their associated PHY. They are routed to the M.2 M-key connector and to the the PCIe x8 slot. Add an always-on regulator sourcing 3.3V from the DC-IN input, to power the PCIe ports. Signed-off-by: Aurelien Jarno Reviewed-by: Javier Martinez Canillas --- .../boot/dts/spacemit/k1-milkv-jupiter.dts | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv= /boot/dts/spacemit/k1-milkv-jupiter.dts index 4432f8287eb5c..d59dea4149ae7 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -40,6 +40,16 @@ led2 { }; }; =20 + pcie_vcc_3v3: regulator-pcie-vcc3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie_vcc3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply =3D <®_dc_in>; + }; + reg_dc_in: regulator-dc-in-12v { compatible =3D "regulator-fixed"; regulator-name =3D "dc_in_12v"; @@ -291,6 +301,38 @@ dldo7 { }; }; =20 +&pcie1_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_3_cfg>; + status =3D "okay"; +}; + +&pcie1_port { + phys =3D <&pcie1_phy>; + vpcie3v3-supply =3D <&pcie_vcc_3v3>; +}; + +&pcie1 { + vpcie3v3-supply =3D <&pcie_vcc_3v3>; + status =3D "okay"; +}; + +&pcie2_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_4_cfg>; + status =3D "okay"; +}; + +&pcie2_port { + phys =3D <&pcie2_phy>; + vpcie3v3-supply =3D <&pcie_vcc_3v3>; +}; + +&pcie2 { + vpcie3v3-supply =3D <&pcie_vcc_3v3>; + status =3D "okay"; +}; + &qspi { pinctrl-names =3D "default"; pinctrl-0 =3D <&qspi_cfg>; --=20 2.51.0