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[96.255.20.138]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50b36e35086sm59688651cf.18.2026.03.22.06.16.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 06:16:44 -0700 (PDT) From: Gregory Price To: linux-cxl@vger.kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com Subject: [PATCH v4 1/3] cxl/core/region: move pmem region driver logic into region_pmem.c Date: Sun, 22 Mar 2026 09:16:36 -0400 Message-ID: <20260322131638.3636725-2-gourry@gourry.net> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260322131638.3636725-1-gourry@gourry.net> References: <20260322131638.3636725-1-gourry@gourry.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" core/region.c is overloaded with per-region control logic (pmem, dax, sysram, etc). Move the pmem region driver logic from region.c into region_pmem.c make it clear that this code only applies to pmem regions. No functional changes. Signed-off-by: Gregory Price Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron --- drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 1 + drivers/cxl/core/region.c | 184 -------------------------------- drivers/cxl/core/region_pmem.c | 189 +++++++++++++++++++++++++++++++++ 4 files changed, 191 insertions(+), 184 deletions(-) create mode 100644 drivers/cxl/core/region_pmem.c diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index a639a9499972..d1484a0e5eb4 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -16,6 +16,7 @@ cxl_core-y +=3D pmu.o cxl_core-y +=3D cdat.o cxl_core-$(CONFIG_TRACING) +=3D trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D region.o +cxl_core-$(CONFIG_CXL_REGION) +=3D region_pmem.o cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 5539e941782f..ef03966eeabd 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -50,6 +50,7 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port); struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 d= pa); u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, u64 dpa); +int devm_cxl_add_pmem_region(struct cxl_region *cxlr); =20 #else static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index f24b7e754727..72aee1408efb 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -2781,46 +2781,6 @@ static ssize_t delete_region_store(struct device *de= v, } DEVICE_ATTR_WO(delete_region); =20 -static void cxl_pmem_region_release(struct device *dev) -{ - struct cxl_pmem_region *cxlr_pmem =3D to_cxl_pmem_region(dev); - int i; - - for (i =3D 0; i < cxlr_pmem->nr_mappings; i++) { - struct cxl_memdev *cxlmd =3D cxlr_pmem->mapping[i].cxlmd; - - put_device(&cxlmd->dev); - } - - kfree(cxlr_pmem); -} - -static const struct attribute_group *cxl_pmem_region_attribute_groups[] = =3D { - &cxl_base_attribute_group, - NULL, -}; - -const struct device_type cxl_pmem_region_type =3D { - .name =3D "cxl_pmem_region", - .release =3D cxl_pmem_region_release, - .groups =3D cxl_pmem_region_attribute_groups, -}; - -bool is_cxl_pmem_region(struct device *dev) -{ - return dev->type =3D=3D &cxl_pmem_region_type; -} -EXPORT_SYMBOL_NS_GPL(is_cxl_pmem_region, "CXL"); - -struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) -{ - if (dev_WARN_ONCE(dev, !is_cxl_pmem_region(dev), - "not a cxl_pmem_region device\n")) - return NULL; - return container_of(dev, struct cxl_pmem_region, dev); -} -EXPORT_SYMBOL_NS_GPL(to_cxl_pmem_region, "CXL"); - struct cxl_poison_context { struct cxl_port *port; int part; @@ -3476,64 +3436,6 @@ static int region_offset_to_dpa_result(struct cxl_re= gion *cxlr, u64 offset, return -ENXIO; } =20 -static struct lock_class_key cxl_pmem_region_key; - -static int cxl_pmem_region_alloc(struct cxl_region *cxlr) -{ - struct cxl_region_params *p =3D &cxlr->params; - struct cxl_nvdimm_bridge *cxl_nvb; - struct device *dev; - int i; - - guard(rwsem_read)(&cxl_rwsem.region); - if (p->state !=3D CXL_CONFIG_COMMIT) - return -ENXIO; - - struct cxl_pmem_region *cxlr_pmem __free(kfree) =3D - kzalloc_flex(*cxlr_pmem, mapping, p->nr_targets); - if (!cxlr_pmem) - return -ENOMEM; - - cxlr_pmem->hpa_range.start =3D p->res->start; - cxlr_pmem->hpa_range.end =3D p->res->end; - - /* Snapshot the region configuration underneath the cxl_rwsem.region */ - cxlr_pmem->nr_mappings =3D p->nr_targets; - for (i =3D 0; i < p->nr_targets; i++) { - struct cxl_endpoint_decoder *cxled =3D p->targets[i]; - struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); - struct cxl_pmem_region_mapping *m =3D &cxlr_pmem->mapping[i]; - - /* - * Regions never span CXL root devices, so by definition the - * bridge for one device is the same for all. - */ - if (i =3D=3D 0) { - cxl_nvb =3D cxl_find_nvdimm_bridge(cxlmd->endpoint); - if (!cxl_nvb) - return -ENODEV; - cxlr->cxl_nvb =3D cxl_nvb; - } - m->cxlmd =3D cxlmd; - get_device(&cxlmd->dev); - m->start =3D cxled->dpa_res->start; - m->size =3D resource_size(cxled->dpa_res); - m->position =3D i; - } - - dev =3D &cxlr_pmem->dev; - device_initialize(dev); - lockdep_set_class(&dev->mutex, &cxl_pmem_region_key); - device_set_pm_not_required(dev); - dev->parent =3D &cxlr->dev; - dev->bus =3D &cxl_bus_type; - dev->type =3D &cxl_pmem_region_type; - cxlr_pmem->cxlr =3D cxlr; - cxlr->cxlr_pmem =3D no_free_ptr(cxlr_pmem); - - return 0; -} - static void cxl_dax_region_release(struct device *dev) { struct cxl_dax_region *cxlr_dax =3D to_cxl_dax_region(dev); @@ -3597,92 +3499,6 @@ static struct cxl_dax_region *cxl_dax_region_alloc(s= truct cxl_region *cxlr) return cxlr_dax; } =20 -static void cxlr_pmem_unregister(void *_cxlr_pmem) -{ - struct cxl_pmem_region *cxlr_pmem =3D _cxlr_pmem; - struct cxl_region *cxlr =3D cxlr_pmem->cxlr; - struct cxl_nvdimm_bridge *cxl_nvb =3D cxlr->cxl_nvb; - - /* - * Either the bridge is in ->remove() context under the device_lock(), - * or cxlr_release_nvdimm() is cancelling the bridge's release action - * for @cxlr_pmem and doing it itself (while manually holding the bridge - * lock). - */ - device_lock_assert(&cxl_nvb->dev); - cxlr->cxlr_pmem =3D NULL; - cxlr_pmem->cxlr =3D NULL; - device_unregister(&cxlr_pmem->dev); -} - -static void cxlr_release_nvdimm(void *_cxlr) -{ - struct cxl_region *cxlr =3D _cxlr; - struct cxl_nvdimm_bridge *cxl_nvb =3D cxlr->cxl_nvb; - - scoped_guard(device, &cxl_nvb->dev) { - if (cxlr->cxlr_pmem) - devm_release_action(&cxl_nvb->dev, cxlr_pmem_unregister, - cxlr->cxlr_pmem); - } - cxlr->cxl_nvb =3D NULL; - put_device(&cxl_nvb->dev); -} - -/** - * devm_cxl_add_pmem_region() - add a cxl_region-to-nd_region bridge - * @cxlr: parent CXL region for this pmem region bridge device - * - * Return: 0 on success negative error code on failure. - */ -static int devm_cxl_add_pmem_region(struct cxl_region *cxlr) -{ - struct cxl_pmem_region *cxlr_pmem; - struct cxl_nvdimm_bridge *cxl_nvb; - struct device *dev; - int rc; - - rc =3D cxl_pmem_region_alloc(cxlr); - if (rc) - return rc; - cxlr_pmem =3D cxlr->cxlr_pmem; - cxl_nvb =3D cxlr->cxl_nvb; - - dev =3D &cxlr_pmem->dev; - rc =3D dev_set_name(dev, "pmem_region%d", cxlr->id); - if (rc) - goto err; - - rc =3D device_add(dev); - if (rc) - goto err; - - dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent), - dev_name(dev)); - - scoped_guard(device, &cxl_nvb->dev) { - if (cxl_nvb->dev.driver) - rc =3D devm_add_action_or_reset(&cxl_nvb->dev, - cxlr_pmem_unregister, - cxlr_pmem); - else - rc =3D -ENXIO; - } - - if (rc) - goto err_bridge; - - /* @cxlr carries a reference on @cxl_nvb until cxlr_release_nvdimm */ - return devm_add_action_or_reset(&cxlr->dev, cxlr_release_nvdimm, cxlr); - -err: - put_device(dev); -err_bridge: - put_device(&cxl_nvb->dev); - cxlr->cxl_nvb =3D NULL; - return rc; -} - static void cxlr_dax_unregister(void *_cxlr_dax) { struct cxl_dax_region *cxlr_dax =3D _cxlr_dax; diff --git a/drivers/cxl/core/region_pmem.c b/drivers/cxl/core/region_pmem.c new file mode 100644 index 000000000000..138c373a5700 --- /dev/null +++ b/drivers/cxl/core/region_pmem.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2022 Intel Corporation. All rights reserved. */ +#include +#include +#include +#include +#include "core.h" + +static void cxl_pmem_region_release(struct device *dev) +{ + struct cxl_pmem_region *cxlr_pmem =3D to_cxl_pmem_region(dev); + int i; + + for (i =3D 0; i < cxlr_pmem->nr_mappings; i++) { + struct cxl_memdev *cxlmd =3D cxlr_pmem->mapping[i].cxlmd; + + put_device(&cxlmd->dev); + } + + kfree(cxlr_pmem); +} + +static const struct attribute_group *cxl_pmem_region_attribute_groups[] = =3D { + &cxl_base_attribute_group, + NULL +}; + +const struct device_type cxl_pmem_region_type =3D { + .name =3D "cxl_pmem_region", + .release =3D cxl_pmem_region_release, + .groups =3D cxl_pmem_region_attribute_groups, +}; +bool is_cxl_pmem_region(struct device *dev) +{ + return dev->type =3D=3D &cxl_pmem_region_type; +} +EXPORT_SYMBOL_NS_GPL(is_cxl_pmem_region, "CXL"); + +struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) +{ + if (dev_WARN_ONCE(dev, !is_cxl_pmem_region(dev), + "not a cxl_pmem_region device\n")) + return NULL; + return container_of(dev, struct cxl_pmem_region, dev); +} +EXPORT_SYMBOL_NS_GPL(to_cxl_pmem_region, "CXL"); +static struct lock_class_key cxl_pmem_region_key; + +static int cxl_pmem_region_alloc(struct cxl_region *cxlr) +{ + struct cxl_region_params *p =3D &cxlr->params; + struct cxl_nvdimm_bridge *cxl_nvb; + struct device *dev; + int i; + + guard(rwsem_read)(&cxl_rwsem.region); + if (p->state !=3D CXL_CONFIG_COMMIT) + return -ENXIO; + + struct cxl_pmem_region *cxlr_pmem __free(kfree) =3D + kzalloc_flex(*cxlr_pmem, mapping, p->nr_targets); + if (!cxlr_pmem) + return -ENOMEM; + + cxlr_pmem->hpa_range.start =3D p->res->start; + cxlr_pmem->hpa_range.end =3D p->res->end; + + /* Snapshot the region configuration underneath the cxl_rwsem.region */ + cxlr_pmem->nr_mappings =3D p->nr_targets; + for (i =3D 0; i < p->nr_targets; i++) { + struct cxl_endpoint_decoder *cxled =3D p->targets[i]; + struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); + struct cxl_pmem_region_mapping *m =3D &cxlr_pmem->mapping[i]; + + /* + * Regions never span CXL root devices, so by definition the + * bridge for one device is the same for all. + */ + if (i =3D=3D 0) { + cxl_nvb =3D cxl_find_nvdimm_bridge(cxlmd->endpoint); + if (!cxl_nvb) + return -ENODEV; + cxlr->cxl_nvb =3D cxl_nvb; + } + m->cxlmd =3D cxlmd; + get_device(&cxlmd->dev); + m->start =3D cxled->dpa_res->start; + m->size =3D resource_size(cxled->dpa_res); + m->position =3D i; + } + + dev =3D &cxlr_pmem->dev; + device_initialize(dev); + lockdep_set_class(&dev->mutex, &cxl_pmem_region_key); + device_set_pm_not_required(dev); + dev->parent =3D &cxlr->dev; + dev->bus =3D &cxl_bus_type; + dev->type =3D &cxl_pmem_region_type; + cxlr_pmem->cxlr =3D cxlr; + cxlr->cxlr_pmem =3D no_free_ptr(cxlr_pmem); + + return 0; +} + +static void cxlr_pmem_unregister(void *_cxlr_pmem) +{ + struct cxl_pmem_region *cxlr_pmem =3D _cxlr_pmem; + struct cxl_region *cxlr =3D cxlr_pmem->cxlr; + struct cxl_nvdimm_bridge *cxl_nvb =3D cxlr->cxl_nvb; + + /* + * Either the bridge is in ->remove() context under the device_lock(), + * or cxlr_release_nvdimm() is cancelling the bridge's release action + * for @cxlr_pmem and doing it itself (while manually holding the bridge + * lock). + */ + device_lock_assert(&cxl_nvb->dev); + cxlr->cxlr_pmem =3D NULL; + cxlr_pmem->cxlr =3D NULL; + device_unregister(&cxlr_pmem->dev); +} + +static void cxlr_release_nvdimm(void *_cxlr) +{ + struct cxl_region *cxlr =3D _cxlr; + struct cxl_nvdimm_bridge *cxl_nvb =3D cxlr->cxl_nvb; + + scoped_guard(device, &cxl_nvb->dev) { + if (cxlr->cxlr_pmem) + devm_release_action(&cxl_nvb->dev, cxlr_pmem_unregister, + cxlr->cxlr_pmem); + } + cxlr->cxl_nvb =3D NULL; + put_device(&cxl_nvb->dev); +} + +/** + * devm_cxl_add_pmem_region() - add a cxl_region-to-nd_region bridge + * @cxlr: parent CXL region for this pmem region bridge device + * + * Return: 0 on success negative error code on failure. + */ +int devm_cxl_add_pmem_region(struct cxl_region *cxlr) +{ + struct cxl_pmem_region *cxlr_pmem; + struct cxl_nvdimm_bridge *cxl_nvb; + struct device *dev; + int rc; + + rc =3D cxl_pmem_region_alloc(cxlr); + if (rc) + return rc; + cxlr_pmem =3D cxlr->cxlr_pmem; + cxl_nvb =3D cxlr->cxl_nvb; + + dev =3D &cxlr_pmem->dev; + rc =3D dev_set_name(dev, "pmem_region%d", cxlr->id); + if (rc) + goto err; + + rc =3D device_add(dev); + if (rc) + goto err; + + dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent), + dev_name(dev)); + + scoped_guard(device, &cxl_nvb->dev) { + if (cxl_nvb->dev.driver) + rc =3D devm_add_action_or_reset(&cxl_nvb->dev, + cxlr_pmem_unregister, + cxlr_pmem); + else + rc =3D -ENXIO; + } + + if (rc) + goto err_bridge; + + /* @cxlr carries a reference on @cxl_nvb until cxlr_release_nvdimm */ + return devm_add_action_or_reset(&cxlr->dev, cxlr_release_nvdimm, cxlr); + +err: + put_device(dev); +err_bridge: + put_device(&cxl_nvb->dev); + cxlr->cxl_nvb =3D NULL; + return rc; +} --=20 2.53.0 From nobody Fri Apr 3 22:50:16 2026 Received: from mail-qt1-f174.google.com (mail-qt1-f174.google.com [209.85.160.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FD2132BF41 for ; Sun, 22 Mar 2026 13:16:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[96.255.20.138]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50b36e35086sm59688651cf.18.2026.03.22.06.16.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 06:16:46 -0700 (PDT) From: Gregory Price To: linux-cxl@vger.kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com Subject: [PATCH v4 2/3] cxl/core/region: move dax region device logic into region_dax.c Date: Sun, 22 Mar 2026 09:16:37 -0400 Message-ID: <20260322131638.3636725-3-gourry@gourry.net> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260322131638.3636725-1-gourry@gourry.net> References: <20260322131638.3636725-1-gourry@gourry.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" core/region.c is overloaded with per-region control logic (pmem, dax, sysram, etc). Move the CXL DAX region device infrastructure from region.c into a new region_dax.c file. This will also allow us to add additional dax-driver integration paths that don't further dirty the core region.c logic. No functional changes. Signed-off-by: Gregory Price Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron --- drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 1 + drivers/cxl/core/region.c | 99 ------------------------------ drivers/cxl/core/region_dax.c | 109 ++++++++++++++++++++++++++++++++++ 4 files changed, 111 insertions(+), 99 deletions(-) create mode 100644 drivers/cxl/core/region_dax.c diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index d1484a0e5eb4..d3ec8aea64c5 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -16,6 +16,7 @@ cxl_core-y +=3D pmu.o cxl_core-y +=3D cdat.o cxl_core-$(CONFIG_TRACING) +=3D trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D region.o +cxl_core-$(CONFIG_CXL_REGION) +=3D region_dax.o cxl_core-$(CONFIG_CXL_REGION) +=3D region_pmem.o cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index ef03966eeabd..82ca3a476708 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -50,6 +50,7 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port); struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 d= pa); u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, u64 dpa); +int devm_cxl_add_dax_region(struct cxl_region *cxlr); int devm_cxl_add_pmem_region(struct cxl_region *cxlr); =20 #else diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 72aee1408efb..6a2ef3475764 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3436,105 +3436,6 @@ static int region_offset_to_dpa_result(struct cxl_r= egion *cxlr, u64 offset, return -ENXIO; } =20 -static void cxl_dax_region_release(struct device *dev) -{ - struct cxl_dax_region *cxlr_dax =3D to_cxl_dax_region(dev); - - kfree(cxlr_dax); -} - -static const struct attribute_group *cxl_dax_region_attribute_groups[] =3D= { - &cxl_base_attribute_group, - NULL, -}; - -const struct device_type cxl_dax_region_type =3D { - .name =3D "cxl_dax_region", - .release =3D cxl_dax_region_release, - .groups =3D cxl_dax_region_attribute_groups, -}; - -static bool is_cxl_dax_region(struct device *dev) -{ - return dev->type =3D=3D &cxl_dax_region_type; -} - -struct cxl_dax_region *to_cxl_dax_region(struct device *dev) -{ - if (dev_WARN_ONCE(dev, !is_cxl_dax_region(dev), - "not a cxl_dax_region device\n")) - return NULL; - return container_of(dev, struct cxl_dax_region, dev); -} -EXPORT_SYMBOL_NS_GPL(to_cxl_dax_region, "CXL"); - -static struct lock_class_key cxl_dax_region_key; - -static struct cxl_dax_region *cxl_dax_region_alloc(struct cxl_region *cxlr) -{ - struct cxl_region_params *p =3D &cxlr->params; - struct cxl_dax_region *cxlr_dax; - struct device *dev; - - guard(rwsem_read)(&cxl_rwsem.region); - if (p->state !=3D CXL_CONFIG_COMMIT) - return ERR_PTR(-ENXIO); - - cxlr_dax =3D kzalloc_obj(*cxlr_dax); - if (!cxlr_dax) - return ERR_PTR(-ENOMEM); - - cxlr_dax->hpa_range.start =3D p->res->start; - cxlr_dax->hpa_range.end =3D p->res->end; - - dev =3D &cxlr_dax->dev; - cxlr_dax->cxlr =3D cxlr; - device_initialize(dev); - lockdep_set_class(&dev->mutex, &cxl_dax_region_key); - device_set_pm_not_required(dev); - dev->parent =3D &cxlr->dev; - dev->bus =3D &cxl_bus_type; - dev->type =3D &cxl_dax_region_type; - - return cxlr_dax; -} - -static void cxlr_dax_unregister(void *_cxlr_dax) -{ - struct cxl_dax_region *cxlr_dax =3D _cxlr_dax; - - device_unregister(&cxlr_dax->dev); -} - -static int devm_cxl_add_dax_region(struct cxl_region *cxlr) -{ - struct cxl_dax_region *cxlr_dax; - struct device *dev; - int rc; - - cxlr_dax =3D cxl_dax_region_alloc(cxlr); - if (IS_ERR(cxlr_dax)) - return PTR_ERR(cxlr_dax); - - dev =3D &cxlr_dax->dev; - rc =3D dev_set_name(dev, "dax_region%d", cxlr->id); - if (rc) - goto err; - - rc =3D device_add(dev); - if (rc) - goto err; - - dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent), - dev_name(dev)); - - return devm_add_action_or_reset(&cxlr->dev, cxlr_dax_unregister, - cxlr_dax); -err: - put_device(dev); - return rc; -} - static int match_root_decoder(struct device *dev, const void *data) { const struct range *r1, *r2 =3D data; diff --git a/drivers/cxl/core/region_dax.c b/drivers/cxl/core/region_dax.c new file mode 100644 index 000000000000..fe367759ac69 --- /dev/null +++ b/drivers/cxl/core/region_dax.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * Copyright(c) 2026 Meta Technologies Inc. All rights reserved. + */ +#include +#include +#include +#include +#include "core.h" + +static void cxl_dax_region_release(struct device *dev) +{ + struct cxl_dax_region *cxlr_dax =3D to_cxl_dax_region(dev); + + kfree(cxlr_dax); +} + +static const struct attribute_group *cxl_dax_region_attribute_groups[] =3D= { + &cxl_base_attribute_group, + NULL +}; + +const struct device_type cxl_dax_region_type =3D { + .name =3D "cxl_dax_region", + .release =3D cxl_dax_region_release, + .groups =3D cxl_dax_region_attribute_groups, +}; + +static bool is_cxl_dax_region(struct device *dev) +{ + return dev->type =3D=3D &cxl_dax_region_type; +} + +struct cxl_dax_region *to_cxl_dax_region(struct device *dev) +{ + if (dev_WARN_ONCE(dev, !is_cxl_dax_region(dev), + "not a cxl_dax_region device\n")) + return NULL; + return container_of(dev, struct cxl_dax_region, dev); +} +EXPORT_SYMBOL_NS_GPL(to_cxl_dax_region, "CXL"); + +static struct lock_class_key cxl_dax_region_key; + +static struct cxl_dax_region *cxl_dax_region_alloc(struct cxl_region *cxlr) +{ + struct cxl_region_params *p =3D &cxlr->params; + struct cxl_dax_region *cxlr_dax; + struct device *dev; + + guard(rwsem_read)(&cxl_rwsem.region); + if (p->state !=3D CXL_CONFIG_COMMIT) + return ERR_PTR(-ENXIO); + + cxlr_dax =3D kzalloc_obj(*cxlr_dax); + if (!cxlr_dax) + return ERR_PTR(-ENOMEM); + + cxlr_dax->hpa_range.start =3D p->res->start; + cxlr_dax->hpa_range.end =3D p->res->end; + + dev =3D &cxlr_dax->dev; + cxlr_dax->cxlr =3D cxlr; + device_initialize(dev); + lockdep_set_class(&dev->mutex, &cxl_dax_region_key); + device_set_pm_not_required(dev); + dev->parent =3D &cxlr->dev; + dev->bus =3D &cxl_bus_type; + dev->type =3D &cxl_dax_region_type; + + return cxlr_dax; +} + +static void cxlr_dax_unregister(void *_cxlr_dax) +{ + struct cxl_dax_region *cxlr_dax =3D _cxlr_dax; + + device_unregister(&cxlr_dax->dev); +} + +int devm_cxl_add_dax_region(struct cxl_region *cxlr) +{ + struct cxl_dax_region *cxlr_dax; + struct device *dev; + int rc; + + cxlr_dax =3D cxl_dax_region_alloc(cxlr); + if (IS_ERR(cxlr_dax)) + return PTR_ERR(cxlr_dax); + + dev =3D &cxlr_dax->dev; + rc =3D dev_set_name(dev, "dax_region%d", cxlr->id); + if (rc) + goto err; + + rc =3D device_add(dev); + if (rc) + goto err; + + dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent), + dev_name(dev)); + + return devm_add_action_or_reset(&cxlr->dev, cxlr_dax_unregister, + cxlr_dax); +err: + put_device(dev); + return rc; +} --=20 2.53.0 From nobody Fri Apr 3 22:50:16 2026 Received: from mail-qt1-f178.google.com (mail-qt1-f178.google.com [209.85.160.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09F2032F76D for ; Sun, 22 Mar 2026 13:16:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774185412; cv=none; b=ss4gZ5OZN1SpBy5Gc1WsAtf6M16B3F8VabXpr9mHcc9XwHP0GRm3Kr0MxMaKNzh9P3dvnlA+pMnls6VslirYys6yDEUDqqlor+yiC/3DaKBtbGXAo3Kdw0J6rrr/a/Ibz3USzbzQG9efvkpoSIlVr24SEyWvFzeR7Ehr8nWA2dk= ARC-Message-Signature: i=1; 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[96.255.20.138]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50b36e35086sm59688651cf.18.2026.03.22.06.16.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 06:16:49 -0700 (PDT) From: Gregory Price To: linux-cxl@vger.kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com Subject: [PATCH v4 3/3] cxl/core: use cleanup.h for devm_cxl_add_dax_region Date: Sun, 22 Mar 2026 09:16:38 -0400 Message-ID: <20260322131638.3636725-4-gourry@gourry.net> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260322131638.3636725-1-gourry@gourry.net> References: <20260322131638.3636725-1-gourry@gourry.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Cleanup the gotos in the function. No functional change. Signed-off-by: Gregory Price Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron --- drivers/cxl/core/region_dax.c | 13 +++++-------- drivers/cxl/cxl.h | 1 + 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/cxl/core/region_dax.c b/drivers/cxl/core/region_dax.c index fe367759ac69..de04f78f6ad8 100644 --- a/drivers/cxl/core/region_dax.c +++ b/drivers/cxl/core/region_dax.c @@ -81,29 +81,26 @@ static void cxlr_dax_unregister(void *_cxlr_dax) =20 int devm_cxl_add_dax_region(struct cxl_region *cxlr) { - struct cxl_dax_region *cxlr_dax; struct device *dev; int rc; =20 - cxlr_dax =3D cxl_dax_region_alloc(cxlr); + struct cxl_dax_region *cxlr_dax __free(put_cxl_dax_region) =3D + cxl_dax_region_alloc(cxlr); if (IS_ERR(cxlr_dax)) return PTR_ERR(cxlr_dax); =20 dev =3D &cxlr_dax->dev; rc =3D dev_set_name(dev, "dax_region%d", cxlr->id); if (rc) - goto err; + return rc; =20 rc =3D device_add(dev); if (rc) - goto err; + return rc; =20 dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent), dev_name(dev)); =20 return devm_add_action_or_reset(&cxlr->dev, cxlr_dax_unregister, - cxlr_dax); -err: - put_device(dev); - return rc; + no_free_ptr(cxlr_dax)); } diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index f08be12e0e53..249a2f5ffc7b 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -712,6 +712,7 @@ DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) pu= t_device(&_T->port.dev)) DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_= device(&_T->dev)) DEFINE_FREE(put_cxl_root_decoder, struct cxl_root_decoder *, if (!IS_ERR_O= R_NULL(_T)) put_device(&_T->cxlsd.cxld.dev)) DEFINE_FREE(put_cxl_region, struct cxl_region *, if (!IS_ERR_OR_NULL(_T)) = put_device(&_T->dev)) +DEFINE_FREE(put_cxl_dax_region, struct cxl_dax_region *, if (!IS_ERR_OR_NU= LL(_T)) put_device(&_T->dev)) =20 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); --=20 2.53.0