From nobody Sat Apr 4 01:51:13 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B54543803FA for ; Sun, 22 Mar 2026 12:24:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774182271; cv=none; b=Wiy827bdGmPOH+7mVVaPzSY1EAS+IDlc0FM8W7PpahdN/pmueuQT4/+VekUq3ZRYGMf4Teg8k/9cATsJK6rzcF0BOVKUrpjfTq91SSrIsmb1ygJrxD577xPeCF5mgt6HXVQodiWejWCljtfUuhNJM94GhmMCiYndL6//Fv6+mgA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774182271; c=relaxed/simple; bh=V3170Kcxf+SwGKUeN/ScFDYmS/C0wM7P/06+kYpoLP0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Qird9UnziTxUuzmKv7GNs36eyfN8mQiDaSbc3gbKJ2sl1A8Jqn3xAWEqvqXQrE/hZY+rHvyT4p8kzlDdR4Ze6vDBc7Vj3UxBFYliyNjGFscM/CqGWnaDK73E/gw+2DH8SVQiq/aY/J6I48rgrM014TE1CSE2fMM/wm3VsRzW/hQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=WOvc/7LN; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WOvc/7LN" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-439b9cf8cb5so4584550f8f.0 for ; Sun, 22 Mar 2026 05:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1774182268; x=1774787068; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Bx5j4FaZKX5iw5JrPcGDY49H4qgRYZDbXdV3Cc+dJs=; b=WOvc/7LN3B8g71UjAFWiSHaOcwx5kxIbOonChX/xa1Rtlz6rH5InT++8uOtZN6YGtj KOW1w56U52xM3tHljwecBhlmVyzHhgxgwXVi8hokXEOxJttmFR6CZK12flvHfWQR6iez ySxp4WhB5k6+F/BWHAvn4+PYExBOKLqxo51VIxnNyV1bUa5QPFGMYZVC8BIcfwltbdV9 O5yo+ONts6n7uiH9C1YafSMQ2zBov/i5/qhhPNrZJb8zl2/VRNbjOsWUWdMMZwoARdNv o26ATgoJJgBnzAtHJEly8+8uS3x971+8P070HuLd0Mn/rPR90ijGued1vjI1ulTyE8m6 y5Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774182268; x=1774787068; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=9Bx5j4FaZKX5iw5JrPcGDY49H4qgRYZDbXdV3Cc+dJs=; b=kpHdH4kNG16IGFdNjx1ylL5eY1t0yHqojNciKRjm5HO5qUuJv1AAXrugcoiu+GKSbD poCGb0Lwgpq3EYcZz/LFryFq8KsyZz5sJnLbDHA7srpRzC5A2nTKBlPAiT+14u8tJRlD VqX9KtniyOaGUT2NcMf8VVnBhBP5v1dirPlAIRhyIMGItE3q1ruWzWQ8zZqQaf5Bmspv fytrJlYsbDrA49LqcbG9xBSGW5v81fQQ95+r4OAu4PyJOfceWWv8/zJLoyzj03wJTRtT YtO+Pwl31EIPUANShAj/IpTJ0tjSFJZXOT0gx1akioDw+5MpTRTcYPPzv9DKoHomIB1M hYzA== X-Forwarded-Encrypted: i=1; AJvYcCV6qyU1jDrms/diEBwRaLlN5f49bzMA3YDJH6jc93LpODM07mX9+uW9JdNugvRcSdVjLxja7mS6PHbbop8=@vger.kernel.org X-Gm-Message-State: AOJu0YwuQFna2j0V3Fo71f3bLAhB0651paxQr6hy7+L2RvL5qzTMUVq9 BhRq4XmMRGPnsG+8O3q0kDtMOvn4xx0gsyxvZoBCK+4AkOkzkM1+C1LR X-Gm-Gg: ATEYQzzPwSNXLh238oBUG9PqcRuUVadg65lxs9Sc41PTgGHE2To/DeY0ZKtcHQ2gas8 /Qnt5/n9Vxj/HLn05eYaPFbLTbo3rtGfxRBnoQKzv8wwSfv0DGdeJLqF9YlL8uZo6FbP5QZAjSD dfHSFjPfVULYlmbpsgB3gPYog1Nn4IAEeUaY6ce3fo3cPLsHzL5G4g/lOizacs9kiv4+pmn7bOH ADkdpCdWjJboZLbQ6CAP3IfQ01OpYrN4wIDa1PDXvY4WKCOmDEelJtxmP2yA8AMJ4M1HPFprJu+ 6JfbLV7N6KuJy6932fG7ej3jcGyEjogwenXqbWvnEVJXRTD2e7RE2i0LxndICrK3ipUL7ygkev7 x/jZx4CLHYAsGV6Ucsl6bil5+dppxQ4GWvy98VQMIQcAwfR1DuNLI77UBuD/Dn4dHDZUsjdseNb pVCeXvaRzPj4Wrgc4wTO8mmafPSBTNbNLiRu7GBHv5xjDF8tAs X-Received: by 2002:a05:6000:250e:b0:43b:4dd4:6856 with SMTP id ffacd0b85a97d-43b64238854mr15485470f8f.8.1774182268067; Sun, 22 Mar 2026 05:24:28 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:1bdc:7f84:18bc:1e56]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b64703343sm21072695f8f.19.2026.03.22.05.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 05:24:27 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v6 04/15] irqchip/renesas-rzg2l: Replace single irq_chip with per-region irq_chip instances Date: Sun, 22 Mar 2026 12:23:47 +0000 Message-ID: <20260322122421.132474-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260322122421.132474-1-biju.das.jz@bp.renesas.com> References: <20260322122421.132474-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The driver previously used a single irq_chip instance shared across all interrupt types, relying on dispatcher callbacks to differentiate between IRQ and TINT regions at runtime. Replace the per-SoC irq_chip and its dispatcher callbacks with dedicated irq_chip instances for each interrupt region: IRQ and TINT. Subsequent patches will add per-region callbacks for IRQ and TINT from the common code. Signed-off-by: Biju Das --- v5->v6: * No change. v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 61 ++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index ed8044b0a339..a0f03f81d5ef 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -71,14 +71,16 @@ struct rzg2l_irqc_reg_cache { /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address - * @irqchip: Pointer to struct irq_chip + * @irq_chip: Pointer to struct irq_chip for irq + * @tint_chip: Pointer to struct irq_chip for tint * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { void __iomem *base; - const struct irq_chip *irqchip; + const struct irq_chip *irq_chip; + const struct irq_chip *tint_chip; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; struct rzg2l_irqc_reg_cache cache; @@ -434,7 +436,7 @@ static struct syscore rzg2l_irqc_syscore =3D { .ops =3D &rzg2l_irqc_syscore_ops, }; =20 -static const struct irq_chip rzg2l_irqc_chip =3D { +static const struct irq_chip rzg2l_irqc_irq_chip =3D { .name =3D "rzg2l-irqc", .irq_eoi =3D rzg2l_irqc_eoi, .irq_mask =3D irq_chip_mask_parent, @@ -451,7 +453,41 @@ static const struct irq_chip rzg2l_irqc_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 -static const struct irq_chip rzfive_irqc_chip =3D { +static const struct irq_chip rzg2l_irqc_tint_chip =3D { + .name =3D "rzg2l-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D rzg2l_irqc_irq_disable, + .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzfive_irqc_irq_chip =3D { + .name =3D "rzfive-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D rzfive_irqc_mask, + .irq_unmask =3D rzfive_irqc_unmask, + .irq_disable =3D rzfive_irqc_irq_disable, + .irq_enable =3D rzfive_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_eoi, .irq_mask =3D rzfive_irqc_mask, @@ -472,6 +508,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, unsigned int nr_irqs, void *arg) { struct rzg2l_irqc_priv *priv =3D domain->host_data; + const struct irq_chip *chip; unsigned long tint =3D 0; irq_hw_number_t hwirq; unsigned int type; @@ -491,13 +528,15 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain= , unsigned int virq, if (hwirq > IRQC_IRQ_COUNT) { tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); + chip =3D priv->tint_chip; + } else { + chip =3D priv->irq_chip; } =20 if (hwirq > (IRQC_NUM_IRQ - 1)) return -EINVAL; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, - (void *)(uintptr_t)tint); + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); if (ret) return ret; =20 @@ -529,7 +568,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, } =20 static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct de= vice_node *parent, - const struct irq_chip *irq_chip) + const struct irq_chip *irq_chip, + const struct irq_chip *tint_chip) { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; @@ -545,7 +585,8 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n if (!rzg2l_irqc_data) return -ENOMEM; =20 - rzg2l_irqc_data->irqchip =3D irq_chip; + rzg2l_irqc_data->irq_chip =3D irq_chip; + rzg2l_irqc_data->tint_chip =3D tint_chip; =20 rzg2l_irqc_data->base =3D devm_of_iomap(dev, dev->of_node, 0, NULL); if (IS_ERR(rzg2l_irqc_data->base)) @@ -585,12 +626,12 @@ static int rzg2l_irqc_common_probe(struct platform_de= vice *pdev, struct device_n =20 static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l= _irqc_tint_chip); } =20 static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfi= ve_irqc_tint_chip); } =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) --=20 2.43.0