From nobody Sat Apr 4 01:51:12 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5620381AF6 for ; Sun, 22 Mar 2026 12:24:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774182284; cv=none; b=omd0H28AysWmm7AdBg99N98nOoHFhVt6SdnmhtIrbXwxaNImDWFa448RsaBR5T4wMwpnByFsuECtmrb1bhcBZmaRztnIllDtX50MRzS+uUXjqoeFb09ot6NRAdw39r6SavLB077WQMbjxr76RAezaT4mVhGeOPxj0GRcdh2h8Uw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774182284; c=relaxed/simple; bh=DMtvpcEgaBXfJ2rMgy2gC2zoJNu6Ano6N3tBASL/0tQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s+OdZHm46Tt53hLcT2pJk1DN46B5pt9Eqf32ru/iPXzADrZLHUuXFME/fYrwgF3mDDWWnrnkywQ/spbg7Ps8MN7iJEQvxLX4Xr2i/geiTtwJfaqALc3w8gdidGLoMJAH/DJeEcGIIycQ/k0lBEcKpUhZs3A212p2bzZTPVhC8Bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Iyisa/k8; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Iyisa/k8" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-439b9cf8cb5so4584622f8f.0 for ; Sun, 22 Mar 2026 05:24:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1774182278; x=1774787078; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jxpYf4rR4gelppN+mkmImDmznlIgWvfrJ1JaybzbEnU=; b=Iyisa/k8BxbAXfSU05wtGxCRMTyDVRZ3m3ZD7LDsj2u0P78F2PhpIB1ahmNueCE9jD ZPMoLg94yX5HPxKDKnYeLY1EQ1Eju20gBC8mAsqstpUJLCSd+T+wc7EgpXuJUu57qYWy H6tKhgxZ6vmEmYXZ3O0Dv1qPRt0eQDkdt/O7D6c9C89D39jJDB4BwhRJFXEo8B61//ru VWFIcJH9SZP6Sib2u16UuHSaErwRSnNTteCCv+hNy3lYmm4EPjtcEkc9wu3EpaxSFwvk 0vjf1WaNHDmI4tCFUvIoOWCG/6RS6haTXQIWndt8ySedyZIprrWCtNjtoA7aKrKPgDkY 49SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774182278; x=1774787078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=jxpYf4rR4gelppN+mkmImDmznlIgWvfrJ1JaybzbEnU=; b=aatzBAcj1M/cOVbhEmRbqMHLuJUK9HlGJ9+oqCSViJ5KNPd20ePOrfnla+T8cMGQOK JunktWBcKWVVEKR7pE0zlZnR/31LlAYtqW/4T6jBROveoJgVulbcRlV9kUrMXvELp3Q0 A95JxH4ABo/YxjH1HcWy+S+HuAd4Apkh7XoAAqmK8spz3l1aEB9hdS+gH9HXTdoZVpZQ vFsHsoKaoeNEJ3r7/0bT6TrpfQo2gmPl16tkyx6zRHKmkg+p0qbogY5jvYCpvBFfNPvf hx7h3JVfF/u9Mhwjhwz3olAR/LuU/XjpjLK+bHtibXX1JBruSdR/cGLLGY48ncCSWj+I zVnQ== X-Forwarded-Encrypted: i=1; AJvYcCU/cFsq13pq3e7xKImYlZlhwwm/bQAr3PrSw1bKsdeXXCmjqolGQZcWHuhrISK5nuSRTSulN/B7gBMM/yQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yw1wgNJm3Chnn83iEAiQLqKxnaoXCgMeuVWjEYt5s2rbfyJMq5i obSO/BKFUwNbyaW46jSmXcJJcdhjsYcSZNsHb1atDml0Sj/vAKX1zpxv X-Gm-Gg: ATEYQzy6T9Q5vbmpUWI++JGC6iXZj4Q6seDiYXamdzKJ/weDnG6q5rrMUzLD4XZh5/y JvDDrBCPwoOIpxY2yAu8gibvfRQy0WzSaFqKsVPTOg/g3kNcwChG7K/qvENc4HV8lU21vIyYXil FvvobwieRlDesONcsdooVX6Q1n4kSrY80e+r9k+QuzDhMVBPe/kY68TX8BumJ4Vfm+looCxiutQ WmPiStzDRdnTXT33rLqw5HHIYyK8dQnaB1VfcdYXaTYY3WugmkvBe7baDPP7uCjmyYA+1jeFbLg 81CLqjFTRWVMOOhCO2KG9i6LxI4g/Ciql6+m8nkI1XA4wRNSkKrKO4oarzlOVwEN70zRikOnreC V+l5LwF63lyo5eIK+ukGy/U3mrRVDOuIqr2LWSnvI1+y9k6fc+dKGtBjNPR24zBtTtRZwgdmb5N vRzTlSiiSXEVI4zI3wqxofwkBPLbwC38M7RCPw3H+KPUWs4iaX X-Received: by 2002:a5d:64e3:0:b0:43b:4720:10f2 with SMTP id ffacd0b85a97d-43b64279755mr14432571f8f.43.1774182277918; Sun, 22 Mar 2026 05:24:37 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:1bdc:7f84:18bc:1e56]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b64703343sm21072695f8f.19.2026.03.22.05.24.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 05:24:37 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v6 15/15] irqchip/renesas-rzg2l: Add shared interrupt support Date: Sun, 22 Mar 2026 12:23:58 +0000 Message-ID: <20260322122421.132474-16-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260322122421.132474-1-biju.das.jz@bp.renesas.com> References: <20260322122421.132474-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has 16 external interrupts, of which 8 are shared with TINT (GPIO interrupts), whereas RZ/G2L has only 8 external interrupts with no sharing. The shared interrupt line selection between external interrupt and GPIO interrupt is based on the INTTSEL register. Add shared_irq_cnt variable to struct rzg2l_hw_info handle these differences. Add used_irqs bitmap to struct rzg2l_irqc_priv to track allocation state. In the alloc callback, use test_and_set_bit() to enforce mutual exclusion and configure the INTTSEL register to route to either the external interrupt or TINT. In the free callback, use test_and_clear_bit() to release the shared interrupt line and reset the INTTSEL. Also add INTTSEL register save/restore support to the suspend/resume path. Signed-off-by: Biju Das --- v5->v6: * Updated commit description. * Switched to using irq_domain_ops::{alloc,free} callbacks for mutual exclusion between external interrupts and GPIO interrupts as using irq_{request,release}_resources() leading to irq storm() * Dropped irq_{request,release}_resources(). * Replaced the macro TINTSEL->INTTSEL_TINTSEL * Added macros INTTSEL_TINTSEL_START, IRQC_SHARED_IRQ_COUNT and IRQC_IRQ_SHARED_START. * Added used_irqs bitmap to struct rzg2l_irqc_priv to track allocation state of shared_interrupt * Added rzg2l_irqc_set_inttsel() for configuring INTTSEL register. * Replaced irq_domain_free_irqs_common()->rzg2l_irqc_free() as=20 rzg2l_irqc_domain_ops::free() callback. * Replaced the 8->IRQC_SHARED_IRQ_COUNT in shared_irq_cnt varaible as the same macro used in bitmap. v4->v5: * Added callback irq_{request,release}_resources() to both irq and tint interrupt chips. v3->v4: * Updated commit header irq->interrupt. * Updated commit description IRQs->interrupts. * Updated shared_irq_cnt variable type from u8->unsigned int. v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 104 +++++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 1ff1c0efed66..97bbaaaeedb0 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -22,6 +22,8 @@ =20 #define IRQC_IRQ_START 1 #define IRQC_TINT_COUNT 32 +#define IRQC_SHARED_IRQ_COUNT 8 +#define IRQC_IRQ_SHARED_START (IRQC_IRQ_START + IRQC_SHARED_IRQ_COUNT) =20 #define ISCR 0x10 #define IITSR 0x14 @@ -29,6 +31,7 @@ #define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 +#define INTTSEL 0x2c #define TSSR(n) (0x30 + ((n) * 4)) #define TIEN BIT(7) #define TSSEL_SHIFT(n) (8 * (n)) @@ -52,16 +55,21 @@ #define IITSR_IITSEL_EDGE_BOTH 3 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) =20 +#define INTTSEL_TINTSEL(n) BIT(n) +#define INTTSEL_TINTSEL_START 24 + #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) =20 /** * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @iitsr: IITSR register + * @inttsel: INTTSEL register * @titsr: TITSR registers */ struct rzg2l_irqc_reg_cache { u32 iitsr; + u32 inttsel; u32 titsr[2]; }; =20 @@ -71,12 +79,14 @@ struct rzg2l_irqc_reg_cache { * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts + * @shared_irq_cnt: Number of shared interrupts */ struct rzg2l_hw_info { const u8 *tssel_lut; unsigned int irq_count; unsigned int tint_start; unsigned int num_irq; + unsigned int shared_irq_cnt; }; =20 /** @@ -88,6 +98,7 @@ struct rzg2l_hw_info { * @lock: Lock to serialize access to hardware registers * @info: Hardware specific data * @cache: Registers cache for suspend/resume + * @used_irqs Bitmap to manage the shared interrupts */ static struct rzg2l_irqc_priv { void __iomem *base; @@ -97,6 +108,7 @@ static struct rzg2l_irqc_priv { raw_spinlock_t lock; struct rzg2l_hw_info info; struct rzg2l_irqc_reg_cache cache; + DECLARE_BITMAP(used_irqs, IRQC_SHARED_IRQ_COUNT); } *rzg2l_irqc_data; =20 static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) @@ -464,6 +476,8 @@ static int rzg2l_irqc_irq_suspend(void *data) void __iomem *base =3D rzg2l_irqc_data->base; =20 cache->iitsr =3D readl_relaxed(base + IITSR); + if (rzg2l_irqc_data->info.shared_irq_cnt) + cache->inttsel =3D readl_relaxed(base + INTTSEL); for (u8 i =3D 0; i < 2; i++) cache->titsr[i] =3D readl_relaxed(base + TITSR(i)); =20 @@ -482,6 +496,8 @@ static void rzg2l_irqc_irq_resume(void *data) */ for (u8 i =3D 0; i < 2; i++) writel_relaxed(cache->titsr[i], base + TITSR(i)); + if (rzg2l_irqc_data->info.shared_irq_cnt) + writel_relaxed(cache->inttsel, base + INTTSEL); writel_relaxed(cache->iitsr, base + IITSR); } =20 @@ -562,6 +578,72 @@ static const struct irq_chip rzfive_irqc_tint_chip =3D= { IRQCHIP_SKIP_SET_WAKE, }; =20 +static bool rzg2l_irqc_is_shared_irqc(const struct rzg2l_hw_info info, uns= igned int hw_irq) +{ + return ((hw_irq >=3D (info.tint_start - info.shared_irq_cnt)) && hw_irq <= info.tint_start); +} + +static bool rzg2l_irqc_is_shared_tint(const struct rzg2l_hw_info info, uns= igned int hw_irq) +{ + return ((hw_irq >=3D (info.num_irq - info.shared_irq_cnt)) && hw_irq < in= fo.num_irq); +} + +static bool rzg2l_irq_is_shared_and_get_irq_num(struct rzg2l_irqc_priv *pr= iv, + irq_hw_number_t hwirq, unsigned int *irq_num) +{ + bool is_shared =3D false; + + if (rzg2l_irqc_is_shared_irqc(priv->info, hwirq)) { + *irq_num =3D hwirq - IRQC_IRQ_SHARED_START; + is_shared =3D true; + } else if (rzg2l_irqc_is_shared_tint(priv->info, hwirq)) { + *irq_num =3D hwirq - IRQC_TINT_COUNT - IRQC_IRQ_SHARED_START; + is_shared =3D true; + } + + return is_shared; +} + +static void rzg2l_irqc_set_inttsel(struct rzg2l_irqc_priv *priv, unsigned = int offset, + unsigned int select_irq) +{ + u32 reg; + + guard(raw_spinlock)(&priv->lock); + reg =3D readl_relaxed(priv->base + INTTSEL); + if (select_irq) + reg |=3D INTTSEL_TINTSEL(offset); + else + reg &=3D ~INTTSEL_TINTSEL(offset); + writel_relaxed(reg, priv->base + INTTSEL); +} + +static int rzg2l_irqc_shared_irq_alloc(struct rzg2l_irqc_priv *priv, irq_h= w_number_t hwirq) +{ + unsigned int irq_num; + + if (rzg2l_irq_is_shared_and_get_irq_num(priv, hwirq, &irq_num)) { + if (test_and_set_bit(irq_num, priv->used_irqs)) + return -EBUSY; + + if (hwirq < priv->info.tint_start) + rzg2l_irqc_set_inttsel(priv, INTTSEL_TINTSEL_START + irq_num, 1); + else + rzg2l_irqc_set_inttsel(priv, INTTSEL_TINTSEL_START + irq_num, 0); + } + + return 0; +} + +static void rzg2l_irqc_shared_irq_free(struct rzg2l_irqc_priv *priv, irq_h= w_number_t hwirq) +{ + unsigned int irq_num; + + if (rzg2l_irq_is_shared_and_get_irq_num(priv, hwirq, &irq_num) && + test_and_clear_bit(irq_num, priv->used_irqs)) + rzg2l_irqc_set_inttsel(priv, INTTSEL_TINTSEL_START + irq_num, 0); +} + static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { @@ -594,6 +676,12 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain,= unsigned int virq, if (hwirq >=3D priv->info.num_irq) return -EINVAL; =20 + if (priv->info.shared_irq_cnt) { + ret =3D rzg2l_irqc_shared_irq_alloc(priv, hwirq); + if (ret) + return ret; + } + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); if (ret) return ret; @@ -601,9 +689,22 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain,= unsigned int virq, return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[= hwirq]); } =20 +static void rzg2l_irqc_free(struct irq_domain *domain, unsigned int virq, = unsigned int nr_irqs) +{ + struct rzg2l_irqc_priv *priv =3D domain->host_data; + + if (priv->info.shared_irq_cnt) { + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + + rzg2l_irqc_shared_irq_free(priv, irqd_to_hwirq(d)); + } + + return irq_domain_free_irqs_common(domain, virq, nr_irqs); +} + static const struct irq_domain_ops rzg2l_irqc_domain_ops =3D { .alloc =3D rzg2l_irqc_alloc, - .free =3D irq_domain_free_irqs_common, + .free =3D rzg2l_irqc_free, .translate =3D irq_domain_translate_twocell, }; =20 @@ -718,6 +819,7 @@ static const struct rzg2l_hw_info rzg3l_hw_params =3D { .irq_count =3D 16, .tint_start =3D IRQC_IRQ_START + 16, .num_irq =3D IRQC_IRQ_START + 16 + IRQC_TINT_COUNT, + .shared_irq_cnt =3D IRQC_SHARED_IRQ_COUNT, }; =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { --=20 2.43.0