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Sun, 22 Mar 2026 05:24:32 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v6 09/15] irqchip/renesas-rzg2l: Split rzfive_irqc_{mask,unmask} into separate IRQ and TINT handlers Date: Sun, 22 Mar 2026 12:23:52 +0000 Message-ID: <20260322122421.132474-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260322122421.132474-1-biju.das.jz@bp.renesas.com> References: <20260322122421.132474-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das rzfive_irqc_mask() and rzfive_irqc_unmask() used hw_irq range checks to dispatch between IRQ and TINT masking operations. Split each into two dedicated handlers =E2=80=94 rzfive_irqc_irq_mask(), rzfive_irqc_tint_mask(= ), rzfive_irqc_irq_unmask(), and rzfive_irqc_tint_unmask() =E2=80=94 each operating unconditionally on its respective interrupt type, removing the runtime conditionals. Assign the IRQ-specific handlers to rzfive_irqc_irq_chip and the TINT-specific handlers to rzfive_irqc_tint_chip, consistent with the separation applied to the EOI, set_type, and enable/disable callbacks in previous patches. While at it, simplify rzfive_irqc_{irq,tint}_{mask,unmask}() by replacing raw_spin_lock locking/unlocking with scoped_guard(). Signed-off-by: Biju Das --- v5->v6: * Updated commit description. * Simplified rzfive_irqc_{irq,tint}_{mask,unmask}() by replacing raw_spin_lock locking/unlocking with scoped_guard(). v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 44 ++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 71bde07675d9..0b1bad002653 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -184,31 +184,47 @@ static void rzfive_irqc_unmask_tint_interrupt(struct = rzg2l_irqc_priv *priv, writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK= ); } =20 -static void rzfive_irqc_mask(struct irq_data *d) +static void rzfive_irqc_irq_mask(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - raw_spin_lock(&priv->lock); - if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) + scoped_guard(raw_spinlock, &priv->lock) rzfive_irqc_mask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + + irq_chip_mask_parent(d); +} + +static void rzfive_irqc_tint_mask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + scoped_guard(raw_spinlock, &priv->lock) rzfive_irqc_mask_tint_interrupt(priv, hwirq); - raw_spin_unlock(&priv->lock); + irq_chip_mask_parent(d); } =20 -static void rzfive_irqc_unmask(struct irq_data *d) +static void rzfive_irqc_irq_unmask(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - raw_spin_lock(&priv->lock); - if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) + scoped_guard(raw_spinlock, &priv->lock) rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + + irq_chip_unmask_parent(d); +} + +static void rzfive_irqc_tint_unmask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + scoped_guard(raw_spinlock, &priv->lock) rzfive_irqc_unmask_tint_interrupt(priv, hwirq); - raw_spin_unlock(&priv->lock); + irq_chip_unmask_parent(d); } =20 @@ -497,8 +513,8 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { static const struct irq_chip rzfive_irqc_irq_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_irq_eoi, - .irq_mask =3D rzfive_irqc_mask, - .irq_unmask =3D rzfive_irqc_unmask, + .irq_mask =3D rzfive_irqc_irq_mask, + .irq_unmask =3D rzfive_irqc_irq_unmask, .irq_disable =3D rzfive_irqc_irq_disable, .irq_enable =3D rzfive_irqc_irq_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, @@ -514,8 +530,8 @@ static const struct irq_chip rzfive_irqc_irq_chip =3D { static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_tint_eoi, - .irq_mask =3D rzfive_irqc_mask, - .irq_unmask =3D rzfive_irqc_unmask, + .irq_mask =3D rzfive_irqc_tint_mask, + .irq_unmask =3D rzfive_irqc_tint_unmask, .irq_disable =3D rzfive_irqc_tint_disable, .irq_enable =3D rzfive_irqc_tint_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, --=20 2.43.0