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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c10b14c985sm11389751eec.2.2026.03.22.23.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 23:20:06 -0700 (PDT) From: Jingyi Wang Date: Sun, 22 Mar 2026 23:19:45 -0700 Subject: [PATCH 5/6] arm64: dts: qcom: kaanapali: add display hardware devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260322-knp-pmic-dt-v1-5-70bc40ea4428@oss.qualcomm.com> References: <20260322-knp-pmic-dt-v1-0-70bc40ea4428@oss.qualcomm.com> In-Reply-To: <20260322-knp-pmic-dt-v1-0-70bc40ea4428@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260224-knp-dts-misc-v6-0-79d20dab8a60@oss.qualcomm.com, Yuanjie Yang X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774246801; l=7174; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=ET7AlHju4QdPwosZx24+HbzlN/hum+VoJGcHfUY3eoE=; b=1yC5Etob8lYqVkBtT30oxu+u/Kwn430xR5Ijxmqb8H1I/6bl+sS/p6fizNJsNzYNCb8VgVff8 Mo+IMg7ZDySBEg8z1Twzl6J5G0IzVJd2Abeh1oVI3soiQL5ksROh09C X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-GUID: jviwwbsL6JCLig64TTTgp9FUxj2oj5i7 X-Authority-Analysis: v=2.4 cv=Z5rh3XRA c=1 sm=1 tr=0 ts=69c0db98 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=ekcQ59J20JkAXHuyNo8A:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDA0NiBTYWx0ZWRfX6NcZx3kvHPxR kPcwPiFTRWorGbM9cLiFpigIm2PK5eT2rFW1u12KkaVGaeeg9F1VWk0Hp3V9Ml2oiUdwdGvZI+O lakuu+lY6KY18+9S8lIMj2cs3/wkEZZbgwVXab8dwk8byw3+mJK290Fe8A4yKGNeO566SiGh0bj X559RqYGS0lFQyd+x4U5ExERBntVmccdVA4raTPi1l+4iYVYuZP8E/1ast+ZwANt4BKlVQALnmW QnVuY3gpoQ9odkXu8MINN8k4GrvovkcUA0gGL5D6UI21WDlrdefRYcRUiFonXtCMkzA1WdGJaSk AvKOUn/MovqOm44aCwlbP+tzLgHAoFHyBo1ERI5FIZJt5J2XC0SxLChpnuqUEsAiODj1yebERM1 KSlrQZYvwb3UvYgmbsnV4UCOgDhA07ZyvODyypAGOV29PRSwNjBTljnCHrKv3uSLJKVLc6I8VNR qSbtp9nQn4hXobKPOSQ== X-Proofpoint-ORIG-GUID: jviwwbsL6JCLig64TTTgp9FUxj2oj5i7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_02,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 suspectscore=0 clxscore=1015 spamscore=0 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230046 From: Yuanjie Yang Add MDSS/MDP/DSI controllers and DSI PHYs for Kaanapali. DP controllers are not included. Signed-off-by: Yuanjie Yang Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 242 ++++++++++++++++++++++++++++= +++- 1 file changed, 240 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index f0de06b2c20b..bf3c6eb496e1 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3,6 +3,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include #include #include #include @@ -3156,6 +3157,243 @@ camcc: clock-controller@956d000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@9800000 { + compatible =3D "qcom,kaanapali-mdss"; + reg =3D <0x0 0x09800000 0x0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_AHB_SWI_CLK>; + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus =3D <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@9801000 { + compatible =3D "qcom,kaanapali-dpu"; + reg =3D <0x0 0x09801000 0x0 0x1c8000>, + <0x0 0x09b16000 0x0 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + }; + }; + + port@2 { + reg =3D <2>; + + dpu_intf0_out: endpoint { + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-156000000 { + opp-hz =3D /bits/ 64 <156000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz =3D /bits/ 64 <207000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz =3D /bits/ 64 <337000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@9ac0000 { + compatible =3D "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x09ac0000 0x0 0x1000>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-250000000 { + opp-hz =3D /bits/ 64 <250000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-312500000 { + opp-hz =3D /bits/ 64 <312500000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@9ac1000 { + compatible =3D "qcom,kaanapali-dsi-phy-3nm"; + reg =3D <0x0 0x09ac1000 0x0 0x1cc>, + <0x0 0x09ac1200 0x0 0x280>, + <0x0 0x09ac1500 0x0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + }; + dispcc: clock-controller@9ba2000 { compatible =3D "qcom,kaanapali-dispcc"; reg =3D <0x0 0x09ba2000 0x0 0x20000>; @@ -3171,8 +3409,8 @@ dispcc: clock-controller@9ba2000 { <0>, <0>, <0>, - <0>, - <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>; =20 --=20 2.25.1