From nobody Thu Apr 2 17:18:51 2026 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F2EC342CB2; Sat, 21 Mar 2026 09:20:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774084854; cv=none; b=uf9l5iGjLlx1ZZxAMnWtl9Gymxtuxc8RnCAjqc3HJe4GuiAnAyjonMqfucvtHhpE5Iv9HobwMjTgP1ZprgMh1G9xQyxN8Mjg1e1yxQltabUPw6nIPj29MnO6GVoY3IsPgkf8O7SarcnfcZrQP/SmPizUSSDwT5SojXve+LauoTY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774084854; c=relaxed/simple; bh=OGOQfaA5uoV50FJuFepEkSe0Mz1uPNAFeLOvgaS+RFM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iY+q119+87O38d6RJ/BGxJu3jTDMYuzBv7bdEX+t0fZixQIzSOuwrGZiy5qCjzJdZHIWvu/7FE+wuTGiQMqNigiCgnefMeVSKg6BVuCiUb8vygq7sfbGDDmuv0g4cRTRL7lAA9DhiNxyx+W3gS0p3O3UuWV1rDpoxIc5cUFcYgA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.102.202]) by APP-01 (Coremail) with SMTP id qwCowAA33mnjYr5p3aWyCg--.465S7; Sat, 21 Mar 2026 17:20:44 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Thomas Bogendoerfer , Jiaxun Yang Cc: Icenowy Zheng , Yao Zi , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, Icenowy Zheng Subject: [PATCH v4 5/6] irqchip/loongson-pch-lpc: Add OF init code Date: Sat, 21 Mar 2026 17:20:31 +0800 Message-ID: <20260321092032.3502701-6-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260321092032.3502701-1-zhengxingda@iscas.ac.cn> References: <20260321092032.3502701-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowAA33mnjYr5p3aWyCg--.465S7 X-Coremail-Antispam: 1UD129KBjvJXoW7tr13ZFy8Zr48Jr4kGrWrAFb_yoW8uF48pF W5Zay5Zr4rJr4Igw1fAFWkArZIvr4rGrW7trWxC3WfAw1DKrWkCF1DCF1qvr4rArW5WFW5 uF4rtF4UCF4DAF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmS14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2 ka0xkIwI1lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Y z7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zV AF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1l IxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF 4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBI daVFxhVjvjDU0xZFpf9x0JUQFxUUUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" The OF-based MIPS Loongson-3 systems can also have a PCH LPC interrupt controller. Add OF-based initialization code for this driver. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Icenowy Zheng --- drivers/irqchip/irq-loongson-pch-lpc.c | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-l= oongson-pch-lpc.c index 2bb6659e9a93c..7117ca6fc2f05 100644 --- a/drivers/irqchip/irq-loongson-pch-lpc.c +++ b/drivers/irqchip/irq-loongson-pch-lpc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include =20 #include "irq-loongson.h" @@ -224,6 +226,7 @@ static int __init pch_lpc_init(phys_addr_t addr, unsign= ed long size, return -ENOMEM; } =20 +#ifdef CONFIG_ACPI int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_l= pc_pic *acpi_pchlpc) { struct fwnode_handle *irq_handle; @@ -256,3 +259,35 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent= , struct acpi_madt_lpc_pic =20 return 0; } +#endif /* CONFIG_ACPI */ + +#ifdef CONFIG_OF +static int __init pch_lpc_of_init(struct device_node *node, struct device_= node *parent) +{ + struct fwnode_handle *irq_handle; + struct resource res; + int parent_irq, ret; + + if (of_address_to_resource(node, 0, &res)) + return -EINVAL; + + parent_irq =3D irq_of_parse_and_map(node, 0); + if (!parent_irq) { + pr_err("Failed to get the parent IRQ for LPC IRQs\n"); + return -EINVAL; + } + + irq_handle =3D of_fwnode_handle(node); + + ret =3D pch_lpc_init(res.start, resource_size(&res), irq_handle, + parent_irq); + if (ret) { + irq_dispose_mapping(parent_irq); + return ret; + } + + return 0; +} + +IRQCHIP_DECLARE(pch_lpc, "loongson,ls7a-lpc", pch_lpc_of_init); +#endif /* CONFIG_OF */ --=20 2.52.0