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Fri, 20 Mar 2026 22:45:17 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Evan Quan , Mario Limonciello , Sasha Levin , Rosen Penev , Lijo Lazar , Ma Jun , Greg Kroah-Hartman , Srinivasan Shanmugam , "Mario Limonciello (AMD)" , Zhigang Luo , Bert Karwatzki , Ray Wu , Wayne Lin , Roman Li , Hersen Wu , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Alex Hung , decce6 , Wentao Liang , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv3 for 6.1 3/4] drm/amd/display: Add pixel_clock to amd_pp_display_configuration Date: Fri, 20 Mar 2026 22:44:52 -0700 Message-ID: <20260321054453.19683-4-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260321054453.19683-1-rosenp@gmail.com> References: <20260321054453.19683-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit b515dcb0dc4e85d8254f5459cfb32fce88dacbfb ] This commit adds the pixel_clock field to the display config struct so that power management (DPM) can use it. We currently don't have a proper bandwidth calculation on old GPUs with DCE 6-10 because dce_calcs only supports DCE 11+. So the power management (DPM) on these GPUs may need to make ad-hoc decisions for display based on the pixel clock. Also rename sym_clock to pixel_clock in dm_pp_single_disp_config to avoid confusion with other code where the sym_clock refers to the DisplayPort symbol clock. Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 1 + drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 +- drivers/gpu/drm/amd/include/dm_pp_interface.h | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/dri= vers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index 75284e2cec74..c4e7d9212cd4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -97,6 +97,7 @@ bool dm_pp_apply_display_requirements( const struct dm_pp_single_disp_config *dc_cfg =3D &pp_display_cfg->disp_configs[i]; adev->pm.pm_display_cfg.displays[i].controller_id =3D dc_cfg->pipe_idx = + 1; + adev->pm.pm_display_cfg.displays[i].pixel_clock =3D dc_cfg->pixel_clock; } amdgpu_dpm_display_configuration_change(adev, &adev->pm.pm_display_cfg); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c= b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c index fb2f154f4fda..bce53ab36f3e 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c @@ -164,7 +164,7 @@ void dce110_fill_display_configs( stream->link->cur_link_settings.link_rate; cfg->link_settings.link_spread =3D stream->link->cur_link_settings.link_spread; - cfg->sym_clock =3D stream->phy_pix_clk; + cfg->pixel_clock =3D stream->phy_pix_clk; /* Round v_refresh*/ cfg->v_refresh =3D stream->timing.pix_clk_100hz * 100; cfg->v_refresh /=3D stream->timing.h_total; diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/g= pu/drm/amd/display/dc/dm_services_types.h index b52ba6ffabe1..954b3aa65adb 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -127,7 +127,7 @@ struct dm_pp_single_disp_config { uint32_t src_height; uint32_t src_width; uint32_t v_refresh; - uint32_t sym_clock; /* HDMI only */ + uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */ struct dc_link_settings link_settings; /* DP only */ }; diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/dr= m/amd/include/dm_pp_interface.h index 1d93a0c574c9..ee4212cc93d1 100644 --- a/drivers/gpu/drm/amd/include/dm_pp_interface.h +++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h @@ -66,6 +66,7 @@ struct single_display_configuration uint32_t view_resolution_cy; enum amd_pp_display_config_type displayconfigtype; uint32_t vertical_refresh; /* for active display */ + uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */ }; #define MAX_NUM_DISPLAY 32 -- 2.53.0