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Fri, 20 Mar 2026 09:42:01 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 1/4] dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3L SoC Date: Fri, 20 Mar 2026 16:41:47 +0000 Message-ID: <20260320164158.487406-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260320164158.487406-1-biju.das.jz@bp.renesas.com> References: <20260320164158.487406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add a compatible string for the Renesas RZ/G3L SoC variants that include a Mali-G31 GPU. These variants share the same restrictions on interrupts, clocks, and power domains as the RZ/G2L SoC, so extend the existing schema validation accordingly. Acked-by: Rob Herring (Arm) Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v1->v2: * Collected tag --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/= Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index db49b8ff8c74..9db9f84ad964 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -26,6 +26,7 @@ properties: - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a08g046-mali - renesas,r9a09g047-mali - renesas,r9a09g056-mali - renesas,r9a09g057-mali @@ -150,6 +151,7 @@ allOf: enum: - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a08g046-mali - renesas,r9a09g047-mali - renesas,r9a09g056-mali - renesas,r9a09g057-mali --=20 2.43.0 From nobody Sat Apr 4 04:35:53 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A67FC3D1714 for ; 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Fri, 20 Mar 2026 09:42:02 -0700 (PDT) Received: from biju.lan ([2a00:23c4:a758:8a01:5b93:d2b1:bc5c:9231]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b64703650sm7016575f8f.20.2026.03.20.09.42.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2026 09:42:02 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Boris Brezillon , Rob Herring , Steven Price , =?UTF-8?q?Adri=C3=A1n=20Larumbe?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Biju Das , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 2/4] drm/panfrost: Drop redundant optional clock checks in runtime PM Date: Fri, 20 Mar 2026 16:41:48 +0000 Message-ID: <20260320164158.487406-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260320164158.487406-1-biju.das.jz@bp.renesas.com> References: <20260320164158.487406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das The clk_enable() and clk_disable() APIs already handle NULL clock pointers gracefully =E2=80=94 clk_enable() returns 0 and clk_disable() returns immed= iately when passed a NULL or optional clock. The explicit if (pfdev->bus_clock) guards around these calls in the runtime suspend/resume paths are therefore unnecessary. Remove them to simplify the code. Reviewed-by: Steven Price Signed-off-by: Biju Das Reviewed-by: Adri=C3=A1n Larumbe --- v1->v2: * Collected tag --- drivers/gpu/drm/panfrost/panfrost_device.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/p= anfrost/panfrost_device.c index dedc13e56631..01e702a0b2f0 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -429,11 +429,9 @@ static int panfrost_device_runtime_resume(struct devic= e *dev) if (ret) goto err_clk; =20 - if (pfdev->bus_clock) { - ret =3D clk_enable(pfdev->bus_clock); - if (ret) - goto err_bus_clk; - } + ret =3D clk_enable(pfdev->bus_clock); + if (ret) + goto err_bus_clk; } =20 panfrost_device_reset(pfdev, true); @@ -464,9 +462,7 @@ static int panfrost_device_runtime_suspend(struct devic= e *dev) panfrost_gpu_power_off(pfdev); =20 if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) { - if (pfdev->bus_clock) - clk_disable(pfdev->bus_clock); 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Fri, 20 Mar 2026 09:42:03 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Boris Brezillon , Rob Herring , Steven Price , =?UTF-8?q?Adri=C3=A1n=20Larumbe?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Biju Das , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 3/4] drm/panfrost: Add bus_ace optional clock support for RZ/G2L Date: Fri, 20 Mar 2026 16:41:49 +0000 Message-ID: <20260320164158.487406-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260320164158.487406-1-biju.das.jz@bp.renesas.com> References: <20260320164158.487406-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das On RZ/G2L SoCs, the GPU MMU requires a bus_ace clock to operate correctly. Without it, unbind/bind cycles leave the GPU non-operational, manifesting as an AS_ACTIVE bit stuck and a soft reset timeout falling back to hard reset. Add bus_ace_clock as an optional clock, wiring it into init/fini, and the runtime suspend/resume paths alongside the existing optional bus_clock. Reviewed-by: Steven Price Signed-off-by: Biju Das Reviewed-by: Adri=C3=A1n Larumbe --- v1->v2: * Dropped duplicate err assignment * Changed the format string of dev_err to "%d" and simplify the dev_err() line by using err rather than the same PTR_ERR(). * Collected tag --- drivers/gpu/drm/panfrost/panfrost_device.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/panfrost/panfrost_device.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/p= anfrost/panfrost_device.c index 01e702a0b2f0..7fed22d555a5 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -70,8 +70,21 @@ static int panfrost_clk_init(struct panfrost_device *pfd= ev) goto disable_clock; } =20 + pfdev->bus_ace_clock =3D devm_clk_get_optional(pfdev->base.dev, "bus_ace"= ); + if (IS_ERR(pfdev->bus_ace_clock)) { + err =3D PTR_ERR(pfdev->bus_ace_clock); + dev_err(pfdev->base.dev, "get bus_ace_clock failed %d\n", err); + goto disable_bus_clock; + } + + err =3D clk_prepare_enable(pfdev->bus_ace_clock); + if (err) + goto disable_bus_clock; + return 0; =20 +disable_bus_clock: + clk_disable_unprepare(pfdev->bus_clock); disable_clock: clk_disable_unprepare(pfdev->clock); =20 @@ -80,6 +93,7 @@ static int panfrost_clk_init(struct panfrost_device *pfde= v) =20 static void panfrost_clk_fini(struct panfrost_device *pfdev) { + clk_disable_unprepare(pfdev->bus_ace_clock); clk_disable_unprepare(pfdev->bus_clock); clk_disable_unprepare(pfdev->clock); } @@ -432,6 +446,10 @@ static int panfrost_device_runtime_resume(struct devic= e *dev) ret =3D clk_enable(pfdev->bus_clock); if (ret) goto err_bus_clk; + + ret =3D clk_enable(pfdev->bus_ace_clock); + if (ret) + goto err_bus_ace_clk; } =20 panfrost_device_reset(pfdev, true); @@ -439,6 +457,9 @@ static int panfrost_device_runtime_resume(struct device= *dev) =20 return 0; =20 +err_bus_ace_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) + clk_disable(pfdev->bus_clock); err_bus_clk: if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) clk_disable(pfdev->clock); @@ -462,6 +483,7 @@ static int panfrost_device_runtime_suspend(struct devic= e *dev) panfrost_gpu_power_off(pfdev); =20 if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) { + clk_disable(pfdev->bus_ace_clock); clk_disable(pfdev->bus_clock); clk_disable(pfdev->clock); reset_control_assert(pfdev->rstc); diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/p= anfrost/panfrost_device.h index 0f3992412205..ec55c136b1b6 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -136,6 +136,7 @@ struct panfrost_device { void __iomem *iomem; struct clk *clock; struct clk *bus_clock; + struct clk *bus_ace_clock; struct regulator_bulk_data *regulators; struct reset_control *rstc; /* pm_domains for devices with more than one. */ --=20 2.43.0 From nobody Sat Apr 4 04:35:53 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B38163CFF77 for ; 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charset="utf-8" From: Biju Das RZ/G3L SoC is embedded with Mali-G31 GPU system. Add GPU_PM_RT support as it needs to be assert/deassert the reset during suspend/resume. Reviewed-by: Steven Price Signed-off-by: Biju Das Reviewed-by: Adri=C3=A1n Larumbe --- v1->v2: * Collected tag --- drivers/gpu/drm/panfrost/panfrost_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 711f5101aa04..3d0bdba2a474 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -1156,6 +1156,7 @@ static const struct of_device_id dt_match[] =3D { .data =3D &amlogic_data, }, { .compatible =3D "amlogic,meson-g12a-mali", .data =3D &amlogic_data, }, + { .compatible =3D "renesas,r9a08g046-mali", .data =3D &default_pm_rt_data= }, { .compatible =3D "renesas,r9a09g047-mali", .data =3D &default_pm_rt_data= }, { .compatible =3D "arm,mali-t604", .data =3D &default_data, }, { .compatible =3D "arm,mali-t624", .data =3D &default_data, }, --=20 2.43.0