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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , Jonathan Corbet , "Shuah Khan" , Mario Limonciello Subject: [PATCH v3 12/12] Documentation/amd-pstate: Add documentation for amd_pstate_floor_{freq,count} Date: Fri, 20 Mar 2026 20:13:21 +0530 Message-ID: <20260320144321.18543-13-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260320144321.18543-1-gautham.shenoy@amd.com> References: <20260320144321.18543-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|SJ0PR12MB6805:EE_ X-MS-Office365-Filtering-Correlation-Id: 76d5d1d3-4d8f-4e05-04e8-08de868f3000 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: PszIhgmoumIe19jRIyZ8QoTrTiuKmp45v4GPUb/08OAKKe0QWbaJ2BB8M41qlMNZ6owBRyYK4LMyu9aV6xGQuxd1em31mGXfAnHCVXlhD9KVrHD7Sw9pHmHjyQ8RTXE2h138wgavYV1huCo1vuews4+vN9hXbpYNaudZE6HK0izRk7JPJ5Kn14PP1DAPB5sNA71SYDmTCfHfUdDpbo1+L5qpfooF/O1/yNhgxoqJIgjS1InICkCxI4TYoiLi9MjmdOPgSk3DnBRyng8SaTGQ5K6IcUgoDYeGw4hb+1LkR10Y4XdI5KPGvOCwPdpMx7vriSOsGbHm44qoUpLj3xxxnGoLjX+aKseKwW0c/tWdyJjiiz1bB9pSDyJTbcStFPKAA1Jlqt/VcjCkXpD25tOENGBg8R4J3xRZ37bdg1CdORDqHG3crLSz1GHqh05uAN8QYSQn7tI7HhW11nPC9SFKU5mibJ0gtpE1q3jh3WzTAxycVyNH8JDpPA1+unJpY9kRE1CWER9kW1lW/5ii8iTr0kbFoR+ELSfTYqk27Bsb1h3hoW8n61Z8WIJ887tLQOYNvl9tdutyaSYlKXy2jcscV9+E8Q1gmiyxr2oeqez8qdHOg3dQhyoMS4w/eLtFwiztThb2cRzkOqdCK2jWdgr/baOq449ZtVQpPltnsvou3aKbY7snAfcHWfGTlgsbRIM33Pnakhpcra3DEtrz4ERJ2tUTSCZIHUdaiuhzU3fOPqNg65ZLW8XK2GCi+ygfG4O6lRsI6cWcTzrr1jKWDw9rhg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0yF7L7Q1cOAtBRLizDhheAvzn2alJgaKwwYATLfOovxRd80gTi6nILQsOD0tLsUFDkp1Bz3Nb44CEWbhbtUhwA6YylJUFjsGPNPRcKxV4DKZN9mZQiibm3g311tw5tijHI1brDbfFcfafa2kQTrEBbixuWs4BOmepjZFZXQ8l+hgb8aGR82Y0RnTIw+gW8CT87G0cnmSGM+e+b0wIPP26Vf4yjnvhrHoMYwwA2L/AJj4DH9P2IAk3C7mB/1TMPkT+iWFQfxbKe7r5i4igDnWBupFcguCIaUfE4Df++ESJrT8xiuyOwKy0iIkajavlDRINVFbBYN3hc+JOeUqvHy8BZnhIqAY94JL5eesM6OC4bMqBjPFlk4AzCijICdB9SPDnm9mCIXd45sI8JllWOFhrVE46wMoD9lNFZ5NPXQgcTuoLbxdXGcy439XBcKwZFai X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2026 14:44:27.6511 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76d5d1d3-4d8f-4e05-04e8-08de868f3000 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6805 Content-Type: text/plain; charset="utf-8" Add documentation for the sysfs files /sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_freq and /sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_count. Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- Documentation/admin-guide/pm/amd-pstate.rst | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/ad= min-guide/pm/amd-pstate.rst index b31a478c28ba..d6c2f233ab23 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -242,6 +242,8 @@ control its functionality at the system level. They are= located in the /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_hw_prefcore /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_floor_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_floor_count /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_prefcore_ranking =20 =20 @@ -277,6 +279,36 @@ larger numbers are preferred at the time of reading. T= his can change at runtime based on platform conditions. This attribute is read-only. This fi= le is only visible on platforms which support the preferred core feature. =20 +``amd_pstate_floor_freq`` + +The floor frequency associated with each CPU. Userspace can write any +value between ``cpuinfo_min_freq`` and ``scaling_max_freq`` into this +file. When the system is under power or thermal constraints, the +platform firmware will attempt to throttle the CPU frequency to the +value specified in ``amd_pstate_floor_freq`` before throttling it +further. This allows userspace to specify different floor frequencies +to different CPUs. For optimal results, threads of the same core +should have the same floor frequency value. This file is only visible +on platforms that support the CPPC Performance Priority feature. + + +``amd_pstate_floor_count`` + +The number of distinct Floor Performance levels supported by the +platform. For example, if this value is 2, then the number of unique +values obtained from the command ``cat +/sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_freq | +sort -n | uniq`` should be at most this number for the behavior +described in ``amd_pstate_floor_freq`` to take effect. A zero value +implies that the platform supports unlimited floor performance levels. +This file is only visible on platforms that support the CPPC +Performance Priority feature. + +**Note**: When ``amd_pstate_floor_count`` is non-zero, the frequency to +which the CPU is throttled under power or thermal constraints is +undefined when the number of unique values of ``amd_pstate_floor_freq`` +across all CPUs in the system exceeds ``amd_pstate_floor_count``. + ``energy_performance_available_preferences`` =20 A list of all the supported EPP preferences that could be used for --=20 2.34.1