From nobody Fri Apr 3 08:20:43 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 245C33A9D9B for ; Fri, 20 Mar 2026 11:28:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774006133; cv=none; b=B08tAAKLXjju+z3qPSOgvxmmZsgiNRF0sBpzjR5HdZwCD5ZROkwbWtGI66vVPBmkppiOvKgc5eBrttWkXb2Grm84Q7c3d/Fm4CcB0Jn8KpvjVmFoXcxUEnyUU74Lrf/M6zHAH6+Mv/RKZo4Q4CyuHtVjjdkhvVCGezcdzd9ATw4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774006133; c=relaxed/simple; bh=h9pis3uIgjZhaRaP43lEEeFj11msn/IipYbHvWci9FA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UFiKxO1LgoarQvLZnkA+oZqQfusRgzL/SyDcoRfCbEaJNVLA72JOZIzytUl4rH57P9C3+xS+Pik83tUF/No32jPlUIivQJe5ILlBwVY7aUNgPPb1MuW3Cd0b8PM2sCUKP5JKamTZ32TK/RLkkvCReBOWLNSdVzGEl12TlfLHyD4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=bURoJ+pK; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="bURoJ+pK" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4853e1ce427so4882835e9.3 for ; Fri, 20 Mar 2026 04:28:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1774006129; x=1774610929; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/ZMErGYEzh9D7FYJyp2n9bFibDdiom/kkDB/CVaUYJE=; b=bURoJ+pKketoBIokqlwRR5hQUPg0ubQM1wqQj7AG29KxSkBuWkvaKAXOCToFWmok1g JH7sxqpuWMi5X1QslDGEmVolGkv5RT9J6WwcMf2WJMF9qemHN2VoRafI71FgABdoVINw 7E8BlYaKsce0ic12kDLbr5IAaubxUqXuMH8F6kvDvv+MyJ8lFAGck6DOirUj6UAxjNvC 0crt7smAFW4rnXyU/3Nu/EVyOJtWR02T/di2F5DvNIwLNAQU2WFEB9FgPhen+DLuJLq1 Ry9IfMOOSmX70tSPGhiMfwJJ6xuM0ZQyy8UG4hhhd8wLeq+0iJovh9tc2sMTmCLr0wxl cOOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774006129; x=1774610929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=/ZMErGYEzh9D7FYJyp2n9bFibDdiom/kkDB/CVaUYJE=; b=gIK/+GDkNXp8qsNWjHTI4cfGGH4Eb5Hq9c65b9EpTqw0hq35QGmcIpPEE851mX2oOm LXw2lplTuxUO8nhzB886lepuEIP040addKcsY+gY2ait7xKcsPFPDaJXAg4F1dYOZuQt +wEdRF1FVsXDdqdHKuSt1UH4oXKZ0iBsdxRBzDWTO15Pl6sS4MgkkvWzrGRNOjGTu8mM q3+WWD2HeHxk11TsINtKXBbxBWMeHiVm/Op8CZ+NOVwrOAucqxunYvpl8foU0iHP2wPC B171s2Iuf/mn/qYf7eInXWCUYt/CDjNbo44eTtjMPQwSUEWtYnr1QyWmbrO8iCWwhttE P8eA== X-Forwarded-Encrypted: i=1; AJvYcCVqjFBnO3kdzZgxHUlaRLi9030/fMuIjqT7Q28d3kACwGYBNXILFAd1Mmh7Vahqkrlj4wYkswISVmhKlqA=@vger.kernel.org X-Gm-Message-State: AOJu0YyRInkPwPYmYXMUHPe/3BnDO27fSmZSjljCIqVIVuXcYjMDo4SE drRwMVx5h6v+L7HV8bLYhUqvY2YRNpUlx5kxztBVwh1wDwyjyPWB4Z+qgsKamSBousk= X-Gm-Gg: ATEYQzyOzYGelfJ+up6byLCFqB1cxIH3s69jeny5sjsrjpU3YNhXU/7BKBjz1H1wNst Tg/4xPtoNxNKh8fZw6bM4KEtNypexGQm7gRSWtJOaiCG8wrEuWqJS6ev9zTGYfijEPhihJTaA6k KOelYpp7l9qqf4kKPDS32iMmC+kVAkweqd68MFpBR/IK8ELMgUbe1cFiIpXnNs/FytK9MLg6KdE nQT5K67kW+Ge939aC6Va4ApMwcMDA+69+malvJaSr8Hl7vjvQqrW2Ak9tnKSaK8rfL4sUqPL3Sc jY/bARRBdNBuDhWvr0+B12lJw//80hEC3Ly2U5PTLuXu4XHeYSbipcG0S0YAc1tyhUP4+H0khk9 zHWvBFvJ+YPZodh3DtAtAwSttmSHjYaF5SYSA8Ng4o7ORFIGp7lxkdGRNGK/CTRmrdZI39fLRlN aDMfO5F/1VP43I798a974BSCYTkYXh6TilaXeMbD06a92SeX3LuDVF X-Received: by 2002:a05:600c:548e:b0:485:3fa9:358c with SMTP id 5b1f17b1804b1-486ff027c33mr41401235e9.17.1774006129463; Fri, 20 Mar 2026 04:28:49 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.216]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-486fe836784sm49869935e9.13.2026.03.20.04.28.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2026 04:28:48 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, Frank.Li@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, p.zabel@pengutronix.de, geert+renesas@glider.be, fabrizio.castro.jz@renesas.com, john.madieu.xa@bp.renesas.com, kuninori.morimoto.gx@renesas.com, tommaso.merciai.xr@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 4/7] dmaengine: sh: rz-dmac: Add cyclic DMA support Date: Fri, 20 Mar 2026 13:28:35 +0200 Message-ID: <20260320112838.2200198-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260320112838.2200198-1-claudiu.beznea.uj@bp.renesas.com> References: <20260320112838.2200198-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add cyclic DMA support to the RZ DMAC driver. A per-channel status bit is introduced to mark cyclic channels and is set during the DMA prepare callback. The IRQ handler checks this status bit and calls vchan_cyclic_callback() accordingly. Signed-off-by: Claudiu Beznea --- Changes in v2: - none drivers/dma/sh/rz-dmac.c | 137 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 133 insertions(+), 4 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 58446726afb5..ca8c0aa8ae59 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -35,6 +35,7 @@ enum rz_dmac_prep_type { RZ_DMAC_DESC_MEMCPY, RZ_DMAC_DESC_SLAVE_SG, + RZ_DMAC_DESC_CYCLIC, }; =20 struct rz_lmdesc { @@ -59,6 +60,7 @@ struct rz_dmac_desc { /* For slave sg */ struct scatterlist *sg; unsigned int sgcount; + u32 start_lmdesc; }; =20 #define to_rz_dmac_desc(d) container_of(d, struct rz_dmac_desc, vd) @@ -67,10 +69,12 @@ struct rz_dmac_desc { * enum rz_dmac_chan_status: RZ DMAC channel status * @RZ_DMAC_CHAN_STATUS_ENABLED: Channel is enabled * @RZ_DMAC_CHAN_STATUS_PAUSED: Channel is paused though DMA engine callba= cks + * @RZ_DMAC_CHAN_STATUS_CYCLIC: Channel is cyclic */ enum rz_dmac_chan_status { RZ_DMAC_CHAN_STATUS_ENABLED, RZ_DMAC_CHAN_STATUS_PAUSED, + RZ_DMAC_CHAN_STATUS_CYCLIC, }; =20 struct rz_dmac_chan { @@ -194,6 +198,7 @@ struct rz_dmac { =20 /* LINK MODE DESCRIPTOR */ #define HEADER_LV BIT(0) +#define HEADER_WBD BIT(2) =20 #define RZ_DMAC_MAX_CHAN_DESCRIPTORS 16 #define RZ_DMAC_MAX_CHANNELS 16 @@ -419,6 +424,60 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct = rz_dmac_chan *channel) rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); } =20 +static void rz_dmac_prepare_descs_for_cyclic(struct rz_dmac_chan *channel) +{ + struct dma_chan *chan =3D &channel->vc.chan; + struct rz_dmac *dmac =3D to_rz_dmac(chan->device); + struct rz_dmac_desc *d =3D channel->desc; + size_t period_len =3D d->sgcount; + struct rz_lmdesc *lmdesc; + size_t buf_len =3D d->len; + size_t periods =3D buf_len / period_len; + u32 start_lmdesc; + + lockdep_assert_held(&channel->vc.lock); + + channel->chcfg |=3D CHCFG_SEL(channel->index) | CHCFG_DMS; + + if (d->direction =3D=3D DMA_DEV_TO_MEM) { + channel->chcfg |=3D CHCFG_SAD; + channel->chcfg &=3D ~CHCFG_REQD; + } else { + channel->chcfg |=3D CHCFG_DAD | CHCFG_REQD; + } + + lmdesc =3D channel->lmdesc.tail; + start_lmdesc =3D channel->lmdesc.base_dma + + (sizeof(struct rz_lmdesc) * (lmdesc - channel->lmdesc.base)); + d->start_lmdesc =3D start_lmdesc; + + for (size_t i =3D 0; i < periods; i++) { + if (d->direction =3D=3D DMA_DEV_TO_MEM) { + lmdesc->sa =3D d->src; + lmdesc->da =3D d->dest + (i * period_len); + } else { + lmdesc->sa =3D d->src + (i * period_len); + lmdesc->da =3D d->dest; + } + + lmdesc->tb =3D period_len; + lmdesc->chitvl =3D 0; + lmdesc->chext =3D 0; + lmdesc->chcfg =3D channel->chcfg; + lmdesc->header =3D HEADER_LV | HEADER_WBD; + + if (i =3D=3D periods - 1) + lmdesc->nxla =3D start_lmdesc; + + if (++lmdesc >=3D (channel->lmdesc.base + DMAC_NR_LMDESC)) + lmdesc =3D channel->lmdesc.base; + } + + channel->lmdesc.tail =3D lmdesc; + + rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); +} + static int rz_dmac_xfer_desc(struct rz_dmac_chan *chan) { struct rz_dmac_desc *d =3D chan->desc; @@ -439,6 +498,10 @@ static int rz_dmac_xfer_desc(struct rz_dmac_chan *chan) rz_dmac_prepare_descs_for_slave_sg(chan); break; =20 + case RZ_DMAC_DESC_CYCLIC: + rz_dmac_prepare_descs_for_cyclic(chan); + break; + default: return -EINVAL; } @@ -573,6 +636,52 @@ rz_dmac_prep_slave_sg(struct dma_chan *chan, struct sc= atterlist *sgl, return vchan_tx_prep(&channel->vc, &desc->vd, flags); } =20 +static struct dma_async_tx_descriptor * +rz_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction direction, + unsigned long flags) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + size_t periods =3D buf_len / period_len; + struct rz_dmac_desc *desc; + + if (!is_slave_direction(direction)) + return NULL; + + if (periods > DMAC_NR_LMDESC) + return NULL; + + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + if (list_empty(&channel->ld_free)) + return NULL; + + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_CYCLIC)) + return NULL; + + channel->status |=3D BIT(RZ_DMAC_CHAN_STATUS_CYCLIC); + + desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); + + desc->type =3D RZ_DMAC_DESC_CYCLIC; + desc->sgcount =3D period_len; + desc->len =3D buf_len; + desc->direction =3D direction; + + if (direction =3D=3D DMA_DEV_TO_MEM) { + desc->src =3D channel->src_per_address; + desc->dest =3D buf_addr; + } else { + desc->src =3D buf_addr; + desc->dest =3D channel->dst_per_address; + } + + list_move_tail(channel->ld_free.next, &channel->ld_queue); + } + + return vchan_tx_prep(&channel->vc, &desc->vd, flags); +} + static int rz_dmac_terminate_all(struct dma_chan *chan) { struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); @@ -723,9 +832,18 @@ static u32 rz_dmac_calculate_residue_bytes_in_vd(struc= t rz_dmac_chan *channel, u } =20 /* Calculate residue from next lmdesc to end of virtual desc */ - while (lmdesc->chcfg & CHCFG_DEM) { - residue +=3D lmdesc->tb; - lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_CYCLIC)) { + struct rz_dmac_desc *desc =3D channel->desc; + + while (lmdesc->nxla !=3D desc->start_lmdesc) { + residue +=3D lmdesc->tb; + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + } + } else { + while (lmdesc->chcfg & CHCFG_DEM) { + residue +=3D lmdesc->tb; + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + } } =20 dev_dbg(dmac->dev, "%s: VD residue is %u\n", __func__, residue); @@ -964,7 +1082,15 @@ static irqreturn_t rz_dmac_irq_handler_thread(int irq= , void *dev_id) } =20 desc =3D list_first_entry(&channel->ld_active, struct rz_dmac_desc, node); - vchan_cookie_complete(&desc->vd); + + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_CYCLIC)) { + desc =3D channel->desc; + vchan_cyclic_callback(&desc->vd); + goto out; + } else { + vchan_cookie_complete(&desc->vd); + } + list_move_tail(channel->ld_active.next, &channel->ld_free); if (!list_empty(&channel->ld_queue)) { desc =3D list_first_entry(&channel->ld_queue, struct rz_dmac_desc, @@ -1231,6 +1357,8 @@ static int rz_dmac_probe(struct platform_device *pdev) engine =3D &dmac->engine; dma_cap_set(DMA_SLAVE, engine->cap_mask); dma_cap_set(DMA_MEMCPY, engine->cap_mask); + dma_cap_set(DMA_CYCLIC, engine->cap_mask); + engine->directions =3D BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); engine->residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL); rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL); @@ -1242,6 +1370,7 @@ static int rz_dmac_probe(struct platform_device *pdev) engine->device_tx_status =3D rz_dmac_tx_status; engine->device_prep_slave_sg =3D rz_dmac_prep_slave_sg; engine->device_prep_dma_memcpy =3D rz_dmac_prep_dma_memcpy; + engine->device_prep_dma_cyclic =3D rz_dmac_prep_dma_cyclic; engine->device_config =3D rz_dmac_config; engine->device_terminate_all =3D rz_dmac_terminate_all; engine->device_issue_pending =3D rz_dmac_issue_pending; --=20 2.43.0