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([82.78.167.216]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-486fe836784sm49869935e9.13.2026.03.20.04.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2026 04:28:44 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, Frank.Li@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, p.zabel@pengutronix.de, geert+renesas@glider.be, fabrizio.castro.jz@renesas.com, john.madieu.xa@bp.renesas.com, kuninori.morimoto.gx@renesas.com, tommaso.merciai.xr@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 2/7] dmaengine: sh: rz-dmac: Add pause status bit Date: Fri, 20 Mar 2026 13:28:33 +0200 Message-ID: <20260320112838.2200198-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260320112838.2200198-1-claudiu.beznea.uj@bp.renesas.com> References: <20260320112838.2200198-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add the RZ_DMAC_CHAN_STATUS_PAUSED status bit index. This is needed to implement suspend to RAM support for cyclic DMA channels, which will be added in subsequent commits. The pause and resume implementations are updated to be reused by the code that will be added for suspend to RAM handling. Since the pause state is now stored in a per-channel software cache, there is no longer a need to interrogate the hardware registers in the pause path. Using the software status cache simplifies the implementation. The resume code was updated to use the software status cache as well. This is a preparatory commit for cyclic DMA suspend to RAM support. Signed-off-by: Claudiu Beznea --- Changes in v2: - fixed typos in patch description drivers/dma/sh/rz-dmac.c | 68 ++++++++++++++++++++++++++++++---------- 1 file changed, 52 insertions(+), 16 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 8148a1c78e12..32349d214f68 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -65,9 +66,11 @@ struct rz_dmac_desc { /** * enum rz_dmac_chan_status: RZ DMAC channel status * @RZ_DMAC_CHAN_STATUS_ENABLED: Channel is enabled + * @RZ_DMAC_CHAN_STATUS_PAUSED: Channel is paused though DMA engine callba= cks */ enum rz_dmac_chan_status { RZ_DMAC_CHAN_STATUS_ENABLED, + RZ_DMAC_CHAN_STATUS_PAUSED, }; =20 struct rz_dmac_chan { @@ -825,12 +828,9 @@ static enum dma_status rz_dmac_tx_status(struct dma_ch= an *chan, return status; =20 scoped_guard(spinlock_irqsave, &channel->vc.lock) { - u32 val; - residue =3D rz_dmac_chan_get_residue(channel, cookie); =20 - val =3D rz_dmac_ch_readl(channel, CHSTAT, 1); - if (val & CHSTAT_SUS) + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_PAUSED)) status =3D DMA_PAUSED; } =20 @@ -843,35 +843,71 @@ static enum dma_status rz_dmac_tx_status(struct dma_c= han *chan, return status; } =20 -static int rz_dmac_device_pause(struct dma_chan *chan) +static int rz_dmac_device_pause_set(struct rz_dmac_chan *channel, + enum rz_dmac_chan_status status) { - struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); u32 val; + int ret; =20 - guard(spinlock_irqsave)(&channel->vc.lock); + lockdep_assert_held(&channel->vc.lock); =20 if (!(channel->status & BIT(RZ_DMAC_CHAN_STATUS_ENABLED))) return 0; =20 rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); - return read_poll_timeout_atomic(rz_dmac_ch_readl, val, - (val & CHSTAT_SUS), 1, 1024, - false, channel, CHSTAT, 1); + ret =3D read_poll_timeout_atomic(rz_dmac_ch_readl, val, + (val & CHSTAT_SUS), 1, 1024, false, + channel, CHSTAT, 1); + if (ret) + return ret; + + channel->status |=3D BIT(status); + + return 0; } =20 -static int rz_dmac_device_resume(struct dma_chan *chan) +static int rz_dmac_device_pause(struct dma_chan *chan) { struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); - u32 val; =20 guard(spinlock_irqsave)(&channel->vc.lock); =20 - /* Do not check CHSTAT_SUS but rely on HW capabilities. */ + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_PAUSED)) + return 0; + + return rz_dmac_device_pause_set(channel, RZ_DMAC_CHAN_STATUS_PAUSED); +} + +static int rz_dmac_device_resume_set(struct rz_dmac_chan *channel, + enum rz_dmac_chan_status status) +{ + u32 val; + int ret; + + lockdep_assert_held(&channel->vc.lock); + + if (!(channel->status & BIT(RZ_DMAC_CHAN_STATUS_PAUSED))) + return 0; =20 rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1); - return read_poll_timeout_atomic(rz_dmac_ch_readl, val, - !(val & CHSTAT_SUS), 1, 1024, - false, channel, CHSTAT, 1); + ret =3D read_poll_timeout_atomic(rz_dmac_ch_readl, val, + !(val & CHSTAT_SUS), 1, 1024, false, + channel, CHSTAT, 1); + if (ret) + return ret; + + channel->status &=3D ~BIT(status); + + return 0; +} + +static int rz_dmac_device_resume(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + + guard(spinlock_irqsave)(&channel->vc.lock); + + return rz_dmac_device_resume_set(channel, RZ_DMAC_CHAN_STATUS_PAUSED); } =20 /* --=20 2.43.0