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([82.78.167.216]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-486fe836784sm49869935e9.13.2026.03.20.04.28.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2026 04:28:43 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, Frank.Li@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, p.zabel@pengutronix.de, geert+renesas@glider.be, fabrizio.castro.jz@renesas.com, john.madieu.xa@bp.renesas.com, kuninori.morimoto.gx@renesas.com, tommaso.merciai.xr@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 1/7] dmaengine: sh: rz-dmac: Add enable status bit Date: Fri, 20 Mar 2026 13:28:32 +0200 Message-ID: <20260320112838.2200198-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260320112838.2200198-1-claudiu.beznea.uj@bp.renesas.com> References: <20260320112838.2200198-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add a status bitmask to struct rz_dmac_chan. This currently stores only the enable status of the DMA channel and it is a preparatory commit for adding cyclic DMA support. Signed-off-by: Claudiu Beznea --- Changes in v2: - fixed typo in patch description drivers/dma/sh/rz-dmac.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 625ff29024de..8148a1c78e12 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -62,6 +62,14 @@ struct rz_dmac_desc { =20 #define to_rz_dmac_desc(d) container_of(d, struct rz_dmac_desc, vd) =20 +/** + * enum rz_dmac_chan_status: RZ DMAC channel status + * @RZ_DMAC_CHAN_STATUS_ENABLED: Channel is enabled + */ +enum rz_dmac_chan_status { + RZ_DMAC_CHAN_STATUS_ENABLED, +}; + struct rz_dmac_chan { struct virt_dma_chan vc; void __iomem *ch_base; @@ -73,6 +81,8 @@ struct rz_dmac_chan { dma_addr_t src_per_address; dma_addr_t dst_per_address; =20 + unsigned long status; + u32 chcfg; u32 chctrl; int mid_rid; @@ -295,6 +305,8 @@ static void rz_dmac_enable_hw(struct rz_dmac_chan *chan= nel) rz_dmac_ch_writel(channel, channel->chcfg, CHCFG, 1); rz_dmac_ch_writel(channel, CHCTRL_SWRST, CHCTRL, 1); rz_dmac_ch_writel(channel, chctrl, CHCTRL, 1); + + channel->status |=3D BIT(RZ_DMAC_CHAN_STATUS_ENABLED); } } =20 @@ -306,6 +318,8 @@ static void rz_dmac_disable_hw(struct rz_dmac_chan *cha= nnel) dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); =20 rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); + + channel->status &=3D ~BIT(RZ_DMAC_CHAN_STATUS_ENABLED); } =20 static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 d= mars) @@ -571,6 +585,9 @@ static int rz_dmac_terminate_all(struct dma_chan *chan) list_splice_tail_init(&channel->ld_active, &channel->ld_free); list_splice_tail_init(&channel->ld_queue, &channel->ld_free); vchan_get_all_descriptors(&channel->vc, &head); + + channel->status =3D 0; + spin_unlock_irqrestore(&channel->vc.lock, flags); vchan_dma_desc_free_list(&channel->vc, &head); =20 @@ -833,8 +850,7 @@ static int rz_dmac_device_pause(struct dma_chan *chan) =20 guard(spinlock_irqsave)(&channel->vc.lock); =20 - val =3D rz_dmac_ch_readl(channel, CHSTAT, 1); - if (!(val & CHSTAT_EN)) + if (!(channel->status & BIT(RZ_DMAC_CHAN_STATUS_ENABLED))) return 0; =20 rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); @@ -874,8 +890,10 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_= chan *channel) dev_err(dmac->dev, "DMAC err CHSTAT_%d =3D %08X\n", channel->index, chstat); =20 - scoped_guard(spinlock_irqsave, &channel->vc.lock) + scoped_guard(spinlock_irqsave, &channel->vc.lock) { rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); + channel->status &=3D ~BIT(RZ_DMAC_CHAN_STATUS_ENABLED); + } return; } =20 --=20 2.43.0