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Fri, 20 Mar 2026 04:13:19 -0700 (PDT) Received: from aldo-conte-t14.tailf68ad9.ts.net ([217.61.173.50]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b644ae37dsm5573954f8f.2.2026.03.20.04.13.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2026 04:13:19 -0700 (PDT) From: Aldo Conte To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, tglx@kernel.org, bp@alien8.de, dave.hansen@linux.intel.com Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, james.clark@linaro.org, hpa@zytor.com, x86@kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, skhan@linuxfoundation.org Subject: [PATCH v2] perf/x86/intel/p4: Fix unused variable warning in p4_pmu_init() Date: Fri, 20 Mar 2026 12:13:18 +0100 Message-ID: <20260320111318.280636-1-aldocontelk@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Build the kernel with make W=3D1 generates the following warning: arch/x86/events/intel/p4.c: In function =E2=80=98p4_pmu_init=E2=80=99: arch/x86/events/intel/p4.c:1370:27: error: variable =E2=80=98high=E2=80= =99 set but not used [-Werror=3Dunused-but-set-variable] 1370 | unsigned int low, high; | ^~~~ This happens because, although both variables are declared and initialized by rdmsr, only `low` is used in the subsequent if statement. This patch uses the rdmsrq() macro instead of the rdmsr() macro. The rdmsrq() macro avoids the use of high and low variables because it reads the msr value in a single u64 variable. Also, replace (1 << 7) with the proper macro. Running `make W=3D1` again resolves the error. I was unable to test the patch because i do not have the hardware. Suggested-by: Dave Hansen Signed-off-by: Aldo Conte --- v2:=20 - Use of rdmsrq() instead of rdmsr() to read the full 64-bit MSR in one single read avoiding the use of high and low. - Replace (1 << 7) with the MSR_IA32_MISC_ENABLE_EMON - Remove pr_cont() with MSR printout added in the previous patch v1: https://lore.kernel.org/all/20260319152210.210854-1-aldocontelk@gmail.c= om/ arch/x86/events/intel/p4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/p4.c b/arch/x86/events/intel/p4.c index e5fd7367e45d..02bfdb77158b 100644 --- a/arch/x86/events/intel/p4.c +++ b/arch/x86/events/intel/p4.c @@ -1367,14 +1367,14 @@ static __initconst const struct x86_pmu p4_pmu =3D { =20 __init int p4_pmu_init(void) { - unsigned int low, high; + unsigned int misc; int i, reg; =20 /* If we get stripped -- indexing fails */ BUILD_BUG_ON(ARCH_P4_MAX_CCCR > INTEL_PMC_MAX_GENERIC); =20 - rdmsr(MSR_IA32_MISC_ENABLE, low, high); - if (!(low & (1 << 7))) { + rdmsrq(MSR_IA32_MISC_ENABLE, misc); + if (!(misc & MSR_IA32_MISC_ENABLE_EMON)) { pr_cont("unsupported Netburst CPU model %d ", boot_cpu_data.x86_model); return -ENODEV; --=20 2.53.0