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Fri, 20 Mar 2026 03:49:55 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Biju Das , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v7 06/10] clk: renesas: Add support for RZ/G3L SoC Date: Fri, 20 Mar 2026 10:49:40 +0000 Message-ID: <20260320104950.42220-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260320104950.42220-1-biju.das.jz@bp.renesas.com> References: <20260320104950.42220-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The clock structure for RZ/G3L is almost identical to that of the RZ/G3S SoC with more IP blocks such as LCDC, CRU, LVDS, and GPU. Add minimal clock and reset entries required to boot the system on Renesas RZ/G3L SMARC EVK and bind it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das --- v6->v7: * Replaced r9a08g046_critical_resets->r9a08g046_crit_resets v5->v6: * No change=20 v4->v5: * No change v3->v4: * Updated commit description * Updated LAST_DT_CORE_CLK with R9A08G046_USB_SCLK * Fixed typo 2->8 in dtable_4_128[]. * Added critical reset table r9a08g046_critical_resets[] * Updated num_resets * Added crit_resets and num_crit_resets to r9a08g046_cpg_info. v2->v3: * No change. v1->v2: * Added CLK_ETH{0,1}_TXC_TX_CLK_IN and CLK_ETH{0,1}_RXC_RX_CLK_IN clocks. * Dropped R9A08G046_IA55_PCLK from critical clock list. --- drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a08g046-cpg.c | 153 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 6 ++ drivers/clk/renesas/rzg2l-cpg.h | 1 + 5 files changed, 167 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/renesas/r9a08g046-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 6a5a04664990..0203ecbb3882 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -39,6 +39,7 @@ config CLK_RENESAS select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_R9A08G045 if ARCH_R9A08G045 + select CLK_R9A08G046 if ARCH_R9A08G046 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_R9A09G047 if ARCH_R9A09G047 select CLK_R9A09G056 if ARCH_R9A09G056 @@ -194,6 +195,10 @@ config CLK_R9A08G045 bool "RZ/G3S clock support" if COMPILE_TEST select CLK_RZG2L =20 +config CLK_R9A08G046 + bool "RZ/G3L clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_R9A09G011 bool "RZ/V2M clock support" if COMPILE_TEST select CLK_RZG2L @@ -250,7 +255,7 @@ config CLK_RCAR_USB2_CLOCK_SEL This is a driver for R-Car USB2 clock selector =20 config CLK_RZG2L - bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST + bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER =20 config CLK_RZV2H diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index d28eb276a153..bd2bed91ab29 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G043) +=3D r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) +=3D r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) +=3D r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) +=3D r9a08g045-cpg.o +obj-$(CONFIG_CLK_R9A08G046) +=3D r9a08g046-cpg.o obj-$(CONFIG_CLK_R9A09G011) +=3D r9a09g011-cpg.o obj-$(CONFIG_CLK_R9A09G047) +=3D r9a09g047-cpg.o obj-$(CONFIG_CLK_R9A09G056) +=3D r9a09g056-cpg.o diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c new file mode 100644 index 000000000000..6c77afdd34ea --- /dev/null +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3L CPG driver + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzg2l-cpg.h" + +/* RZ/G3L Specific registers. */ +#define G3L_CPG_PL2_DDIV (0x204) +#define G3L_CPG_PL3_DDIV (0x208) +#define G3L_CLKDIVSTATUS (0x280) + +/* RZ/G3L Specific division configuration. */ +#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2) +#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2) +#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2) + +/* RZ/G3L Clock status configuration. */ +#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1) +#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) +#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK =3D R9A08G046_USB_SCLK, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_ETH0_TXC_TX_CLK_IN, + CLK_ETH0_RXC_RX_CLK_IN, + CLK_ETH1_TXC_TX_CLK_IN, + CLK_ETH1_RXC_RX_CLK_IN, + + /* Internal Core Clocks */ + CLK_PLL2, + CLK_PLL2_DIV2, + CLK_PLL3, + CLK_PLL3_DIV2, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +/* Divider tables */ +static const struct clk_div_table dtable_4_128[] =3D { + { 0, 4 }, + { 1, 8 }, + { 2, 16 }, + { 3, 128 }, + { 0, 0 }, +}; + +static const struct clk_div_table dtable_8_256[] =3D { + { 0, 8 }, + { 1, 16 }, + { 2, 32 }, + { 3, 256 }, + { 0, 0 }, +}; + +static const struct cpg_core_clk r9a08g046_core_clks[] __initconst =3D { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN), + DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN), + DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN), + DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN), + + /* Internal Core Clocks */ + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + + /* Core output clk */ + DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL= 2B_STS, + dtable_8_256, 0, 0, 0, NULL), + DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL= 3A_STS, + dtable_4_128, 0, 0, 0, NULL), + DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL= 2A_STS, + dtable_4_128, 0, 0, 0, NULL), +}; + +static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { + DEF_MOD("gic_gicclk", R9A08G046_GIC600_GICCLK, R9A08G046_CLK_P1, 0x514, = 0, + MSTOP(BUS_PERI_COM, BIT(12))), + DEF_MOD("ia55_pclk", R9A08G046_IA55_PCLK, R9A08G046_CLK_P0, 0x518, 0, + MSTOP(BUS_PERI_CPU, BIT(13))), + DEF_MOD("ia55_clk", R9A08G046_IA55_CLK, R9A08G046_CLK_P1, 0x518, 1, + MSTOP(BUS_PERI_CPU, BIT(13))), + DEF_MOD("dmac_aclk", R9A08G046_DMAC_ACLK, R9A08G046_CLK_P3, 0x52c, 0, + MSTOP(BUS_REG1, BIT(2))), + DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1, + MSTOP(BUS_REG1, BIT(3))), + DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584= , 0, + MSTOP(BUS_MCPU2, BIT(1))), +}; + +static const struct rzg2l_reset r9a08g046_resets[] =3D { + DEF_RST(R9A08G046_GIC600_GICRESET_N, 0x814, 0), + DEF_RST(R9A08G046_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0), + DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0), + DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0), +}; + +static const unsigned int r9a08g046_crit_mod_clks[] __initconst =3D { + MOD_CLK_BASE + R9A08G046_GIC600_GICCLK, + MOD_CLK_BASE + R9A08G046_IA55_CLK, + MOD_CLK_BASE + R9A08G046_DMAC_ACLK, +}; + +static const unsigned int r9a08g046_crit_resets[] =3D { + R9A08G046_DMAC_ARESETN, + R9A08G046_DMAC_RST_ASYNC, +}; + +const struct rzg2l_cpg_info r9a08g046_cpg_info =3D { + /* Core Clocks */ + .core_clks =3D r9a08g046_core_clks, + .num_core_clks =3D ARRAY_SIZE(r9a08g046_core_clks), + .last_dt_core_clk =3D LAST_DT_CORE_CLK, + .num_total_core_clks =3D MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks =3D r9a08g046_crit_mod_clks, + .num_crit_mod_clks =3D ARRAY_SIZE(r9a08g046_crit_mod_clks), + + /* Module Clocks */ + .mod_clks =3D r9a08g046_mod_clks, + .num_mod_clks =3D ARRAY_SIZE(r9a08g046_mod_clks), + .num_hw_mod_clks =3D R9A08G046_BSC_X_BCK_BSC + 1, + + /* Resets */ + .resets =3D r9a08g046_resets, + .num_resets =3D R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */ + + /* Critical Resets */ + .crit_resets =3D r9a08g046_crit_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a08g046_crit_resets), + + .has_clk_mon_regs =3D true, +}; diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 038b3f8e85a1..a510a4d32924 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -2144,6 +2144,12 @@ static const struct of_device_id rzg2l_cpg_match[] = =3D { .data =3D &r9a08g045_cpg_info, }, #endif +#ifdef CONFIG_CLK_R9A08G046 + { + .compatible =3D "renesas,r9a08g046-cpg", + .data =3D &r9a08g046_cpg_info, + }, +#endif #ifdef CONFIG_CLK_R9A09G011 { .compatible =3D "renesas,r9a09g011-cpg", diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index af0a003d93f7..10baf9e71a6e 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -316,6 +316,7 @@ extern const struct rzg2l_cpg_info r9a07g043_cpg_info; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; extern const struct rzg2l_cpg_info r9a07g054_cpg_info; extern const struct rzg2l_cpg_info r9a08g045_cpg_info; +extern const struct rzg2l_cpg_info r9a08g046_cpg_info; extern const struct rzg2l_cpg_info r9a09g011_cpg_info; =20 int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long= event, void *data); --=20 2.43.0