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Fri, 20 Mar 2026 03:49:53 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v7 02/10] clk: renesas: rzg2l-cpg: Add support for critical resets Date: Fri, 20 Mar 2026 10:49:36 +0000 Message-ID: <20260320104950.42220-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260320104950.42220-1-biju.das.jz@bp.renesas.com> References: <20260320104950.42220-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Some reset lines must remain deasserted at all times after boot, as asserting them would disable critical system functionality with no owning driver to restore them. This mirrors the existing crit_mod_clks mechanism which protects critical module clocks from being disabled. On RZ/G2L family SoCs, the DMA reset must be remain deasserted for routing some peripheral interrupts to CPU. Add crit_resets and num_crit_resets fields to struct rzg2l_cpg_info to allow SoC-specific data tables to declare reset IDs that must never be asserted. Introduce rzg2l_cpg_deassert_crit_resets() to iterate over all critical resets and deassert them. Call it both at probe time and during resume to ensure critical peripherals are held out of reset after power-on and suspend/resume cycles. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v6->v7: * No change v5->v6: * Moved loop variable declaration inside for loops in __rzg2l_cpg_assert() and rzg2l_cpg_deassert_crit_resets() * Collected tag v4->v5: * No change v4: * Moved this patch from [1] as it is boot-dependent [1] https://lore.kernel.org/all/20260306134228.871815-1-biju.das.jz@bp.ren= esas.com/ --- drivers/clk/renesas/rzg2l-cpg.c | 30 ++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 7 +++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index c0584bab58a3..f9e4af7f49d0 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1765,6 +1765,13 @@ static int __rzg2l_cpg_assert(struct reset_controlle= r_dev *rcdev, dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n", assert ? "assert" : "deassert", id, CLK_RST_R(reg)); =20 + if (assert) { + for (unsigned int i =3D 0; i < priv->info->num_crit_resets; i++) { + if (id =3D=3D priv->info->crit_resets[i]) + return 0; + } + } + if (!assert) value |=3D mask; writel(value, priv->base + CLK_RST_R(reg)); @@ -1802,6 +1809,20 @@ static int rzg2l_cpg_deassert(struct reset_controlle= r_dev *rcdev, return __rzg2l_cpg_assert(rcdev, id, false); } =20 +static int rzg2l_cpg_deassert_crit_resets(struct reset_controller_dev *rcd= ev, + const struct rzg2l_cpg_info *info) +{ + int ret; + + for (unsigned int i =3D 0; i < info->num_crit_resets; i++) { + ret =3D rzg2l_cpg_deassert(rcdev, info->crit_resets[i]); + if (ret) + return ret; + } + + return 0; +} + static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, unsigned long id) { @@ -2051,6 +2072,10 @@ static int __init rzg2l_cpg_probe(struct platform_de= vice *pdev) if (error) return error; =20 + error =3D rzg2l_cpg_deassert_crit_resets(&priv->rcdev, info); + if (error) + return error; + debugfs_create_file("mstop", 0444, NULL, priv, &rzg2l_mod_clock_mstop_fop= s); return 0; } @@ -2058,6 +2083,11 @@ static int __init rzg2l_cpg_probe(struct platform_de= vice *pdev) static int rzg2l_cpg_resume(struct device *dev) { struct rzg2l_cpg_priv *priv =3D dev_get_drvdata(dev); + int ret; + + ret =3D rzg2l_cpg_deassert_crit_resets(&priv->rcdev, priv->info); + if (ret) + return ret; =20 rzg2l_mod_clock_init_mstop(priv); =20 diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 55e815be16c8..af0a003d93f7 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -276,6 +276,9 @@ struct rzg2l_reset { * @crit_mod_clks: Array with Module Clock IDs of critical clocks that * should not be disabled without a knowledgeable driver * @num_crit_mod_clks: Number of entries in crit_mod_clks[] + * @crit_resets: Array with Reset IDs of critical resets that should not be + * asserted without a knowledgeable driver + * @num_crit_resets: Number of entries in crit_resets[] * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers */ struct rzg2l_cpg_info { @@ -302,6 +305,10 @@ struct rzg2l_cpg_info { const unsigned int *crit_mod_clks; unsigned int num_crit_mod_clks; =20 + /* Critical Resets that should not be asserted */ + const unsigned int *crit_resets; + unsigned int num_crit_resets; + bool has_clk_mon_regs; }; =20 --=20 2.43.0