From nobody Sat Apr 4 07:51:21 2026 Received: from canpmsgout12.his.huawei.com (canpmsgout12.his.huawei.com [113.46.200.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B4BF38E5F7; Fri, 20 Mar 2026 10:41:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774003276; cv=none; b=dOZLerrqGMqMy884U4acrc9dE4AuTPr4AsJZIedS8ck7F7hBgy0RFfPvv7e7bCf3JK0HDtH0pvM+6kYsU4/FNphlyqtN25lwI8GwXvlsj/cnhSfoKKRpo8kvX9WGbg7wAKgl8t24VhhlRebQVk4YZa41b5UZWXapV5xc9RISIss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774003276; c=relaxed/simple; bh=73ahRz1Fz7U16vUCmobH9Jf4VbRXY+7dc+vDFyNydkg=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WJqjzYO8wX+cPuRyMLqhLOuDSAILISZTTceWBqCtc1IB0wsuvQ9jwO+wx+OYIboqZItlIUoFDcCUcyTMOeGUa4BUfJ/+eqIbCjYz4+iy9jDPgJ7hk+yD8a4e9tzJ3LqJpbjJUDP7QAdoo8tgVZ48yDW8YhxTvXdBRqEXd6tGhRs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=NWK77cO8; arc=none smtp.client-ip=113.46.200.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="NWK77cO8" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=bGLRd4d7yQ3H+9TIHcIPsE85mcc6keddmlE/BpghkFU=; b=NWK77cO8Yv/ZtTPldvzb/QPdz3/CFVRwIXgRoyC/BtjPaQFYhCnQGJkmDAWaLGUhVQ/lGhCyv IheC3FMs33YD/DqemB5CErNwP9ig8m92kioE8MQhepZMcOi9/13KYqlNPXhZDZ4Pv6gHmPkYj1O PzjCePBUSLHfBS3XFb13SYw= Received: from mail.maildlp.com (unknown [172.19.163.127]) by canpmsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4fcf994STHznTWn; Fri, 20 Mar 2026 18:35:41 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 2467A402AB; Fri, 20 Mar 2026 18:41:12 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 20 Mar 2026 18:41:09 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v14 1/4] s390: Rename TIF_SINGLE_STEP to TIF_SINGLESTEP Date: Fri, 20 Mar 2026 18:42:19 +0800 Message-ID: <20260320104222.1381274-2-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260320104222.1381274-1-ruanjinjie@huawei.com> References: <20260320104222.1381274-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Rename TIF_SINGLE_STEP to TIF_SINGLESTEP to align with the naming convention used by arm64, x86, and other architectures. By aligning the name, TIF_SINGLESTEP can be consolidated into the generic TIF bits definitions, reducing architectural divergence and simplifying cross-architecture entry/exit logic. No functional changes intended. Reviewed-by: Kevin Brodsky Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun Acked-by: Heiko Carstens Signed-off-by: Jinjie Ruan --- arch/s390/include/asm/thread_info.h | 4 ++-- arch/s390/kernel/process.c | 2 +- arch/s390/kernel/ptrace.c | 20 ++++++++++---------- arch/s390/kernel/signal.c | 6 +++--- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/th= read_info.h index 6a548a819400..1bcd42614e41 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -69,7 +69,7 @@ void arch_setup_new_exec(void); #define TIF_GUARDED_STORAGE 17 /* load guarded storage control block */ #define TIF_ISOLATE_BP_GUEST 18 /* Run KVM guests with isolated BP */ #define TIF_PER_TRAP 19 /* Need to handle PER trap on exit to usermode */ -#define TIF_SINGLE_STEP 21 /* This task is single stepped */ +#define TIF_SINGLESTEP 21 /* This task is single stepped */ #define TIF_BLOCK_STEP 22 /* This task is block stepped */ #define TIF_UPROBE_SINGLESTEP 23 /* This task is uprobe single stepped */ =20 @@ -77,7 +77,7 @@ void arch_setup_new_exec(void); #define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE) #define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST) #define _TIF_PER_TRAP BIT(TIF_PER_TRAP) -#define _TIF_SINGLE_STEP BIT(TIF_SINGLE_STEP) +#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_BLOCK_STEP BIT(TIF_BLOCK_STEP) #define _TIF_UPROBE_SINGLESTEP BIT(TIF_UPROBE_SINGLESTEP) =20 diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index 0df95dcb2101..3accc0c064a0 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -122,7 +122,7 @@ int copy_thread(struct task_struct *p, const struct ker= nel_clone_args *args) /* Don't copy debug registers */ memset(&p->thread.per_user, 0, sizeof(p->thread.per_user)); memset(&p->thread.per_event, 0, sizeof(p->thread.per_event)); - clear_tsk_thread_flag(p, TIF_SINGLE_STEP); + clear_tsk_thread_flag(p, TIF_SINGLESTEP); p->thread.per_flags =3D 0; /* Initialize per thread user and system timer values */ p->thread.user_timer =3D 0; diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index 125ca4c4e30c..d2cf91f4ac3f 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c @@ -90,8 +90,8 @@ void update_cr_regs(struct task_struct *task) new.start.val =3D thread->per_user.start; new.end.val =3D thread->per_user.end; =20 - /* merge TIF_SINGLE_STEP into user specified PER registers. */ - if (test_tsk_thread_flag(task, TIF_SINGLE_STEP) || + /* merge TIF_SINGLESTEP into user specified PER registers. */ + if (test_tsk_thread_flag(task, TIF_SINGLESTEP) || test_tsk_thread_flag(task, TIF_UPROBE_SINGLESTEP)) { if (test_tsk_thread_flag(task, TIF_BLOCK_STEP)) new.control.val |=3D PER_EVENT_BRANCH; @@ -119,18 +119,18 @@ void update_cr_regs(struct task_struct *task) void user_enable_single_step(struct task_struct *task) { clear_tsk_thread_flag(task, TIF_BLOCK_STEP); - set_tsk_thread_flag(task, TIF_SINGLE_STEP); + set_tsk_thread_flag(task, TIF_SINGLESTEP); } =20 void user_disable_single_step(struct task_struct *task) { clear_tsk_thread_flag(task, TIF_BLOCK_STEP); - clear_tsk_thread_flag(task, TIF_SINGLE_STEP); + clear_tsk_thread_flag(task, TIF_SINGLESTEP); } =20 void user_enable_block_step(struct task_struct *task) { - set_tsk_thread_flag(task, TIF_SINGLE_STEP); + set_tsk_thread_flag(task, TIF_SINGLESTEP); set_tsk_thread_flag(task, TIF_BLOCK_STEP); } =20 @@ -143,7 +143,7 @@ void ptrace_disable(struct task_struct *task) { memset(&task->thread.per_user, 0, sizeof(task->thread.per_user)); memset(&task->thread.per_event, 0, sizeof(task->thread.per_event)); - clear_tsk_thread_flag(task, TIF_SINGLE_STEP); + clear_tsk_thread_flag(task, TIF_SINGLESTEP); clear_tsk_thread_flag(task, TIF_PER_TRAP); task->thread.per_flags =3D 0; } @@ -155,19 +155,19 @@ static inline unsigned long __peek_user_per(struct ta= sk_struct *child, { if (addr =3D=3D offsetof(struct per_struct_kernel, cr9)) /* Control bits of the active per set. */ - return test_thread_flag(TIF_SINGLE_STEP) ? + return test_thread_flag(TIF_SINGLESTEP) ? PER_EVENT_IFETCH : child->thread.per_user.control; else if (addr =3D=3D offsetof(struct per_struct_kernel, cr10)) /* Start address of the active per set. */ - return test_thread_flag(TIF_SINGLE_STEP) ? + return test_thread_flag(TIF_SINGLESTEP) ? 0 : child->thread.per_user.start; else if (addr =3D=3D offsetof(struct per_struct_kernel, cr11)) /* End address of the active per set. */ - return test_thread_flag(TIF_SINGLE_STEP) ? + return test_thread_flag(TIF_SINGLESTEP) ? -1UL : child->thread.per_user.end; else if (addr =3D=3D offsetof(struct per_struct_kernel, bits)) /* Single-step bit. */ - return test_thread_flag(TIF_SINGLE_STEP) ? + return test_thread_flag(TIF_SINGLESTEP) ? (1UL << (BITS_PER_LONG - 1)) : 0; else if (addr =3D=3D offsetof(struct per_struct_kernel, starting_addr)) /* Start address of the user specified per set. */ diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c index 4874de5edea0..83f7650f2032 100644 --- a/arch/s390/kernel/signal.c +++ b/arch/s390/kernel/signal.c @@ -423,7 +423,7 @@ static void handle_signal(struct ksignal *ksig, sigset_= t *oldset, else ret =3D setup_frame(ksig->sig, &ksig->ka, oldset, regs); =20 - signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLE_STEP)); + signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP)); } =20 /* @@ -491,7 +491,7 @@ void arch_do_signal_or_restart(struct pt_regs *regs) regs->gprs[2] =3D regs->orig_gpr2; current->restart_block.arch_data =3D regs->psw.addr; regs->psw.addr =3D VDSO_SYMBOL(current, restart_syscall); - if (test_thread_flag(TIF_SINGLE_STEP)) + if (test_thread_flag(TIF_SINGLESTEP)) clear_thread_flag(TIF_PER_TRAP); break; case -ERESTARTNOHAND: @@ -499,7 +499,7 @@ void arch_do_signal_or_restart(struct pt_regs *regs) case -ERESTARTNOINTR: regs->gprs[2] =3D regs->orig_gpr2; regs->psw.addr =3D __rewind_psw(regs->psw, regs->int_code >> 16); - if (test_thread_flag(TIF_SINGLE_STEP)) + if (test_thread_flag(TIF_SINGLESTEP)) clear_thread_flag(TIF_PER_TRAP); break; } --=20 2.34.1 From nobody Sat Apr 4 07:51:21 2026 Received: from canpmsgout04.his.huawei.com (canpmsgout04.his.huawei.com [113.46.200.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1165396B82; Fri, 20 Mar 2026 10:41:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.219 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774003279; cv=none; b=Ro3axsQybtJt0fq/S0VG4ln7kSzJolXq/Z3awyjAPJ5FrQZQM4ejWg2CyuEZXxBX8Lit/kVlLBqzoUMgBxtfmM7/7egKJOP92IaRHJLhJlmkAmwOaYcDavpOCC+bEq4sgFkFJTZFgxQvWZt+det7kDdXb47gRTDzOY2luKNwSG8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774003279; c=relaxed/simple; bh=uqtoHEnKrMD9AOu+mT4dlXzcrCRXLOUQPqRC1csUNWg=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qPKTUHWIVxbDIOTqndqi8K2i0wwM3x82t7L+eMLySSsCA19jfJl28TisgwZPokkjZ3KKoMpZFo+zWxZSMShH6uNBlamOzGa6lUqLEu28v40caYMzG9PjZlrH4JuUn8NXd+TyENb9EFNK+udF3TzX6AejC59yydUe/aULY75pq38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=uMw8JNjJ; arc=none smtp.client-ip=113.46.200.219 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="uMw8JNjJ" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=RlEOjT/JGfRsNSEE+lFWaeBcRGitlwJLE3NLIWJLUhs=; b=uMw8JNjJm65egx8filgcNYg+xKS4KD2QlOiXufHgPtmQQNWs5nElNcRPJeDAQVRhk1bMjzXuB a55fTFogezyM4v2x6cA/PsKiAVNz7sVdOjDJOK3nA3hE5c3p1iPUba8osxw9Vri65Hu/XjBkfXQ 253FJOp1+Iru6/z1DHnHERU= Received: from mail.maildlp.com (unknown [172.19.163.104]) by canpmsgout04.his.huawei.com (SkyGuard) with ESMTPS id 4fcf9l1hTJz1prLS; Fri, 20 Mar 2026 18:36:11 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 471C3404AD; Fri, 20 Mar 2026 18:41:14 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 20 Mar 2026 18:41:12 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v14 2/4] asm-generic: Move TIF_SINGLESTEP to generic TIF bits Date: Fri, 20 Mar 2026 18:42:20 +0800 Message-ID: <20260320104222.1381274-3-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260320104222.1381274-1-ruanjinjie@huawei.com> References: <20260320104222.1381274-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Currently, x86, ARM64, s390, and LoongArch all define and use TIF_SINGLESTEP to track single-stepping state. Since this flag is shared across multiple major architectures and serves a common purpose in the generic entry/exit paths, move TIF_SINGLESTEP into the generic Thread Information Flags (TIF) infrastructure. This consolidation reduces architecture-specific boilerplate code and ensures consistency for generic features that rely on single-step state tracking. Cc: Thomas Gleixner Reviewed-by: Kevin Brodsky Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun Acked-by: Heiko Carstens # s390 Signed-off-by: Jinjie Ruan --- arch/loongarch/include/asm/thread_info.h | 11 +++++------ arch/s390/include/asm/thread_info.h | 7 +++---- arch/x86/include/asm/thread_info.h | 6 ++---- include/asm-generic/thread_info_tif.h | 5 +++++ 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/loongarch/include/asm/thread_info.h b/arch/loongarch/incl= ude/asm/thread_info.h index 4d7117fcdc78..a2ec87f18e1d 100644 --- a/arch/loongarch/include/asm/thread_info.h +++ b/arch/loongarch/include/asm/thread_info.h @@ -70,6 +70,7 @@ register unsigned long current_stack_pointer __asm__("$sp= "); */ #define HAVE_TIF_NEED_RESCHED_LAZY #define HAVE_TIF_RESTORE_SIGMASK +#define HAVE_TIF_SINGLESTEP =20 #include =20 @@ -82,11 +83,10 @@ register unsigned long current_stack_pointer __asm__("$= sp"); #define TIF_32BIT_REGS 21 /* 32-bit general purpose registers */ #define TIF_32BIT_ADDR 22 /* 32-bit address space */ #define TIF_LOAD_WATCH 23 /* If set, load watch registers */ -#define TIF_SINGLESTEP 24 /* Single Step */ -#define TIF_LSX_CTX_LIVE 25 /* LSX context must be preserved */ -#define TIF_LASX_CTX_LIVE 26 /* LASX context must be preserved */ -#define TIF_USEDLBT 27 /* LBT was used by this task this quantum (SMP) */ -#define TIF_LBT_CTX_LIVE 28 /* LBT context must be preserved */ +#define TIF_LSX_CTX_LIVE 24 /* LSX context must be preserved */ +#define TIF_LASX_CTX_LIVE 25 /* LASX context must be preserved */ +#define TIF_USEDLBT 26 /* LBT was used by this task this quantum (SMP) */ +#define TIF_LBT_CTX_LIVE 27 /* LBT context must be preserved */ =20 #define _TIF_NOHZ BIT(TIF_NOHZ) #define _TIF_USEDFPU BIT(TIF_USEDFPU) @@ -96,7 +96,6 @@ register unsigned long current_stack_pointer __asm__("$sp= "); #define _TIF_32BIT_REGS BIT(TIF_32BIT_REGS) #define _TIF_32BIT_ADDR BIT(TIF_32BIT_ADDR) #define _TIF_LOAD_WATCH BIT(TIF_LOAD_WATCH) -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_LSX_CTX_LIVE BIT(TIF_LSX_CTX_LIVE) #define _TIF_LASX_CTX_LIVE BIT(TIF_LASX_CTX_LIVE) #define _TIF_USEDLBT BIT(TIF_USEDLBT) diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/th= read_info.h index 1bcd42614e41..95be5258a422 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -61,6 +61,7 @@ void arch_setup_new_exec(void); */ #define HAVE_TIF_NEED_RESCHED_LAZY #define HAVE_TIF_RESTORE_SIGMASK +#define HAVE_TIF_SINGLESTEP =20 #include =20 @@ -69,15 +70,13 @@ void arch_setup_new_exec(void); #define TIF_GUARDED_STORAGE 17 /* load guarded storage control block */ #define TIF_ISOLATE_BP_GUEST 18 /* Run KVM guests with isolated BP */ #define TIF_PER_TRAP 19 /* Need to handle PER trap on exit to usermode */ -#define TIF_SINGLESTEP 21 /* This task is single stepped */ -#define TIF_BLOCK_STEP 22 /* This task is block stepped */ -#define TIF_UPROBE_SINGLESTEP 23 /* This task is uprobe single stepped */ +#define TIF_BLOCK_STEP 20 /* This task is block stepped */ +#define TIF_UPROBE_SINGLESTEP 21 /* This task is uprobe single stepped */ =20 #define _TIF_ASCE_PRIMARY BIT(TIF_ASCE_PRIMARY) #define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE) #define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST) #define _TIF_PER_TRAP BIT(TIF_PER_TRAP) -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_BLOCK_STEP BIT(TIF_BLOCK_STEP) #define _TIF_UPROBE_SINGLESTEP BIT(TIF_UPROBE_SINGLESTEP) =20 diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thre= ad_info.h index 0067684afb5b..f59072ba1473 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -98,9 +98,8 @@ struct thread_info { #define TIF_IO_BITMAP 22 /* uses I/O bitmap */ #define TIF_SPEC_FORCE_UPDATE 23 /* Force speculation MSR update in contex= t switch */ #define TIF_FORCED_TF 24 /* true if TF in eflags artificially */ -#define TIF_SINGLESTEP 25 /* reenable singlestep on user return*/ -#define TIF_BLOCKSTEP 26 /* set when we want DEBUGCTLMSR_BTF */ -#define TIF_ADDR32 27 /* 32-bit address space on 64 bits */ +#define TIF_BLOCKSTEP 25 /* set when we want DEBUGCTLMSR_BTF */ +#define TIF_ADDR32 26 /* 32-bit address space on 64 bits */ =20 #define _TIF_SSBD BIT(TIF_SSBD) #define _TIF_SPEC_IB BIT(TIF_SPEC_IB) @@ -112,7 +111,6 @@ struct thread_info { #define _TIF_SPEC_FORCE_UPDATE BIT(TIF_SPEC_FORCE_UPDATE) #define _TIF_FORCED_TF BIT(TIF_FORCED_TF) #define _TIF_BLOCKSTEP BIT(TIF_BLOCKSTEP) -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) #define _TIF_ADDR32 BIT(TIF_ADDR32) =20 /* flags to check in __switch_to() */ diff --git a/include/asm-generic/thread_info_tif.h b/include/asm-generic/th= read_info_tif.h index da1610a78f92..b277fe06aee3 100644 --- a/include/asm-generic/thread_info_tif.h +++ b/include/asm-generic/thread_info_tif.h @@ -48,4 +48,9 @@ #define TIF_RSEQ 11 // Run RSEQ fast path #define _TIF_RSEQ BIT(TIF_RSEQ) =20 +#ifdef HAVE_TIF_SINGLESTEP +#define TIF_SINGLESTEP 12 /* reenable singlestep on user return*/ +#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP) +#endif + #endif /* _ASM_GENERIC_THREAD_INFO_TIF_H_ */ --=20 2.34.1 From nobody Sat Apr 4 07:51:21 2026 Received: from canpmsgout05.his.huawei.com (canpmsgout05.his.huawei.com [113.46.200.220]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3023398905; 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Fri, 20 Mar 2026 18:41:14 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v14 3/4] arm64: Use generic TIF bits for common thread flags Date: Fri, 20 Mar 2026 18:42:21 +0800 Message-ID: <20260320104222.1381274-4-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260320104222.1381274-1-ruanjinjie@huawei.com> References: <20260320104222.1381274-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Use the generic TIF bits defined in for standard thread flags (TIF_SIGPENDING, TIF_NEED_RESCHED, TIF_NOTIFY_RESUME, TIF_RESTORE_SIGMASK, TIF_SINGLESTEP, etc.) instead of defining them locally. Arm64-specific bits (TIF_FOREIGN_FPSTATE, TIF_MTE_ASYNC_FAULT, TIF_SVE, TIF_SSBD, etc.) are renumbered to start at bit 16 to avoid conflicts. This enables RSEQ optimizations which require CONFIG_HAVE_GENERIC_TIF_BITS combined with the generic entry infrastructure (already used by arm64). By the way, remove TIF_FREEZE because this flag became unused since commit d88e4cb67197 ("freezer: remove now unused TIF_FREEZE"). Cc: Thomas Gleixner Reviewed-by: Kevin Brodsky Reviewed-by: Linus Walleij Reviewed-by: Yeoreum Yun Signed-off-by: Jinjie Ruan Acked-by: Catalin Marinas --- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/thread_info.h | 61 ++++++++++++---------------- 2 files changed, 27 insertions(+), 35 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 96fef01598be..33cf901fb1a0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -224,6 +224,7 @@ config ARM64 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI select HAVE_BUILDTIME_MCOUNT_SORT select HAVE_EFFICIENT_UNALIGNED_ACCESS + select HAVE_GENERIC_TIF_BITS select HAVE_GUP_FAST select HAVE_FTRACE_GRAPH_FUNC select HAVE_FUNCTION_TRACER diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/= thread_info.h index f89a15dc6ad5..57c37b05b961 100644 --- a/arch/arm64/include/asm/thread_info.h +++ b/arch/arm64/include/asm/thread_info.h @@ -58,42 +58,33 @@ void arch_setup_new_exec(void); =20 #endif =20 -#define TIF_SIGPENDING 0 /* signal pending */ -#define TIF_NEED_RESCHED 1 /* rescheduling necessary */ -#define TIF_NEED_RESCHED_LAZY 2 /* Lazy rescheduling needed */ -#define TIF_NOTIFY_RESUME 3 /* callback before returning to user */ -#define TIF_FOREIGN_FPSTATE 4 /* CPU's FP state is not current's */ -#define TIF_UPROBE 5 /* uprobe breakpoint or singlestep */ -#define TIF_MTE_ASYNC_FAULT 6 /* MTE Asynchronous Tag Check Fault */ -#define TIF_NOTIFY_SIGNAL 7 /* signal notifications exist */ -#define TIF_PATCH_PENDING 13 /* pending live patching update */ -#define TIF_MEMDIE 18 /* is terminating due to OOM killer */ -#define TIF_FREEZE 19 -#define TIF_RESTORE_SIGMASK 20 -#define TIF_SINGLESTEP 21 -#define TIF_32BIT 22 /* 32bit process */ -#define TIF_SVE 23 /* Scalable Vector Extension in use */ -#define TIF_SVE_VL_INHERIT 24 /* Inherit SVE vl_onexec across exec */ -#define TIF_SSBD 25 /* Wants SSB mitigation */ -#define TIF_TAGGED_ADDR 26 /* Allow tagged user addresses */ -#define TIF_SME 27 /* SME in use */ -#define TIF_SME_VL_INHERIT 28 /* Inherit SME vl_onexec across exec */ -#define TIF_KERNEL_FPSTATE 29 /* Task is in a kernel mode FPSIMD section */ -#define TIF_TSC_SIGSEGV 30 /* SIGSEGV on counter-timer access */ -#define TIF_LAZY_MMU_PENDING 31 /* Ops pending for lazy mmu mode exit */ +/* + * Tell the generic TIF infrastructure which bits arm64 supports + */ +#define HAVE_TIF_NEED_RESCHED_LAZY +#define HAVE_TIF_RESTORE_SIGMASK +#define HAVE_TIF_SINGLESTEP + +#include + +#define TIF_FOREIGN_FPSTATE 16 /* CPU's FP state is not current's */ +#define TIF_MTE_ASYNC_FAULT 17 /* MTE Asynchronous Tag Check Fault */ +#define TIF_32BIT 18 /* 32bit process */ +#define TIF_SVE 19 /* Scalable Vector Extension in use */ +#define TIF_SVE_VL_INHERIT 20 /* Inherit SVE vl_onexec across exec */ +#define TIF_SSBD 21 /* Wants SSB mitigation */ +#define TIF_TAGGED_ADDR 22 /* Allow tagged user addresses */ +#define TIF_SME 23 /* SME in use */ +#define TIF_SME_VL_INHERIT 24 /* Inherit SME vl_onexec across exec */ +#define TIF_KERNEL_FPSTATE 25 /* Task is in a kernel mode FPSIMD section */ +#define TIF_TSC_SIGSEGV 26 /* SIGSEGV on counter-timer access */ +#define TIF_LAZY_MMU_PENDING 27 /* Ops pending for lazy mmu mode exit */ =20 -#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) -#define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY) -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) -#define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE) -#define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING) -#define _TIF_UPROBE (1 << TIF_UPROBE) -#define _TIF_32BIT (1 << TIF_32BIT) -#define _TIF_SVE (1 << TIF_SVE) -#define _TIF_MTE_ASYNC_FAULT (1 << TIF_MTE_ASYNC_FAULT) -#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) -#define _TIF_TSC_SIGSEGV (1 << TIF_TSC_SIGSEGV) +#define _TIF_FOREIGN_FPSTATE BIT(TIF_FOREIGN_FPSTATE) +#define _TIF_32BIT BIT(TIF_32BIT) +#define _TIF_SVE BIT(TIF_SVE) +#define _TIF_MTE_ASYNC_FAULT BIT(TIF_MTE_ASYNC_FAULT) +#define _TIF_TSC_SIGSEGV BIT(TIF_TSC_SIGSEGV) =20 #ifdef CONFIG_SHADOW_CALL_STACK #define INIT_SCS \ --=20 2.34.1 From nobody Sat Apr 4 07:51:22 2026 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55D9E399343; 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Fri, 20 Mar 2026 18:41:16 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v14 4/4] selftests: sud_test: Support aarch64 Date: Fri, 20 Mar 2026 18:42:22 +0800 Message-ID: <20260320104222.1381274-5-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260320104222.1381274-1-ruanjinjie@huawei.com> References: <20260320104222.1381274-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" From: kemal Support aarch64 to test "Syscall User Dispatch" feature with sud_test selftest testcase. On qemu-kvm machine, the sud_benchmark test results are as below: # ./sud_benchmark Calibrating test set to last ~5 seconds... test iterations =3D 24500000 Avg syscall time 208ns. Enabling syscall trapping. Caught sys_1c2 trapped_call_count 1, native_call_count 0. Avg syscall time 213ns. Interception overhead: 2.5% (+5ns). Reviewed-by: Yeoreum Yun Signed-off-by: kemal Signed-off-by: Jinjie Ruan Reviewed-by: Linus Walleij --- tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c | 2 +- tools/testing/selftests/syscall_user_dispatch/sud_test.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c = b/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c index 073a03702ff5..6059abe75cb3 100644 --- a/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c +++ b/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c @@ -41,7 +41,7 @@ * out of the box, but don't enable them until they support syscall user * dispatch. */ -#if defined(__x86_64__) || defined(__i386__) +#if defined(__x86_64__) || defined(__i386__) || defined(__aarch64__) #define TEST_BLOCKED_RETURN #endif =20 diff --git a/tools/testing/selftests/syscall_user_dispatch/sud_test.c b/too= ls/testing/selftests/syscall_user_dispatch/sud_test.c index b855c6000287..3ffea2f4a66d 100644 --- a/tools/testing/selftests/syscall_user_dispatch/sud_test.c +++ b/tools/testing/selftests/syscall_user_dispatch/sud_test.c @@ -192,6 +192,10 @@ static void handle_sigsys(int sig, siginfo_t *info, vo= id *ucontext) ((ucontext_t *)ucontext)->uc_mcontext.__gregs[REG_A0] =3D ((ucontext_t *)ucontext)->uc_mcontext.__gregs[REG_A7]; #endif +#ifdef __aarch64__ + ((ucontext_t *)ucontext)->uc_mcontext.regs[0] =3D (unsigned int) + ((ucontext_t *)ucontext)->uc_mcontext.regs[8]; +#endif } =20 int setup_sigsys_handler(void) --=20 2.34.1