From nobody Thu Apr 2 02:46:05 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29C83325710; Fri, 20 Mar 2026 05:59:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773986399; cv=none; b=opSLltij4+KIk0uWbSoYcavA5Kk9MD7aN44SJ7HJZHAoIZu/bZC4Ti0tbybOOuV/PEu2LNuDIV9DLxbeeJ6jzNxDCXYO5tkqGmf4oy+yF31KgSx4TBFaDANhTr9ikicXqztu+f5665Phcpaa4ijomBwwUl71dEYWsUDQSWXleHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773986399; c=relaxed/simple; bh=SINNr/9PQVWmohqEQcl0q3MmRdpabubASIYNha9MW+I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g+rEj53xtm2Y7bjHPHe93tpW8CGlkkXLgRe/9vxAeekUNnlR6/zZ3rpEJBZiQzqeyJP5G6TRaCtoVJtVe0eYhi77/BTm6F4/OhttTN6A6Y01LTZI2hdsmGeEcihDXiwn6tsnYwMRjsiZn4XFl/qA702dDR/Z9zmbInAX1X71PyE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=WW0S9P73; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="WW0S9P73" X-UUID: 014bde46242211f1a02d4725871ece0b-20260320 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zWxKExStOAZc57km/2fM7Wk/MBk+KqJmr+NV+wNKQG0=; b=WW0S9P735B2pvWTROBNwBg0WWBEGfQFQe1UOCTTPUznhfu5rcX/VNQFCwyz7BwJz1huATKDaWRf5f2a0HsKVs2RKXQizpgn/w6K04NDp6ZAXlUI+zbG+J2M9ExmdMXALQTFxVVv8crHxRkcN2z+dM85csxfGjCZ9Z1HODvlP+Og=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:0b9c9a90-8469-4d2b-9909-e98fa17b069d,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:1805eb16-aa6b-4b2e-be76-373ef1a42b04,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 014bde46242211f1a02d4725871ece0b-20260320 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 839650910; Fri, 20 Mar 2026 13:59:49 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 20 Mar 2026 13:59:48 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 20 Mar 2026 13:59:47 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v8 3/9] media: mediatek: vcodec: Refactor Decoder profile & level Handling Date: Fri, 20 Mar 2026 13:59:34 +0800 Message-ID: <20260320055940.15961-4-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260320055940.15961-1-kyrie.wu@mediatek.com> References: <20260320055940.15961-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" This commit refactors the handling of decoder parameters for H264, H265, and VP9 codecs by introducing a new structure to standardize supported level and profile information. By leveraging this change, chipset-specific conditional logic in the codec configuration functions is significantly reduced. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 16 ++ .../vcodec/decoder/mtk_vcodec_dec_stateful.c | 12 ++ .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 165 ++++++++++-------- 3 files changed, 118 insertions(+), 75 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index 7921588bf814..4ffc0eae855b 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -78,6 +78,16 @@ struct vdec_pic_info { unsigned int reserved; }; =20 +/** + * struct mtk_vcodec_dec_params - decoder supported parameters + * @level: decoder supported vcodec level + * @profile: decoder supported vcodec profile + */ +struct mtk_vcodec_dec_params { + s64 level; + s64 profile; +}; + /** * struct mtk_vcodec_dec_pdata - compatible data for each IC * @init_vdec_params: init vdec params @@ -98,6 +108,9 @@ struct vdec_pic_info { * @is_subdev_supported: whether support parent-node architecture(subdev) * @uses_stateless_api: whether the decoder uses the stateless API with re= quests * @chip_model: platforms configuration values + * @h264_params: H264 decoder default supported params + * @h265_params: H265 decoder default supported params + * @vp9_params: VP9 decoder default supported params */ struct mtk_vcodec_dec_pdata { void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx); @@ -120,6 +133,9 @@ struct mtk_vcodec_dec_pdata { bool is_subdev_supported; bool uses_stateless_api; unsigned int chip_model; + struct mtk_vcodec_dec_params h264_params; + struct mtk_vcodec_dec_params h265_params; + struct mtk_vcodec_dec_params vp9_params; }; =20 /** diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index 0e702d6a43ed..64f32976d15e 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -619,4 +619,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_model =3D 8173, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_1, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index 5ecbfc169805..efcd28f5f289 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -571,106 +571,49 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctr= l_ops =3D { static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8192: - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0; - break; - case 8183: - case 8186: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_1; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h264_params.level; } =20 static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h264_params.profile; } =20 static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h265_params.level; } =20 static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h265_params.profile; } =20 static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8192: - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; - break; - case 8186: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->vp9_params.level; } =20 static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->vp9_params.profile; } =20 static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, @@ -936,6 +879,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_model =3D 8183, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; =20 /* This platform data is used for one lat and one core architecture. */ @@ -975,24 +930,72 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata= =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_model =3D 8188, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_model =3D 8192, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_model =3D 8195, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_model =3D 8196, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata =3D { @@ -1016,4 +1019,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdat= a =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_model =3D 8186, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; --=20 2.45.2