From nobody Thu Apr 2 02:46:04 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 715FF31F9A1; Fri, 20 Mar 2026 05:59:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773986399; cv=none; b=ApfXaORcRT9+tUcPmBRBzpfpWY77duXxUxk8aw8UKXfPro9q78gkHaFu8BciOqSWn8GgQURlD4H72M39iR3v0hRuFFRWEU0eZJZJPJdhtWi9uZsT8h+9OrOhIWxhmAY4R5nGvXQUdrRAsxasjBhQU7tv/72piYag/+Wct8EhiyA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773986399; c=relaxed/simple; bh=hWZ9SOeEwcSHxdQS6qTLqFXgct3KF/nSoKKcBUnd6VQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ljR9Agz5Z24I/ovaWHn6kSJlCpHkjiTd32JnBYYCk4MAEvOa+jIJX4JrK9yHYt3eTPqX4we9Zn/Zach7s648WtEi0IHWr1GKQdTPr82QFDRdDU/uiP8tcgCWq6ImV5Vp9lBc/ELB7a1xBnvtKLvKrh19ltivH690aD03VnJyVSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=RzTQUluX; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="RzTQUluX" X-UUID: 0094a3c0242211f1a02d4725871ece0b-20260320 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=yAXrdupkuSVERovQ8wGJ213SL8rS7SkIUkd7HGZC1I8=; b=RzTQUluX4vVH6Jh9UbP6eUBzQJkfRDUzeAYG/dMhk7ZKfbfEaydvDOvXBMOd8FQQaOTHwd6vIH5S8S7qCzwqojSyRaiFFYOgGjynj+AHz6YB6UcybZa7/3SZ7Wn5INg45bjSoxE0i82ssjcqLFI4GwbLZ3+eyJ1l9UDpH0vwG2g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:9015f040-72ef-412a-96e1-ab3d96fc2494,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:3891b64c-9183-487b-8624-e74f2dd98990,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 0094a3c0242211f1a02d4725871ece0b-20260320 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 354332778; Fri, 20 Mar 2026 13:59:48 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 20 Mar 2026 13:59:46 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 20 Mar 2026 13:59:45 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v8 2/9] media: mediatek: decoder: Add a new platform data member Date: Fri, 20 Mar 2026 13:59:33 +0800 Message-ID: <20260320055940.15961-3-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260320055940.15961-1-kyrie.wu@mediatek.com> References: <20260320055940.15961-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Move the chip model information into the codec match data and remove the second compatible matching code. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nicolas Dufresne --- .../mediatek/vcodec/decoder/mtk_vcodec_dec.c | 2 +- .../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 5 + .../vcodec/decoder/mtk_vcodec_dec_drv.c | 39 ++----- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 17 +-- .../vcodec/decoder/mtk_vcodec_dec_hw.c | 2 +- .../vcodec/decoder/mtk_vcodec_dec_stateful.c | 1 + .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 104 +++++++++++++----- 7 files changed, 96 insertions(+), 74 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.= c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c index d76e891f784b..13d70acda88b 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c @@ -263,7 +263,7 @@ static int vidioc_vdec_querycap(struct file *file, void= *priv, struct device *dev =3D &ctx->dev->plat_dev->dev; =20 strscpy(cap->driver, dev->driver->name, sizeof(cap->driver)); - snprintf(cap->card, sizeof(cap->card), "MT%d video decoder", ctx->dev->ch= ip_name); + snprintf(cap->card, sizeof(cap->card), "MT%d video decoder", ctx->dev->ch= ip_model); =20 return 0; } diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.= h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h index 1af075fc0194..80cb46f1cded 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h @@ -69,6 +69,11 @@ extern const struct v4l2_m2m_ops mtk_vdec_m2m_ops; extern const struct media_device_ops mtk_vcodec_media_ops; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata; extern const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata; =20 diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index e7c140b26955..6ebd82ba8d23 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -331,26 +331,9 @@ static const struct v4l2_file_operations mtk_vcodec_fo= ps =3D { .mmap =3D v4l2_m2m_fop_mmap, }; =20 -static void mtk_vcodec_dec_get_chip_name(struct mtk_vcodec_dec_dev *vdec_d= ev) +static void mtk_vcodec_dec_get_chip_model(struct mtk_vcodec_dec_dev *vdec_= dev) { - struct device *dev =3D &vdec_dev->plat_dev->dev; - - if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-dec")) - vdec_dev->chip_name =3D MTK_VDEC_MT8173; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8183; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8192; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8195; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8186-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8186; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8188-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8188; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8196-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8196; - else - vdec_dev->chip_name =3D MTK_VDEC_INVAL; + vdec_dev->chip_model =3D vdec_dev->vdec_pdata->chip_model; } =20 static int mtk_vcodec_probe(struct platform_device *pdev) @@ -368,11 +351,7 @@ static int mtk_vcodec_probe(struct platform_device *pd= ev) INIT_LIST_HEAD(&dev->ctx_list); dev->plat_dev =3D pdev; =20 - mtk_vcodec_dec_get_chip_name(dev); - if (dev->chip_name =3D=3D MTK_VDEC_INVAL) { - dev_err(&pdev->dev, "Failed to get decoder chip name"); - return -EINVAL; - } + mtk_vcodec_dec_get_chip_model(dev); =20 dev->vdec_pdata =3D of_device_get_match_data(&pdev->dev); if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu", @@ -389,7 +368,7 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) return -ENODEV; } dma_set_max_seg_size(&pdev->dev, UINT_MAX); - if (dev->chip_name =3D=3D MTK_VDEC_MT8196) { + if (dev->chip_model =3D=3D 8196) { ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); if (ret) { dev_err(&pdev->dev, "Failed to enable 36-bit DMA: %d\n", ret); @@ -558,23 +537,23 @@ static const struct of_device_id mtk_vcodec_match[] = =3D { }, { .compatible =3D "mediatek,mt8192-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8192_pdata, }, { .compatible =3D "mediatek,mt8186-vcodec-dec", - .data =3D &mtk_vdec_single_core_pdata, + .data =3D &mtk_vdec_8186_pdata, }, { .compatible =3D "mediatek,mt8195-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8195_pdata, }, { .compatible =3D "mediatek,mt8188-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8188_pdata, }, { .compatible =3D "mediatek,mt8196-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8196_pdata, }, {}, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index f06dfc1a3455..7921588bf814 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -21,17 +21,6 @@ #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_= RACING) #define IS_VDEC_SUPPORT_EXT(capability) ((capability) & MTK_VDEC_IS_SUPPOR= T_EXT) =20 -enum mtk_vcodec_dec_chip_name { - MTK_VDEC_INVAL =3D 0, - MTK_VDEC_MT8173 =3D 8173, - MTK_VDEC_MT8183 =3D 8183, - MTK_VDEC_MT8186 =3D 8186, - MTK_VDEC_MT8188 =3D 8188, - MTK_VDEC_MT8192 =3D 8192, - MTK_VDEC_MT8195 =3D 8195, - MTK_VDEC_MT8196 =3D 8196, -}; - /* * enum mtk_vdec_format_types - Structure used to get supported * format types according to decoder capability @@ -108,6 +97,7 @@ struct vdec_pic_info { * * @is_subdev_supported: whether support parent-node architecture(subdev) * @uses_stateless_api: whether the decoder uses the stateless API with re= quests + * @chip_model: platforms configuration values */ struct mtk_vcodec_dec_pdata { void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx); @@ -129,6 +119,7 @@ struct mtk_vcodec_dec_pdata { =20 bool is_subdev_supported; bool uses_stateless_api; + unsigned int chip_model; }; =20 /** @@ -276,7 +267,7 @@ struct mtk_vcodec_dec_ctx { * @dec_racing_info_mutex: mutex lock used for inner racing mode * @dbgfs: debug log related information * - * @chip_name: used to distinguish platforms and select the correct codec = configuration values + * @chip_model: used to distinguish platforms and select the correct codec= configuration values */ struct mtk_vcodec_dec_dev { struct v4l2_device v4l2_dev; @@ -319,7 +310,7 @@ struct mtk_vcodec_dec_dev { struct mutex dec_racing_info_mutex; struct mtk_vcodec_dbgfs dbgfs; =20 - enum mtk_vcodec_dec_chip_name chip_name; + unsigned int chip_model; }; =20 static inline struct mtk_vcodec_dec_ctx *fh_to_dec_ctx(struct v4l2_fh *fh) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= hw.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c index e4e527fe54dc..149f1ad58152 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c @@ -76,7 +76,7 @@ static void mtk_vdec_hw_clean_xpc(struct mtk_vdec_hw_dev = *dev) { u32 val, mask, addr =3D VDEC_XPC_CLEAN_ADDR; =20 - if (dev->main_dev->chip_name !=3D MTK_VDEC_MT8196) + if (dev->main_dev->chip_model !=3D 8196) return; =20 val =3D dev->hw_idx =3D=3D MTK_VDEC_LAT0 ? VDEC_XPC_LAT_VAL : VDEC_XPC_CO= RE_VAL; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index aa9bdee7a96c..0e702d6a43ed 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -618,4 +618,5 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .flush_decoder =3D mtk_vdec_flush_decoder, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_model =3D 8173, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index 472ece5713a5..5ecbfc169805 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -571,17 +571,17 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl= _ops =3D { static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8192: - case MTK_VDEC_MT8188: + switch (ctx->dev->chip_model) { + case 8192: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0; break; - case MTK_VDEC_MT8183: - case MTK_VDEC_MT8186: + case 8183: + case 8186: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2; break; default: @@ -593,10 +593,10 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l= 2_ctrl_config *cfg, static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + switch (ctx->dev->chip_model) { + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; break; default: @@ -608,12 +608,12 @@ static void mtk_vcodec_dec_fill_h264_profile(struct v= 4l2_ctrl_config *cfg, static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: + switch (ctx->dev->chip_model) { + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; break; default: @@ -625,10 +625,10 @@ static void mtk_vcodec_dec_fill_h265_level(struct v4l= 2_ctrl_config *cfg, static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + switch (ctx->dev->chip_model) { + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; break; default: @@ -640,16 +640,16 @@ static void mtk_vcodec_dec_fill_h265_profile(struct v= 4l2_ctrl_config *cfg, static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8192: - case MTK_VDEC_MT8188: + switch (ctx->dev->chip_model) { + case 8192: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; break; - case MTK_VDEC_MT8186: + case 8186: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; break; default: @@ -661,10 +661,10 @@ static void mtk_vcodec_dec_fill_vp9_level(struct v4l2= _ctrl_config *cfg, static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + switch (ctx->dev->chip_model) { + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2; break; default: @@ -935,6 +935,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .get_cap_buffer =3D vdec_get_cap_buffer, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_model =3D 8183, }; =20 /* This platform data is used for one lat and one core architecture. */ @@ -955,6 +956,45 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pda= ta =3D { .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, }; =20 +#define MTK_STATELESS_DEC_DATA \ + .init_vdec_params =3D mtk_init_vdec_params, \ + .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, \ + .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, \ + .vdec_formats =3D mtk_video_formats, \ + .num_formats =3D &num_formats, \ + .default_out_fmt =3D &default_out_format, \ + .default_cap_fmt =3D &default_cap_format, \ + .uses_stateless_api =3D true, \ + .worker =3D mtk_vdec_worker, \ + .flush_decoder =3D mtk_vdec_flush_decoder, \ + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, \ + .get_cap_buffer =3D vdec_get_cap_buffer, \ + .is_subdev_supported =3D true + +const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_model =3D 8188, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_model =3D 8192, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_model =3D 8195, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_model =3D 8196, +}; + const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata =3D { .init_vdec_params =3D mtk_init_vdec_params, .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, @@ -971,3 +1011,9 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_single_core= _pdata =3D { .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, }; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_model =3D 8186, +}; --=20 2.45.2