From nobody Thu Apr 2 01:10:06 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF4282F360A; Fri, 20 Mar 2026 05:59:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773986396; cv=none; b=m2IGWVh8LmqWJGULnid7VgB1PTGDDm+fG9qSXjZ2WJ6qlmiN5a++8HwdAouO2gzrO3j9MSuSOHUr4ifCgZQLYZmwSKYOOLuWX8Xz+jXVuQ8Gmzh2VOv+7x+DXHjK3bMM0C75ANbmHY+OBPbZB8GXuOtqHUnzoITnRdEQPRdVOHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773986396; c=relaxed/simple; bh=cziYfs0U76ZCGMxZhfyz4A6Do/VDXzBlZRinINiINKU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ayBaQdGXzmSJ6D0kTnFHebxjmxCWTqKwys5cy6dsggC4hzOdnltAQSsym/mYJkkJ+N/jLT0osnPxPvDHWp3bBNQR9n8ijN5J04wp1+7xHxO18PeeDo846YRIT6YHBJz62nNKjDJijuYuomuuDQTSC8GWzHfc6RPMG9Fbv9hrbeA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Qu18c3p5; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Qu18c3p5" X-UUID: ffc1eef8242111f1a02d4725871ece0b-20260320 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=PYvG3A9bhcpcCBRSGioZeJBjwhbqKSxm5F0PwaNR9Wc=; b=Qu18c3p50oU8iJ2uh0BSGXe1SmzE7ltaX6kSw9++82kMUaxpEPaYIHt4G5XuEn9jQgXkAv/ygpaXrsfva7GoSc0JuFzLKi984FoL7O3DZf5ens9RzOTsvI9i/aFYJ1VmqrKusclNQXZ07k9BPJ2ODWYWbgYtWL/h00Po/JFbss4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:27f73fc2-6326-48b1-8d80-ae536145b7a9,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:51380394-f8ef-4ca8-bea0-143568f9ca1d,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: ffc1eef8242111f1a02d4725871ece0b-20260320 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1712127322; Fri, 20 Mar 2026 13:59:46 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 20 Mar 2026 13:59:45 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 20 Mar 2026 13:59:44 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v8 1/9] dt-bindings: media: mediatek: decoder: Add MT8189 mediatek,vcodec-decoder Date: Fri, 20 Mar 2026 13:59:32 +0800 Message-ID: <20260320055940.15961-2-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260320055940.15961-1-kyrie.wu@mediatek.com> References: <20260320055940.15961-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add compatible for video decoder on MT8189 platform. Compared with former ICs, the MT8189 decoder use iommu to instead of smmu, and use scp architecture, the frequency is only 406MHZ, and cannot reach more than 700MHZ. It uses only one clock. At the same time, the decoder supports the vp9 decoding protocol for the first time in single IC. Signed-off-by: Kyrie Wu Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nicolas Dufresne --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev= -decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-sub= dev-decoder.yaml index 74e1d88d3056..ee2bbbdb2d50 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml @@ -75,6 +75,7 @@ properties: - mediatek,mt8192-vcodec-dec - mediatek,mt8186-vcodec-dec - mediatek,mt8188-vcodec-dec + - mediatek,mt8189-vcodec-dec - mediatek,mt8195-vcodec-dec - mediatek,mt8196-vcodec-dec =20 @@ -132,11 +133,11 @@ patternProperties: Refer to bindings/iommu/mediatek,iommu.yaml. =20 clocks: - minItems: 4 + minItems: 1 maxItems: 5 =20 clock-names: - minItems: 4 + minItems: 1 maxItems: 5 =20 assigned-clocks: --=20 2.45.2 From nobody Thu Apr 2 01:10:06 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 715FF31F9A1; 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charset="utf-8" Move the chip model information into the codec match data and remove the second compatible matching code. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nicolas Dufresne --- .../mediatek/vcodec/decoder/mtk_vcodec_dec.c | 2 +- .../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 5 + .../vcodec/decoder/mtk_vcodec_dec_drv.c | 39 ++----- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 17 +-- .../vcodec/decoder/mtk_vcodec_dec_hw.c | 2 +- .../vcodec/decoder/mtk_vcodec_dec_stateful.c | 1 + .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 104 +++++++++++++----- 7 files changed, 96 insertions(+), 74 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.= c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c index d76e891f784b..13d70acda88b 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c @@ -263,7 +263,7 @@ static int vidioc_vdec_querycap(struct file *file, void= *priv, struct device *dev =3D &ctx->dev->plat_dev->dev; =20 strscpy(cap->driver, dev->driver->name, sizeof(cap->driver)); - snprintf(cap->card, sizeof(cap->card), "MT%d video decoder", ctx->dev->ch= ip_name); + snprintf(cap->card, sizeof(cap->card), "MT%d video decoder", ctx->dev->ch= ip_model); =20 return 0; } diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.= h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h index 1af075fc0194..80cb46f1cded 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h @@ -69,6 +69,11 @@ extern const struct v4l2_m2m_ops mtk_vdec_m2m_ops; extern const struct media_device_ops mtk_vcodec_media_ops; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata; extern const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata; =20 diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index e7c140b26955..6ebd82ba8d23 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -331,26 +331,9 @@ static const struct v4l2_file_operations mtk_vcodec_fo= ps =3D { .mmap =3D v4l2_m2m_fop_mmap, }; =20 -static void mtk_vcodec_dec_get_chip_name(struct mtk_vcodec_dec_dev *vdec_d= ev) +static void mtk_vcodec_dec_get_chip_model(struct mtk_vcodec_dec_dev *vdec_= dev) { - struct device *dev =3D &vdec_dev->plat_dev->dev; - - if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-dec")) - vdec_dev->chip_name =3D MTK_VDEC_MT8173; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8183; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8192; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8195; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8186-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8186; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8188-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8188; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8196-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8196; - else - vdec_dev->chip_name =3D MTK_VDEC_INVAL; + vdec_dev->chip_model =3D vdec_dev->vdec_pdata->chip_model; } =20 static int mtk_vcodec_probe(struct platform_device *pdev) @@ -368,11 +351,7 @@ static int mtk_vcodec_probe(struct platform_device *pd= ev) INIT_LIST_HEAD(&dev->ctx_list); dev->plat_dev =3D pdev; =20 - mtk_vcodec_dec_get_chip_name(dev); - if (dev->chip_name =3D=3D MTK_VDEC_INVAL) { - dev_err(&pdev->dev, "Failed to get decoder chip name"); - return -EINVAL; - } + mtk_vcodec_dec_get_chip_model(dev); =20 dev->vdec_pdata =3D of_device_get_match_data(&pdev->dev); if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu", @@ -389,7 +368,7 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) return -ENODEV; } dma_set_max_seg_size(&pdev->dev, UINT_MAX); - if (dev->chip_name =3D=3D MTK_VDEC_MT8196) { + if (dev->chip_model =3D=3D 8196) { ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); if (ret) { dev_err(&pdev->dev, "Failed to enable 36-bit DMA: %d\n", ret); @@ -558,23 +537,23 @@ static const struct of_device_id mtk_vcodec_match[] = =3D { }, { .compatible =3D "mediatek,mt8192-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8192_pdata, }, { .compatible =3D "mediatek,mt8186-vcodec-dec", - .data =3D &mtk_vdec_single_core_pdata, + .data =3D &mtk_vdec_8186_pdata, }, { .compatible =3D "mediatek,mt8195-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8195_pdata, }, { .compatible =3D "mediatek,mt8188-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8188_pdata, }, { .compatible =3D "mediatek,mt8196-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8196_pdata, }, {}, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index f06dfc1a3455..7921588bf814 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -21,17 +21,6 @@ #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_= RACING) #define IS_VDEC_SUPPORT_EXT(capability) ((capability) & MTK_VDEC_IS_SUPPOR= T_EXT) =20 -enum mtk_vcodec_dec_chip_name { - MTK_VDEC_INVAL =3D 0, - MTK_VDEC_MT8173 =3D 8173, - MTK_VDEC_MT8183 =3D 8183, - MTK_VDEC_MT8186 =3D 8186, - MTK_VDEC_MT8188 =3D 8188, - MTK_VDEC_MT8192 =3D 8192, - MTK_VDEC_MT8195 =3D 8195, - MTK_VDEC_MT8196 =3D 8196, -}; - /* * enum mtk_vdec_format_types - Structure used to get supported * format types according to decoder capability @@ -108,6 +97,7 @@ struct vdec_pic_info { * * @is_subdev_supported: whether support parent-node architecture(subdev) * @uses_stateless_api: whether the decoder uses the stateless API with re= quests + * @chip_model: platforms configuration values */ struct mtk_vcodec_dec_pdata { void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx); @@ -129,6 +119,7 @@ struct mtk_vcodec_dec_pdata { =20 bool is_subdev_supported; bool uses_stateless_api; + unsigned int chip_model; }; =20 /** @@ -276,7 +267,7 @@ struct mtk_vcodec_dec_ctx { * @dec_racing_info_mutex: mutex lock used for inner racing mode * @dbgfs: debug log related information * - * @chip_name: used to distinguish platforms and select the correct codec = configuration values + * @chip_model: used to distinguish platforms and select the correct codec= configuration values */ struct mtk_vcodec_dec_dev { struct v4l2_device v4l2_dev; @@ -319,7 +310,7 @@ struct mtk_vcodec_dec_dev { struct mutex dec_racing_info_mutex; struct mtk_vcodec_dbgfs dbgfs; =20 - enum mtk_vcodec_dec_chip_name chip_name; + unsigned int chip_model; }; =20 static inline struct mtk_vcodec_dec_ctx *fh_to_dec_ctx(struct v4l2_fh *fh) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= hw.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c index e4e527fe54dc..149f1ad58152 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c @@ -76,7 +76,7 @@ static void mtk_vdec_hw_clean_xpc(struct mtk_vdec_hw_dev = *dev) { u32 val, mask, addr =3D VDEC_XPC_CLEAN_ADDR; =20 - if (dev->main_dev->chip_name !=3D MTK_VDEC_MT8196) + if (dev->main_dev->chip_model !=3D 8196) return; =20 val =3D dev->hw_idx =3D=3D MTK_VDEC_LAT0 ? VDEC_XPC_LAT_VAL : VDEC_XPC_CO= RE_VAL; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index aa9bdee7a96c..0e702d6a43ed 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -618,4 +618,5 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .flush_decoder =3D mtk_vdec_flush_decoder, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_model =3D 8173, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index 472ece5713a5..5ecbfc169805 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -571,17 +571,17 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl= _ops =3D { static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8192: - case MTK_VDEC_MT8188: + switch (ctx->dev->chip_model) { + case 8192: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0; break; - case MTK_VDEC_MT8183: - case MTK_VDEC_MT8186: + case 8183: + case 8186: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2; break; default: @@ -593,10 +593,10 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l= 2_ctrl_config *cfg, static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + switch (ctx->dev->chip_model) { + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; break; default: @@ -608,12 +608,12 @@ static void mtk_vcodec_dec_fill_h264_profile(struct v= 4l2_ctrl_config *cfg, static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: + switch (ctx->dev->chip_model) { + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; break; default: @@ -625,10 +625,10 @@ static void mtk_vcodec_dec_fill_h265_level(struct v4l= 2_ctrl_config *cfg, static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + switch (ctx->dev->chip_model) { + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; break; default: @@ -640,16 +640,16 @@ static void mtk_vcodec_dec_fill_h265_profile(struct v= 4l2_ctrl_config *cfg, static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8192: - case MTK_VDEC_MT8188: + switch (ctx->dev->chip_model) { + case 8192: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; break; - case MTK_VDEC_MT8186: + case 8186: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; break; default: @@ -661,10 +661,10 @@ static void mtk_vcodec_dec_fill_vp9_level(struct v4l2= _ctrl_config *cfg, static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + switch (ctx->dev->chip_model) { + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2; break; default: @@ -935,6 +935,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .get_cap_buffer =3D vdec_get_cap_buffer, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_model =3D 8183, }; =20 /* This platform data is used for one lat and one core architecture. */ @@ -955,6 +956,45 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pda= ta =3D { .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, }; =20 +#define MTK_STATELESS_DEC_DATA \ + .init_vdec_params =3D mtk_init_vdec_params, \ + .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, \ + .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, \ + .vdec_formats =3D mtk_video_formats, \ + .num_formats =3D &num_formats, \ + .default_out_fmt =3D &default_out_format, \ + .default_cap_fmt =3D &default_cap_format, \ + .uses_stateless_api =3D true, \ + .worker =3D mtk_vdec_worker, \ + .flush_decoder =3D mtk_vdec_flush_decoder, \ + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, \ + .get_cap_buffer =3D vdec_get_cap_buffer, \ + .is_subdev_supported =3D true + +const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_model =3D 8188, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_model =3D 8192, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_model =3D 8195, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_model =3D 8196, +}; + const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata =3D { .init_vdec_params =3D mtk_init_vdec_params, .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, @@ -971,3 +1011,9 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_single_core= _pdata =3D { .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, }; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_model =3D 8186, +}; --=20 2.45.2 From nobody Thu Apr 2 01:10:06 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29C83325710; 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Fri, 20 Mar 2026 13:59:49 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 20 Mar 2026 13:59:48 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 20 Mar 2026 13:59:47 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v8 3/9] media: mediatek: vcodec: Refactor Decoder profile & level Handling Date: Fri, 20 Mar 2026 13:59:34 +0800 Message-ID: <20260320055940.15961-4-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260320055940.15961-1-kyrie.wu@mediatek.com> References: <20260320055940.15961-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" This commit refactors the handling of decoder parameters for H264, H265, and VP9 codecs by introducing a new structure to standardize supported level and profile information. By leveraging this change, chipset-specific conditional logic in the codec configuration functions is significantly reduced. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 16 ++ .../vcodec/decoder/mtk_vcodec_dec_stateful.c | 12 ++ .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 165 ++++++++++-------- 3 files changed, 118 insertions(+), 75 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index 7921588bf814..4ffc0eae855b 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -78,6 +78,16 @@ struct vdec_pic_info { unsigned int reserved; }; =20 +/** + * struct mtk_vcodec_dec_params - decoder supported parameters + * @level: decoder supported vcodec level + * @profile: decoder supported vcodec profile + */ +struct mtk_vcodec_dec_params { + s64 level; + s64 profile; +}; + /** * struct mtk_vcodec_dec_pdata - compatible data for each IC * @init_vdec_params: init vdec params @@ -98,6 +108,9 @@ struct vdec_pic_info { * @is_subdev_supported: whether support parent-node architecture(subdev) * @uses_stateless_api: whether the decoder uses the stateless API with re= quests * @chip_model: platforms configuration values + * @h264_params: H264 decoder default supported params + * @h265_params: H265 decoder default supported params + * @vp9_params: VP9 decoder default supported params */ struct mtk_vcodec_dec_pdata { void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx); @@ -120,6 +133,9 @@ struct mtk_vcodec_dec_pdata { bool is_subdev_supported; bool uses_stateless_api; unsigned int chip_model; + struct mtk_vcodec_dec_params h264_params; + struct mtk_vcodec_dec_params h265_params; + struct mtk_vcodec_dec_params vp9_params; }; =20 /** diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index 0e702d6a43ed..64f32976d15e 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -619,4 +619,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_model =3D 8173, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_1, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index 5ecbfc169805..efcd28f5f289 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -571,106 +571,49 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctr= l_ops =3D { static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8192: - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0; - break; - case 8183: - case 8186: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_1; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h264_params.level; } =20 static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h264_params.profile; } =20 static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h265_params.level; } =20 static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h265_params.profile; } =20 static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8192: - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; - break; - case 8186: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->vp9_params.level; } =20 static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->vp9_params.profile; } =20 static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, @@ -936,6 +879,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_model =3D 8183, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; =20 /* This platform data is used for one lat and one core architecture. */ @@ -975,24 +930,72 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata= =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_model =3D 8188, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_model =3D 8192, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_model =3D 8195, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, .chip_model =3D 8196, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata =3D { @@ -1016,4 +1019,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdat= a =3D { MTK_STATELESS_DEC_DATA, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_model =3D 8186, + .h264_params =3D { + .level =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params =3D { + .level =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params =3D { + .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, + .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; 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Fri, 20 Mar 2026 13:59:49 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 20 Mar 2026 13:59:48 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v8 4/9] media: mediatek: vcodec: Add VP9 Probability Size Configuration Date: Fri, 20 Mar 2026 13:59:35 +0800 Message-ID: <20260320055940.15961-5-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260320055940.15961-1-kyrie.wu@mediatek.com> References: <20260320055940.15961-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Introduce support for using different probability buffer sizes for different stateless decoders: in particular, the VP9 decoder can use a different size on different SoCs because of different hardware capabilities. Move the hardcoded single probability buffer size value to decoder params, introduce a new VP9_4K_PROB_BUF_SIZE and assign: - VP9_PROB_BUF_SIZE (2560 lines) to legacy SoCs; - VP9_4K_PROB_BUF_SIZE (3840 lines) to newer SoCs (MT8196, MT8189). Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h | 2 ++ .../mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c | 1 + .../mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c | 9 +++++++++ .../mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 4 ++-- 4 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index 4ffc0eae855b..43dc0b22fdb0 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -82,10 +82,12 @@ struct vdec_pic_info { * struct mtk_vcodec_dec_params - decoder supported parameters * @level: decoder supported vcodec level * @profile: decoder supported vcodec profile + * @prob_size: vp9 decoder probability size */ struct mtk_vcodec_dec_params { s64 level; s64 profile; + size_t prob_size; }; =20 /** diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index 64f32976d15e..5dcbe6550419 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -630,5 +630,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D 2560, }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index efcd28f5f289..748725e563d8 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -10,6 +10,9 @@ #include "mtk_vcodec_dec_pm.h" #include "vdec_drv_if.h" +#define VP9_PROB_BUF_SIZE 2560 +#define VP9_4K_PROB_BUF_SIZE 3840 /** * struct mtk_stateless_control - CID control type * @cfg: control configuration @@ -890,6 +893,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; =20 @@ -941,6 +945,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; =20 @@ -959,6 +964,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; =20 @@ -977,6 +983,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; =20 @@ -995,6 +1002,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D VP9_4K_PROB_BUF_SIZE, }, }; =20 @@ -1030,5 +1038,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata= =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_r= eq_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_= req_lat_if.c index 08d10b3578ae..6123666ce1d5 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c @@ -22,7 +22,6 @@ #define VP9_RESET_FRAME_CONTEXT_ALL 3 =20 #define VP9_TILE_BUF_SIZE 4096 -#define VP9_PROB_BUF_SIZE 2560 #define VP9_COUNTS_BUF_SIZE 16384 =20 #define HDR_FLAG(x) (!!((hdr)->flags & V4L2_VP9_FRAME_FLAG_##x)) @@ -552,6 +551,7 @@ static int vdec_vp9_slice_alloc_working_buffer(struct v= dec_vp9_slice_instance *i struct vdec_vp9_slice_vsi *vsi) { struct mtk_vcodec_dec_ctx *ctx =3D instance->ctx; + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; enum vdec_vp9_slice_resolution_level level; /* super blocks */ unsigned int max_sb_w; @@ -622,7 +622,7 @@ static int vdec_vp9_slice_alloc_working_buffer(struct v= dec_vp9_slice_instance *i } =20 if (!instance->prob.va) { - instance->prob.size =3D VP9_PROB_BUF_SIZE; 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Fri, 20 Mar 2026 13:59:52 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 20 Mar 2026 13:59:50 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 20 Mar 2026 13:59:49 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v8 5/9] media: mediatek: vcodec: Fix vp9 4096x2176 fail for profile2 Date: Fri, 20 Mar 2026 13:59:36 +0800 Message-ID: <20260320055940.15961-6-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260320055940.15961-1-kyrie.wu@mediatek.com> References: <20260320055940.15961-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" The DRAM address of the VP9 decoder tile info buffers may require as much as 36bits for 4096x2176 resolution. Fold the 4 most significant bits into the lower (padding) four bits of address. Fixes: 5d418351ca8f1 ("media: mediatek: vcodec: support stateless VP9 decod= ing") Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nicolas Dufresne --- .../mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_r= eq_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_= req_lat_if.c index 6123666ce1d5..c941bb0f6a62 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c @@ -1139,9 +1139,17 @@ static int vdec_vp9_slice_setup_tile_buffer(struct v= dec_vp9_slice_instance *inst return -EINVAL; } tiles->size[i][j] =3D size; + /* + * If the system supports 64-bit DMA addresses, the upper 4 bits + * of the address are also encoded into the buffer entry. + * The buffer pointer (tb) is incremented after each entry is written. + */ if (tiles->mi_rows[i]) { *tb++ =3D (size << 3) + ((offset << 3) & 0x7f); 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charset="utf-8" MT8189 is pure single core architecture. Add its compatible to initialize platform data. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 1 + .../vcodec/decoder/mtk_vcodec_dec_drv.c | 4 ++++ .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 19 +++++++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.= h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h index 80cb46f1cded..2bde871c0224 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h @@ -71,6 +71,7 @@ extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pd= ata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index 6ebd82ba8d23..dc67c2b84776 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -555,6 +555,10 @@ static const struct of_device_id mtk_vcodec_match[] = =3D { .compatible =3D "mediatek,mt8196-vcodec-dec", .data =3D &mtk_vdec_8196_pdata, }, + { + .compatible =3D "mediatek,mt8189-vcodec-dec", + .data =3D &mtk_vdec_8189_pdata, + }, {}, }; =20 diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index 748725e563d8..b72a22b15834 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -1041,3 +1041,22 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdat= a =3D { .prob_size =3D VP9_PROB_BUF_SIZE, }, }; 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charset="utf-8" change media register device node number to a correct value. The vfd minor is used to record the number of registered video device nodes. The mdev_dec.devnode minor counter is used to record the number of registered media device nodes. Fixes: 41f03c673cb7b ("media: mediatek: vcodec: replace pr_* with dev_* for= v4l2 debug message") Signed-off-by: Kyrie Wu Reviewed-by: Nicolas Dufresne Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index dc67c2b84776..edf0caf3efce 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -495,7 +495,8 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) goto err_media_reg; } =20 - dev_dbg(&pdev->dev, "media registered as /dev/media%d", vfd_dec->minor); + dev_dbg(&pdev->dev, "media registered as /dev/media%d", + dev->mdev_dec.devnode->minor); } =20 mtk_vcodec_dbgfs_init(dev, false); --=20 2.45.2 From nobody Thu Apr 2 01:10:06 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0710C33031F; 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charset="utf-8" Add MT8189 encoder compatible string to distinguish former ICs MTK's. Compared with MT8196, the maximum resolution of MT8189 encoder is only 4K, and the fps is only 30, which cannot reach the highest parameter of MT8196: level6.2, 8K@60fps. Compared with MT8188, the level can only support 5.1, which is less than 5.2 of MT8188. But the maximum bitrate is 100Mbps, which is twice that of MT8188. And MT8189 could support NBM mode. Signed-off-by: Kyrie Wu Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.ya= ml index 72698456374a..91e1e0151e03 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt8173-vcodec-enc - mediatek,mt8183-vcodec-enc - mediatek,mt8188-vcodec-enc + - mediatek,mt8189-vcodec-enc - mediatek,mt8192-vcodec-enc - mediatek,mt8195-vcodec-enc - mediatek,mt8196-vcodec-enc @@ -105,6 +106,7 @@ allOf: enum: - mediatek,mt8183-vcodec-enc - mediatek,mt8188-vcodec-enc + - mediatek,mt8189-vcodec-enc - mediatek,mt8192-vcodec-enc - mediatek,mt8195-vcodec-enc =20 --=20 2.45.2 From nobody Thu Apr 2 01:10:06 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05E18326941; 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charset="utf-8" add MT8189 compatible data to initialize platform data for encoder. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c index 23e47f462f49..16d75680d1e9 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c @@ -469,6 +469,19 @@ static const struct mtk_vcodec_enc_pdata mt8196_pdata = =3D { .set_dma_bit_mask =3D true, }; =20 +static const struct mtk_vcodec_enc_pdata mt8189_pdata =3D { + .venc_model_num =3D 8189, + .capture_formats =3D mtk_video_formats_capture_h264, + .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), + .output_formats =3D mtk_video_formats_output, + .num_output_formats =3D ARRAY_SIZE(mtk_video_formats_output), + .min_bitrate =3D 64, + .max_bitrate =3D 100000000, + .core_id =3D VENC_SYS, + .uses_common_fw_iface =3D true, + .set_dma_bit_mask =3D true, +}; + static const struct of_device_id mtk_vcodec_enc_match[] =3D { {.compatible =3D "mediatek,mt8173-vcodec-enc", .data =3D &mt8173_avc_pdata}, @@ -479,6 +492,7 @@ static const struct of_device_id mtk_vcodec_enc_match[]= =3D { {.compatible =3D "mediatek,mt8192-vcodec-enc", .data =3D &mt8192_pdata}, {.compatible =3D "mediatek,mt8195-vcodec-enc", .data =3D &mt8195_pdata}, {.compatible =3D "mediatek,mt8196-vcodec-enc", .data =3D &mt8196_pdata}, + {.compatible =3D "mediatek,mt8189-vcodec-enc", .data =3D &mt8189_pdata}, {}, }; MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match); --=20 2.45.2