From nobody Sat Apr 4 04:48:04 2026 Received: from s106b.cyber-folks.pl (s106b.cyber-folks.pl [195.78.66.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6E02314D07; Fri, 20 Mar 2026 17:53:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.78.66.88 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774029204; cv=none; b=Z5QCuFaFdeXk4tDrI62ka+ton9B66RaLYMZ3PyXSc3mFVH6XBJ9aOLFFQUwdTJBavh98XjuM57opHHwrh/gU9a5vneevhnsXduTaJoVjh7ykRY8uUZSjCbdjd3TVvgS4iEMx4VAIgOnZsbIUZhx7yW9o8wFpDC4XrDld3TmFp4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774029204; c=relaxed/simple; bh=gEWOqy+sIeNcPjljvwLLn3I0yJZERiHS40iKFLFPDUA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PjFBEDQBY4NA96ITYf/yP6lZUKMcy3f9Z1nP5mmEOv3A+TJy5kGLEbZwmTZjvORtaq0xzr8L18hHLxSsCKRzKEtHLmu6cMmRUA53Kj/ZZbvoTxKHB/wBNgZ9wUKdHcYkpf2y4NR4eMUlWPDSx8yQ6UMjpbaanmoaymb+CgMGASE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=mmpsystems.pl; spf=pass smtp.mailfrom=mmpsystems.pl; dkim=pass (2048-bit key) header.d=mmpsystems.pl header.i=@mmpsystems.pl header.b=BZ+x97hr; arc=none smtp.client-ip=195.78.66.88 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=mmpsystems.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mmpsystems.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mmpsystems.pl header.i=@mmpsystems.pl header.b="BZ+x97hr" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mmpsystems.pl; s=x; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=IQ5DmSWbpEi6JV0hoLTshUA+7sqOlx1p8QemCOc4Jrk=; b=BZ+x97hrR4odN8AQiWs1lPtUnt teCg9uiv12OvkeVLqUXbl60h0OOupLkb8xSa0aSnR3fo/v8rQiWH1kyb1oeF0HMo6NuEPw5dCd1VT Hy4dpx+KW2/3/oKpvZ+u+2aavrMd+MaNm2FIUOZqBr3t4l1a5hEaP1DuaQ8akAfOGL5kP5x6R7m6U 26XZuLGpvfL1rNqgo8DGarQij2ZmZmXejR8O+oWiqW2DHzgf3MJ8ucCwttXxJ0v6sBPGLpvJSEjS8 Tl8wuYs4EW28nnLw/DG+1oRqAR0/Fz5XKSdZManGmwHONi9iD5LbC14uQXo8HFEQXH8BXTn63avCI CyZj1JMg==; Received: from user-5-173-16-20.play-internet.pl ([5.173.16.20] helo=localhost) by s106.cyber-folks.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w3e2A-00000005OlX-2ODM; Fri, 20 Mar 2026 18:53:18 +0100 From: michal.piekos@mmpsystems.pl Date: Fri, 20 Mar 2026 18:52:30 +0100 Subject: [PATCH v6 1/2] pinctrl: sunxi: pass down flags to pinctrl routines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-rc2-boot-hang-v6-1-74dca70dd60e@mmpsystems.pl> References: <20260320-rc2-boot-hang-v6-0-74dca70dd60e@mmpsystems.pl> In-Reply-To: <20260320-rc2-boot-hang-v6-0-74dca70dd60e@mmpsystems.pl> To: Linus Walleij , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Michal Piekos X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774029161; l=6004; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=SbDK8rvVfMawrpNEZaxW/K09ccUSRo97Vz7GT5bX7kA=; b=/1OQ3yCrz96HA7tlcQyBJ0QatKVtY8ojhYiUuIIU4D6rOZ6gxnuiavwDJjdrqDGwB2KqhEv/y IShshZNI7miB+HpTZ1xnsqo/RszA4fgkkIovRHFz+XBeKB5/BeyhiJQ X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl From: Andre Przywara Recent changes in the Allwinner pinctrl/GPIO IP made us add some quirks, which the new SoCs (A523 family) need to use. We now have a comfortable "flags" field on the per-SoC setup side, to tag those quirks we need, but were translating those flag bits into specific fields for runtime use, in the init routine. Now the newest Allwinner GPIO IP adds even more quirks and exceptions, some of a boolean nature. To avoid inventing various new boolean flags for the runtime struct sunxi_pinctrl, let's just directly pass on the flags variable used by the setup code, so runtime can check for those various quirk bits directly. Rename the "variant" member to "flags", and directly copy the value from the setup code into there. Move the variant masking from the init routine to the functions which actually use the "variant" value. This mostly paves the way for the new A733 IP generation, which needs more quirks to be checked at runtime. Reviewed-by: Chen-Yu Tsai Signed-off-by: Andre Przywara Signed-off-by: Michal Piekos --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 23 ++++++++++++++--------- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/= pinctrl-sunxi.c index c990b6118172..685b79fc0bf8 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -157,6 +157,7 @@ sunxi_pinctrl_desc_find_function_by_name(struct sunxi_p= inctrl *pctl, const char *pin_name, const char *func_name) { + unsigned long variant =3D pctl->flags & SUNXI_PINCTRL_VARIANT_MASK; int i; =20 for (i =3D 0; i < pctl->desc->npins; i++) { @@ -168,7 +169,7 @@ sunxi_pinctrl_desc_find_function_by_name(struct sunxi_p= inctrl *pctl, while (func->name) { if (!strcmp(func->name, func_name) && (!func->variant || - func->variant & pctl->variant)) + func->variant & variant)) return func; =20 func++; @@ -209,6 +210,8 @@ sunxi_pinctrl_desc_find_function_by_pin_and_mux(struct = sunxi_pinctrl *pctl, const u16 pin_num, const u8 muxval) { + unsigned long variant =3D pctl->flags & SUNXI_PINCTRL_VARIANT_MASK; + for (unsigned int i =3D 0; i < pctl->desc->npins; i++) { const struct sunxi_desc_pin *pin =3D pctl->desc->pins + i; struct sunxi_desc_function *func =3D pin->functions; @@ -216,7 +219,7 @@ sunxi_pinctrl_desc_find_function_by_pin_and_mux(struct = sunxi_pinctrl *pctl, if (pin->pin.number !=3D pin_num) continue; =20 - if (pin->variant && !(pctl->variant & pin->variant)) + if (pin->variant && !(variant & pin->variant)) continue; =20 while (func->name) { @@ -1338,6 +1341,7 @@ static int sunxi_pinctrl_add_function(struct sunxi_pi= nctrl *pctl, static int sunxi_pinctrl_build_state(struct platform_device *pdev) { struct sunxi_pinctrl *pctl =3D platform_get_drvdata(pdev); + unsigned long variant =3D pctl->flags & SUNXI_PINCTRL_VARIANT_MASK; void *ptr; int i; =20 @@ -1362,7 +1366,7 @@ static int sunxi_pinctrl_build_state(struct platform_= device *pdev) const struct sunxi_desc_pin *pin =3D pctl->desc->pins + i; struct sunxi_pinctrl_group *group =3D pctl->groups + pctl->ngroups; =20 - if (pin->variant && !(pctl->variant & pin->variant)) + if (pin->variant && !(variant & pin->variant)) continue; =20 group->name =3D pin->pin.name; @@ -1387,11 +1391,11 @@ static int sunxi_pinctrl_build_state(struct platfor= m_device *pdev) const struct sunxi_desc_pin *pin =3D pctl->desc->pins + i; struct sunxi_desc_function *func; =20 - if (pin->variant && !(pctl->variant & pin->variant)) + if (pin->variant && !(variant & pin->variant)) continue; =20 for (func =3D pin->functions; func->name; func++) { - if (func->variant && !(pctl->variant & func->variant)) + if (func->variant && !(variant & func->variant)) continue; =20 /* Create interrupt mapping while we're at it */ @@ -1419,14 +1423,14 @@ static int sunxi_pinctrl_build_state(struct platfor= m_device *pdev) const struct sunxi_desc_pin *pin =3D pctl->desc->pins + i; struct sunxi_desc_function *func; =20 - if (pin->variant && !(pctl->variant & pin->variant)) + if (pin->variant && !(variant & pin->variant)) continue; =20 for (func =3D pin->functions; func->name; func++) { struct sunxi_pinctrl_function *func_item; const char **func_grp; =20 - if (func->variant && !(pctl->variant & func->variant)) + if (func->variant && !(variant & func->variant)) continue; =20 func_item =3D sunxi_pinctrl_find_function_by_name(pctl, @@ -1568,7 +1572,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_dev= ice *pdev, =20 pctl->dev =3D &pdev->dev; pctl->desc =3D desc; - pctl->variant =3D flags & SUNXI_PINCTRL_VARIANT_MASK; + pctl->flags =3D flags; if (flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) { pctl->bank_mem_size =3D D1_BANK_MEM_SIZE; pctl->pull_regs_offset =3D D1_PULL_REGS_OFFSET; @@ -1604,8 +1608,9 @@ int sunxi_pinctrl_init_with_flags(struct platform_dev= ice *pdev, =20 for (i =3D 0, pin_idx =3D 0; i < pctl->desc->npins; i++) { const struct sunxi_desc_pin *pin =3D pctl->desc->pins + i; + unsigned long variant =3D pctl->flags & SUNXI_PINCTRL_VARIANT_MASK; =20 - if (pin->variant && !(pctl->variant & pin->variant)) + if (pin->variant && !(variant & pin->variant)) continue; =20 pins[pin_idx++] =3D pin->pin; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/= pinctrl-sunxi.h index ad26e4de16a8..22bffac1c3f0 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -174,7 +174,7 @@ struct sunxi_pinctrl { unsigned *irq_array; raw_spinlock_t lock; struct pinctrl_dev *pctl_dev; - unsigned long variant; + unsigned long flags; u32 bank_mem_size; u32 pull_regs_offset; u32 dlevel_field_width; --=20 2.43.0 From nobody Sat Apr 4 04:48:04 2026 Received: from s106b.cyber-folks.pl (s106b.cyber-folks.pl [195.78.66.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C334B28469F; Fri, 20 Mar 2026 17:53:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.78.66.88 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774029204; cv=none; b=BdkFUmy1/62cn5MgI8E+FOLIuBlLWLyMkRCLRGti/wDXd5zP19QkA6y6hdH84oWQ2nGKqDhlC6wgQJ9m/yTUAZqVwsDQNc97kdUUOmOqUBQ1iBxoJrSWgYvi825IEWrbjOdMdyzCOwVfj5BxwGnjT3pgdauKM3PmwuzTTcAKQFo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774029204; c=relaxed/simple; bh=rZ8GolW8aT1v8bfrIeIl9S12jlFKdW++KGKQxWnb5Xc=; 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bh=+5pKY2eSspVqqY3nsOZ1gQ+ssdoRyfh9wUR9eYtNMao=; b=T2ahv+dodZUILVWl1mJkUKcm1c UXhL3IZqk0LmYTbQIaEI2eiUFyh2/laid1Qm+Vn+QxBjZ7Q1tDNIMEnFuaplwvoJX/BhaLiyvPe0I NxkP+rtsVABKTtIO11+4x+LMJBxWAwI7NDztdI98ckYavoAtVk4x0QpgjEapvk/pz5a9CUt+v5cRf U3x1AaYrN9ReZfU66Dyau5WKyQQOounL2WoEgikNZGyWvwc1DIileJiGcGse3IGW6dzru0Waqj/YH MN/qbj64eNsleqZzbTYhAsPZiwmrdCz78s2ovMqxG4qJgQWTYS7/om6DBUDOR8Pl5Xg4VgbNatWS1 g/woX1eQ==; Received: from user-5-173-16-20.play-internet.pl ([5.173.16.20] helo=localhost) by s106.cyber-folks.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w3e2B-00000005OnI-1SW7; Fri, 20 Mar 2026 18:53:19 +0100 From: Michal Piekos Date: Fri, 20 Mar 2026 18:52:31 +0100 Subject: [PATCH v6 2/2] pinctrl: sunxi: fix gpiochip_lock_as_irq() failure when pinmux is unknown Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-rc2-boot-hang-v6-2-74dca70dd60e@mmpsystems.pl> References: <20260320-rc2-boot-hang-v6-0-74dca70dd60e@mmpsystems.pl> In-Reply-To: <20260320-rc2-boot-hang-v6-0-74dca70dd60e@mmpsystems.pl> To: Linus Walleij , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Michal Piekos X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774029161; l=2683; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=rZ8GolW8aT1v8bfrIeIl9S12jlFKdW++KGKQxWnb5Xc=; b=JM0Yz0qx+b3ioJx5PketJuePCKqOuSTNIiAD7JoTPWldPKr9KzlNDN2kUXm7Iz89xnHKSBI64 y57MhvTpr2jCB4nvNougc8nI8yNcUgqX2nWYtzvQ2AmyRVJ9cuJh96B X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl Fixes kernel hang during boot due to inability to set up IRQ on AXP313a. The issue is caused by gpiochip_lock_as_irq() which is failing when gpio is in uninitialized state. Solution is to set pinmux to GPIO INPUT in sunxi_pinctrl_irq_request_resources() if it wasn't initialized earlier. Tested on Orange Pi Zero 3. Fixes: 01e10d0272b9 ("pinctrl: sunxi: Implement gpiochip::get_direction()") Reviewed-by: Andre Przywara Reviewed-by: Chen-Yu Tsai Signed-off-by: Michal Piekos --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 20 ++++++++++++++++++-- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 ++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/= pinctrl-sunxi.c index 685b79fc0bf8..d3042e0c9712 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1092,6 +1092,9 @@ static int sunxi_pinctrl_irq_request_resources(struct= irq_data *d) { struct sunxi_pinctrl *pctl =3D irq_data_get_irq_chip_data(d); struct sunxi_desc_function *func; + unsigned int offset; + u32 reg, shift, mask; + u8 disabled_mux, muxval; int ret; =20 func =3D sunxi_pinctrl_desc_find_function_by_pin(pctl, @@ -1099,8 +1102,21 @@ static int sunxi_pinctrl_irq_request_resources(struc= t irq_data *d) if (!func) return -EINVAL; =20 - ret =3D gpiochip_lock_as_irq(pctl->chip, - pctl->irq_array[d->hwirq] - pctl->desc->pin_base); + offset =3D pctl->irq_array[d->hwirq] - pctl->desc->pin_base; + sunxi_mux_reg(pctl, offset, ®, &shift, &mask); + muxval =3D (readl(pctl->membase + reg) & mask) >> shift; + + /* Change muxing to GPIO INPUT mode if at reset value */ + if (pctl->flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) + disabled_mux =3D SUN4I_FUNC_DISABLED_NEW; + else + disabled_mux =3D SUN4I_FUNC_DISABLED_OLD; + + if (muxval =3D=3D disabled_mux) + sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], + SUN4I_FUNC_INPUT); + + ret =3D gpiochip_lock_as_irq(pctl->chip, offset); if (ret) { dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", irqd_to_hwirq(d)); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/= pinctrl-sunxi.h index 22bffac1c3f0..0daf7600e2fb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -86,6 +86,8 @@ =20 #define SUN4I_FUNC_INPUT 0 #define SUN4I_FUNC_IRQ 6 +#define SUN4I_FUNC_DISABLED_OLD 7 +#define SUN4I_FUNC_DISABLED_NEW 15 =20 #define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0) #define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8) --=20 2.43.0