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Fri, 20 Mar 2026 08:33:44 +0100 (CET) Received: by pc63539-2527.se.axis.com (Postfix, from userid 17419) id 9CEC5604326C; Fri, 20 Mar 2026 08:33:44 +0100 (CET) From: =?utf-8?q?Andr=C3=A9_Svensson?= Date: Fri, 20 Mar 2026 08:33:25 +0100 Subject: [PATCH v2 2/2] regulator: da9121: Allow caching BUCK registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-no-gpio-control-v2-2-dbc938e462cb@axis.com> References: <20260320-no-gpio-control-v2-0-dbc938e462cb@axis.com> In-Reply-To: <20260320-no-gpio-control-v2-0-dbc938e462cb@axis.com> To: Support Opensource , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adam Ward CC: , , , Waqar Hameed , =?utf-8?q?Andr=C3=A9_Svensson?= X-Mailer: b4 0.14.3 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PEPF00028D06:EE_|DB8PR02MB5961:EE_ X-MS-Office365-Filtering-Correlation-Id: 7132a89a-33ce-442f-b62a-08de8653050b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|18002099003|56012099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1Dbr8bBrx9WtZmaM/d4FCNJB8ozvFnk6g4R3KQdl/rEDdAi87BvbiTC+kZ+zt43EU69S/uogWtSkS+tH95jsXqce1ScGbcMb7GJs5PQP5CMfyW/8R6i23B/m/URkxD8X0bbot1N5WV8PZilrceMyoSFqPQOTGzg6+t8DoRnPBsrL61H4x2dYEMJ8Ki9OQBas85LmOHG01N4GWdD6WbiFZ9eucZTewYPniWS7sw298fDp8RiIhoGS48typOsH9HLrAPnGOoFxHGss+9c1MDYKmXDwFcF5n56jdN/8S51BdcLUa4bKEyv2y/BR5XPi5cRITE84UyG0Asly7YUoC8pHq7pmT4i67bYjQfawLTazw4L3C2bEvL2oFluS5oYaioaoVT2PvganBn023djjYuRDbZwr78kOqqxMZyr3qKBs18u6a+OUxqRj8nc/YhUNEuDw X-OriginatorOrg: axis.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2026 07:33:45.7704 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7132a89a-33ce-442f-b62a-08de8653050b X-MS-Exchange-CrossTenant-Id: 78703d3c-b907-432f-b066-88f7af9ca3af X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=78703d3c-b907-432f-b066-88f7af9ca3af;Ip=[195.60.68.100];Helo=[mail.axis.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D06.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR02MB5961 Some BUCK registers may change without software writes when GPIO pins are configured for functions DVC/RELOAD/EN. If the board does not use these pin-controlled features, caching is possible. Caching BUCK registers removes unnecessary I2C reads when performing register updates. For example, updating regulator mode can result in two I2C reads, one from the regulator core regulator_set_mode() and one from the DA9121 driver, where da9121_buck_set_mode() uses regmap_update_bits() (read/modify/write). Check for the optional DT property dlg,no-gpio-control. When present, select the regmap configuration that does not mark the BUCK1 register block (DA9121_REG_BUCK_BUCK1_0..DA9121_REG_BUCK_BUCK1_6) as volatile, so that regmap can cache BUCK1 registers and avoid unnecessary I2C reads. The property dlg,no-gpio-control is required to ensure that BUCK1 registers can be cached, as the absence of relevant GPIO DT properties does not imply that the RELOAD/DVC/EN GPIO functions are unused. These functions are provided by DA91xx GPIO pins and may be controlled by external hardware without corresponding GPIO DT properties. The dlg,no-gpio-control property explicitly indicates that none of these GPIO functions are used. The dlg,no-gpio-control property is mutually exclusive with enable-gpios, regardless of whether the referenced GPIO is connected to a GPIO pin or the IC_EN pin, since pulling IC_EN low powers down the regulator and registers are reinitialized at startup, leaving cached values stale. Co-developed-by: Waqar Hameed Signed-off-by: Waqar Hameed Signed-off-by: Andr=C3=A9 Svensson --- drivers/regulator/da9121-regulator.c | 43 ++++++++++++++++++++++++++++++--= ---- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/drivers/regulator/da9121-regulator.c b/drivers/regulator/da912= 1-regulator.c index ef161eb0ca27..2b150bb4d471 100644 --- a/drivers/regulator/da9121-regulator.c +++ b/drivers/regulator/da9121-regulator.c @@ -400,8 +400,14 @@ static int da9121_of_parse_cb(struct device_node *np, GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE, "da9121-enable"); - if (!IS_ERR(ena_gpiod)) + if (!IS_ERR(ena_gpiod)) { + if (of_property_read_bool(chip->dev->of_node, "dlg,no-gpio-control")) { + gpiod_put(ena_gpiod); + dev_err(chip->dev, "dlg,no-gpio-control conflicts with enable-gpios\n"); + return -EINVAL; + } config->ena_gpiod =3D ena_gpiod; + } =20 if (variant_parameters[chip->variant_id].num_bucks =3D=3D 2) { uint32_t ripple_cancel; @@ -864,6 +870,21 @@ static const struct regmap_access_table da9121_volatil= e_table =3D { .n_yes_ranges =3D ARRAY_SIZE(da9121_volatile_ranges), }; =20 +/* + * When GPIO functions DVC/RELOAD/EN are not used, the registers in the ra= nge + * DA9121_REG_BUCK_BUCK1_0 to DA9121_REG_BUCK_BUCK1_6 need not be volatile + * because register writes to these registers can only be performed via I2= C. + */ +static const struct regmap_range da9121_volatile_ranges_no_gpio_ctrl[] =3D= { + regmap_reg_range(DA9121_REG_SYS_STATUS_0, DA9121_REG_SYS_EVENT_2), + regmap_reg_range(DA9121_REG_SYS_GPIO0_0, DA9121_REG_SYS_GPIO2_1), +}; + +static const struct regmap_access_table da9121_volatile_table_no_gpio_ctrl= =3D { + .yes_ranges =3D da9121_volatile_ranges_no_gpio_ctrl, + .n_yes_ranges =3D ARRAY_SIZE(da9121_volatile_ranges_no_gpio_ctrl), +}; + /* DA9121 regmap config for 1 channel variants */ static const struct regmap_config da9121_1ch_regmap_config =3D { .reg_bits =3D 8, @@ -994,10 +1015,18 @@ static int da9121_assign_chip_model(struct i2c_clien= t *i2c, struct da9121 *chip) { const struct regmap_config *regmap; + struct regmap_config regmap_config_1ch =3D da9121_1ch_regmap_config; + struct regmap_config regmap_config_2ch =3D da9121_2ch_regmap_config; + int ret =3D 0; =20 chip->dev =3D &i2c->dev; =20 + if (of_property_read_bool(i2c->dev.of_node, "dlg,no-gpio-control")) { + regmap_config_1ch.volatile_table =3D &da9121_volatile_table_no_gpio_ctrl; + regmap_config_2ch.volatile_table =3D &da9121_volatile_table_no_gpio_ctrl; + } + /* Use configured subtype to select the regulator descriptor index and * register map, common to both consumer and automotive grade variants */ @@ -1005,29 +1034,29 @@ static int da9121_assign_chip_model(struct i2c_clie= nt *i2c, case DA9121_SUBTYPE_DA9121: case DA9121_SUBTYPE_DA9130: chip->variant_id =3D DA9121_TYPE_DA9121_DA9130; - regmap =3D &da9121_1ch_regmap_config; + regmap =3D ®map_config_1ch; break; case DA9121_SUBTYPE_DA9217: chip->variant_id =3D DA9121_TYPE_DA9217; - regmap =3D &da9121_1ch_regmap_config; + regmap =3D ®map_config_1ch; break; case DA9121_SUBTYPE_DA9122: case DA9121_SUBTYPE_DA9131: chip->variant_id =3D DA9121_TYPE_DA9122_DA9131; - regmap =3D &da9121_2ch_regmap_config; + regmap =3D ®map_config_2ch; break; case DA9121_SUBTYPE_DA9220: case DA9121_SUBTYPE_DA9132: chip->variant_id =3D DA9121_TYPE_DA9220_DA9132; - regmap =3D &da9121_2ch_regmap_config; + regmap =3D ®map_config_2ch; break; case DA9121_SUBTYPE_DA9141: chip->variant_id =3D DA9121_TYPE_DA9141; - regmap =3D &da9121_1ch_regmap_config; + regmap =3D ®map_config_1ch; break; case DA9121_SUBTYPE_DA9142: chip->variant_id =3D DA9121_TYPE_DA9142; - regmap =3D &da9121_2ch_regmap_config; + regmap =3D ®map_config_2ch; break; default: return -EINVAL; --=20 2.43.0