From nobody Mon Apr 6 09:13:15 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 020493BC68F; Fri, 20 Mar 2026 15:02:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018941; cv=none; b=FNK5mfi0Rv5PrGoB+eRpfYDGux8vkgi/baRy/K9K2KuUqBI+kyVh5qi2CCm6n0bjWdB1ErKUIhUYIGfEV7gj+VaZmgFh/hP1m4OR7qiihcjn1+gWds3k1uSQrA14oPGwlGS9Wki2xpTMumiSx9lLOBH6pP0fq8QonJhPEMUuPQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018941; c=relaxed/simple; bh=pWnlyVxQ/Qq6MdzK6zaFgmlS11HHGn0FriRfY0ImOJk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=L9z33vythgh3yYUTvfrI+GfkVG4MstH7WH3YvpQYo3gNlE8vTqEYrN5xOMHaG8Sb3aiFW8LNYeh694fcFP0BaardT8LJ0+0CTfSbtP5bK72U88BaR7Km0lOxTgK0EdqGTHToIRh3qLWt0RkXtY9mTzxJFza5nD5NgrSLJ5aW+3w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=aSC3hFMg; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="aSC3hFMg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1774018940; x=1805554940; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=pWnlyVxQ/Qq6MdzK6zaFgmlS11HHGn0FriRfY0ImOJk=; b=aSC3hFMg/f+hNfzbTYXWxhFVLtY5Pw0+Swg6LwA/W+YMakG++5grlrPD poYCXFZxSZn3H3ZfaHZziZBLtbFIcFHZ6x4xwRWXMvqJKKsAMQe3X8TDp BIj4ZztJeZ82m46XZ+1/WDj7fl9ZxGRTnmxz376Qdd0mttDkwUiqoup+P 20oBehAY2f+vsGp0uO8TgsDJbBXxpcXSCVaPQzhLK07N5ks2gCUp5nWo/ dFNvwbOKjt0YEitdyFjnP1H0P8rKLz3/IpVHVgjmt4aAZcNqvOHEGQPxG vomTm43Vk5i+LKsUrZwuWQ1ogfMXUoWWATLPbs+ts0NDLvGK1zRTungi+ A==; X-CSE-ConnectionGUID: Pv4RbQ7sShqou4Z9GlxWPw== X-CSE-MsgGUID: YCGkhLDkSk66jgKdKHZdhQ== X-IronPort-AV: E=Sophos;i="6.23,130,1770620400"; d="scan'208";a="62637230" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Mar 2026 08:02:18 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 20 Mar 2026 08:01:40 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:37 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:01:03 +0100 Subject: [PATCH net-next 07/10] net: lan966x: add PCIe FDMA MTU change support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-7-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 Add MTU change support for the PCIe FDMA path. When the MTU changes, the contiguous ATU-mapped RX and TX buffers are reallocated with the new size. On allocation failure, the old buffers are restored. Signed-off-by: Daniel Machon --- .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 126 +++++++++++++++++= +++- 1 file changed, 125 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c index a92862b386ab..4d69beb41c0c 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -300,9 +300,133 @@ static int lan966x_fdma_pci_init(struct lan966x *lan9= 66x) return 0; } =20 +/* Reset existing rx and tx buffers. */ +static void lan966x_fdma_pci_reset_mem(struct lan966x *lan966x) +{ + struct lan966x_rx *rx =3D &lan966x->rx; + struct lan966x_tx *tx =3D &lan966x->tx; + + memset(rx->fdma.dcbs, 0, rx->fdma.size); + memset(tx->fdma.dcbs, 0, tx->fdma.size); + + fdma_dcbs_init(&rx->fdma, + FDMA_DCB_INFO_DATAL(rx->fdma.db_size), + FDMA_DCB_STATUS_INTR); + + fdma_dcbs_init(&tx->fdma, + FDMA_DCB_INFO_DATAL(tx->fdma.db_size), + FDMA_DCB_STATUS_DONE); + + lan966x_fdma_llp_configure(lan966x, + tx->fdma.atu_region->base_addr, + tx->fdma.channel_id); + lan966x_fdma_llp_configure(lan966x, + rx->fdma.atu_region->base_addr, + rx->fdma.channel_id); +} + +static int lan966x_fdma_pci_reload(struct lan966x *lan966x, int new_mtu) +{ + struct fdma tx_fdma_old =3D lan966x->tx.fdma; + struct fdma rx_fdma_old =3D lan966x->rx.fdma; + u32 old_mtu =3D lan966x->rx.max_mtu; + int err; + + napi_synchronize(&lan966x->napi); + napi_disable(&lan966x->napi); + lan966x_fdma_stop_netdev(lan966x); + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + lan966x->tx.activated =3D false; + + lan966x->rx.max_mtu =3D new_mtu; + + lan966x->tx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->tx.fdma.size =3D fdma_get_size_contiguous(&lan966x->tx.fdma); + lan966x->rx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->rx.fdma.size =3D fdma_get_size_contiguous(&lan966x->rx.fdma); + + err =3D lan966x_fdma_pci_rx_alloc(&lan966x->rx); + if (err) + goto restore; + + err =3D lan966x_fdma_pci_tx_alloc(&lan966x->tx); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dev, &lan966x->rx.fdma); + goto restore; + } + + lan966x_fdma_rx_start(&lan966x->rx); + + /* Free and unmap old memory. */ + fdma_free_coherent_and_unmap(lan966x->dev, &rx_fdma_old); + fdma_free_coherent_and_unmap(lan966x->dev, &tx_fdma_old); + + lan966x_fdma_wakeup_netdev(lan966x); + napi_enable(&lan966x->napi); + + return err; +restore: + + /* No new buffers are allocated at this point. Use the old buffers, + * but reset them before starting the FDMA again. + */ + + memcpy(&lan966x->tx.fdma, &tx_fdma_old, sizeof(struct fdma)); + memcpy(&lan966x->rx.fdma, &rx_fdma_old, sizeof(struct fdma)); + + lan966x->rx.max_mtu =3D old_mtu; + + lan966x_fdma_pci_reset_mem(lan966x); + + lan966x_fdma_rx_start(&lan966x->rx); + lan966x_fdma_wakeup_netdev(lan966x); + napi_enable(&lan966x->napi); + + return err; +} + +static int __lan966x_fdma_pci_reload(struct lan966x *lan966x, int max_mtu) +{ + int err; + u32 val; + + /* Disable the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + /* Flush the CPU queues. */ + readx_poll_timeout(lan966x_qsys_sw_status, + lan966x, + val, + !(QSYS_SW_STATUS_EQ_AVAIL_GET(val)), + READL_SLEEP_US, READL_TIMEOUT_US); + + /* Add a sleep in case there are frames between the queues and the CPU + * port + */ + usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); + + err =3D lan966x_fdma_pci_reload(lan966x, max_mtu); + + /* Enable back the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(1), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + return err; +} + static int lan966x_fdma_pci_resize(struct lan966x *lan966x) { - return -EOPNOTSUPP; + int max_mtu; + + max_mtu =3D lan966x_fdma_get_max_frame(lan966x); + if (max_mtu =3D=3D lan966x->rx.max_mtu) + return 0; + + return __lan966x_fdma_pci_reload(lan966x, max_mtu); } =20 static void lan966x_fdma_pci_deinit(struct lan966x *lan966x) --=20 2.34.1