From nobody Mon Apr 6 09:13:15 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC0CE3C944E; Fri, 20 Mar 2026 15:01:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018911; cv=none; b=sMwoOiZQMXeBYpJ4O4TWOlqOstYu5qRXbME5WMHye/7SBemHPfN2d2ANETVrWIIVAUPtSmUCnQ3XUJHxOZAHLYdoPfPCFTBRRGZ8I2zD8zJI7vUmbD/9XA+0GCxXbQeBgRWj7I+/YO4XRCEqKc0ylPRorqZXKxgg6gaJ+onOKRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018911; c=relaxed/simple; bh=/DPKCeh2DTXoyX0alXK6kXVypfY/O3JYSfcklQi3GQ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=iyj0Vg4lULRz5SbnZT0tEPRgl/n0FuEBZeLiJLmPUdHg5mL//Jzu2vHreWV5fm+Brvc/pp9+qEeILpATYSldLMcfaoyiZvwyGHTaZlNnUTbhBbju6nd4XD6keK/KTTPvO9jJNsuwJY15cxyRbmmNt+MsfLsaP/fBeiLTWey8zh0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=xVEl13E8; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="xVEl13E8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1774018910; x=1805554910; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=/DPKCeh2DTXoyX0alXK6kXVypfY/O3JYSfcklQi3GQ4=; b=xVEl13E8FWOSMZEmp1an9wq8xmlDjEeSSND5c7HM010IRaoPKK4Gqu/n hxCA6eyg4qSebTWzEkY57rW/OroAIGnL8o4IKGaWVY9Dnfz60VOH444tQ MECrIMmgxAmA+MzFAObkVhHIxUNWJsA3SCG+OyvaDiMNdgBKF+vqLzaep JPGDSQpGiXHH1LgeQAmlsDQ33nja9VgBZrshiTfiAfKMCBU+C0QymwWc2 qkxxIHVIRoFWAe4nXbenC2wP2texKspNr02wyyxylBNSDgRRENg3qHzcO MZ2CwnXyugOUNtryfHtN8QopZJe/YhxeE7px2vieuQyTjx8P7LmP1y02c Q==; X-CSE-ConnectionGUID: uoQg81OiQ1aIAKaIXuNqaA== X-CSE-MsgGUID: oMXLbz/jS1KFGfoA9ZicnA== X-IronPort-AV: E=Sophos;i="6.23,130,1770620400"; d="scan'208";a="54967828" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Mar 2026 08:01:48 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 20 Mar 2026 08:01:26 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:23 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:00:59 +0100 Subject: [PATCH net-next 03/10] net: lan966x: add FDMA LLP register write helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-3-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 The FDMA Link List Pointer (LLP) register points to the first DCB in the chain and must be written before the channel is activated. This tells the FDMA engine where to begin DMA transfers. Move the LLP register writes from the channel start/activate functions into the allocation functions and introduce a shared lan966x_fdma_llp_configure() helper. This is needed because the upcoming PCIe FDMA path writes ATU-translated addresses to the LLP registers instead of DMA addresses. Keeping the writes in the shared start/activate path would overwrite these translated addresses. Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 29 ++++++++++--------= ---- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 7b6369e43451..5c5ae8b36058 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -107,6 +107,13 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan9= 66x_rx *rx) return PTR_ERR_OR_ZERO(rx->page_pool); } =20 +static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) +{ + lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); + lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); +} + static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; @@ -123,6 +130,9 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), FDMA_DCB_STATUS_INTR); =20 + lan966x_fdma_llp_configure(lan966x, (u64)fdma->dma, + fdma->channel_id); + return 0; } =20 @@ -132,14 +142,6 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *r= x) struct fdma *fdma =3D &rx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -210,6 +212,9 @@ static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx) =20 fdma_dcbs_init(fdma, 0, 0); =20 + lan966x_fdma_llp_configure(lan966x, (u64)fdma->dma, + fdma->channel_id); + return 0; =20 out: @@ -231,14 +236,6 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx= *tx) struct fdma *fdma =3D &tx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | --=20 2.34.1