From nobody Sat Apr 4 07:50:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AE3C3CBE77; Fri, 20 Mar 2026 15:01:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018913; cv=none; b=NgEyeGIqW+xOED1pVHdCWmdl/gZu8Z2P3OTqdyc07n0t4WeQtk8nGSjxbiFcIoUPXXRpgBE/lo/Z0Fy0ZKox50e9HvC5XXpoIGmzdlXFDAxTaAWWeM7zAalY7SmAJf9HgbxQnB+PJBwSfKOCsRX5d5lZeuDmIcM/p3v9yLpi8Ho= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018913; c=relaxed/simple; bh=oUwDA3FVh/O+XkO9AlTr0IOVgeQfsUFFMQIBIanPYGA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=b4jr04chg4gBSEyEQ8DooBofjSBqZq9nPvAA89qWhByVNJO0zTiK4QIE+XFdtCzXotYRWKhd00VK6zdmo7o5w8u/OTbFlt2anjLo45MowXWyOH9QjnO7HExbq5rOvdDNmu8DkgOPwgIuv8R7aqcaCnEyVykb1KhiKc6a58Z038g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=CvvavWaB; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="CvvavWaB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1774018912; x=1805554912; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=oUwDA3FVh/O+XkO9AlTr0IOVgeQfsUFFMQIBIanPYGA=; b=CvvavWaBRGQSrx3Qt7qViiBY/Ps83AteB/dbq1iaThkq0SwtUsUE6fAj 4mbUFd7uFqynYNYoHQjaxIAU8+nwZ8fcakR6++H/hj+OqetZDVRvEY1Vs 8/Hpy5JtesIh0ftQs/3kB3TYl5qs79SVEIceAWCq2NokShzhZ7Zzd4mp/ GZnIu15saJvX8XopYCSed9w0BUHb8Y+/xVLRC5q0J5EsOc9XLAd2mxJbx wziG0oPSIlf2q9jmb5HDgfLS9aleYaCHIjuYc+HNo3vnRxge9+1/Ny61u rQD1jonvXJ9yXYfBl61YPsAk5NaajIA+iFi50e9bptBVgv4eZRldb6XXt g==; X-CSE-ConnectionGUID: pJu2WHvLRcaRsqolGjnVWA== X-CSE-MsgGUID: 0dhdXO6aR/Ox/2EkOG4QPw== X-IronPort-AV: E=Sophos;i="6.23,130,1770620400"; d="scan'208";a="55385884" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2026 08:01:51 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Fri, 20 Mar 2026 08:01:19 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:16 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:00:57 +0100 Subject: [PATCH net-next 01/10] net: microchip: fdma: rename contiguous dataptr helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-1-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 When the FDMA library was introduced [1], two helpers to get the DMA and virtual address of a DCB, in contiguous memory, were added. These helpers have had no callers until this series. I found the naming I initially used confusing and inconsistent. Rename fdma_dataptr_get_contiguous() and fdma_dataptr_virt_get_contiguous() to fdma_dataptr_dma_addr_contiguous() and fdma_dataptr_virt_addr_contiguous(). This makes the pair symmetric and clarifies what type of address each returns. [1]: commit 30e48a75df9c ("net: microchip: add FDMA library") Signed-off-by: Daniel Machon Tested-by: Herve Codina --- drivers/net/ethernet/microchip/fdma/fdma_api.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.h b/drivers/net/e= thernet/microchip/fdma/fdma_api.h index d91affe8bd98..94f1a6596097 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.h +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.h @@ -197,8 +197,9 @@ static inline int fdma_nextptr_cb(struct fdma *fdma, in= t dcb_idx, u64 *nextptr) * if the dataptr addresses and DCB's are in contiguous memory and the dri= ver * supports XDP. */ -static inline u64 fdma_dataptr_get_contiguous(struct fdma *fdma, int dcb_i= dx, - int db_idx) +static inline u64 fdma_dataptr_dma_addr_contiguous(struct fdma *fdma, + int dcb_idx, + int db_idx) { return fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + (dcb_idx * fdma->n_dbs + db_idx) * fdma->db_size + @@ -209,8 +210,8 @@ static inline u64 fdma_dataptr_get_contiguous(struct fd= ma *fdma, int dcb_idx, * applicable if the dataptr addresses and DCB's are in contiguous memory = and * the driver supports XDP. */ -static inline void *fdma_dataptr_virt_get_contiguous(struct fdma *fdma, - int dcb_idx, int db_idx) +static inline void *fdma_dataptr_virt_addr_contiguous(struct fdma *fdma, + int dcb_idx, int db_idx) { return (u8 *)fdma->dcbs + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + (dcb_idx * fdma->n_dbs + db_idx) * fdma->db_size + --=20 2.34.1 From nobody Sat Apr 4 07:50:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CB5A382379; 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X-CSE-ConnectionGUID: uoQg81OiQ1aIAKaIXuNqaA== X-CSE-MsgGUID: 8/6bsWnzRCKOY/TE9W8hvA== X-IronPort-AV: E=Sophos;i="6.23,130,1770620400"; d="scan'208";a="54967827" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Mar 2026 08:01:48 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 20 Mar 2026 08:01:23 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:20 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:00:58 +0100 Subject: [PATCH net-next 02/10] net: microchip: fdma: add PCIe ATU support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-2-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 When lan966x or lan969x operates as a PCIe endpoint, the internal FDMA engine cannot directly access host memory. Instead, DMA addresses must be translated through the PCIe Address Translation Unit (ATU). The ATU provides outbound windows that map internal addresses to PCIe bus addresses. The ATU outbound address space (0x10000000-0x1fffffff) is divided into six equally-sized regions (~42MB each). When FDMA buffers are allocated, a free ATU region is claimed and programmed with the DMA target address. The FDMA engine then uses the region's base address in its descriptors, and the ATU translates these to the actual DMA addresses on the PCIe bus. Add the required functions and helpers that combine the DMA allocation with the ATU region mapping, effectively adding support for PCIe FDMA. This implementation will also be used by the lan969x, when PCIe FDMA is added for that platform in the future. Signed-off-by: Daniel Machon Tested-by: Herve Codina --- drivers/net/ethernet/microchip/fdma/Makefile | 4 + drivers/net/ethernet/microchip/fdma/fdma_api.c | 33 +++++ drivers/net/ethernet/microchip/fdma/fdma_api.h | 16 +++ drivers/net/ethernet/microchip/fdma/fdma_pci.c | 177 +++++++++++++++++++++= ++++ drivers/net/ethernet/microchip/fdma/fdma_pci.h | 41 ++++++ 5 files changed, 271 insertions(+) diff --git a/drivers/net/ethernet/microchip/fdma/Makefile b/drivers/net/eth= ernet/microchip/fdma/Makefile index cc9a736be357..eed4df6f7158 100644 --- a/drivers/net/ethernet/microchip/fdma/Makefile +++ b/drivers/net/ethernet/microchip/fdma/Makefile @@ -5,3 +5,7 @@ =20 obj-$(CONFIG_FDMA) +=3D fdma.o fdma-y +=3D fdma_api.o + +ifdef CONFIG_MCHP_LAN966X_PCI +fdma-y +=3D fdma_pci.o +endif diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.c b/drivers/net/e= thernet/microchip/fdma/fdma_api.c index e78c3590da9e..072d36773835 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.c +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.c @@ -127,6 +127,39 @@ void fdma_free_phys(struct fdma *fdma) } EXPORT_SYMBOL_GPL(fdma_free_phys); =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +/* Allocate coherent DMA memory and map it in the ATU. */ +int fdma_alloc_coherent_and_map(struct device *dev, struct fdma *fdma, + struct fdma_pci_atu *atu) +{ + int err; + + err =3D fdma_alloc_coherent(dev, fdma); + if (err) + return err; + + fdma->atu_region =3D fdma_pci_atu_region_map(atu, + fdma->dma, + fdma->size); + + if (IS_ERR(fdma->atu_region)) { + fdma_free_coherent(dev, fdma); + return PTR_ERR(fdma->atu_region); + } + + return 0; +} +EXPORT_SYMBOL_GPL(fdma_alloc_coherent_and_map); + +/* Free coherent DMA memory and unmap the memory in the ATU. */ +void fdma_free_coherent_and_unmap(struct device *dev, struct fdma *fdma) +{ + fdma_pci_atu_region_unmap(fdma->atu_region); + fdma_free_coherent(dev, fdma); +} +EXPORT_SYMBOL_GPL(fdma_free_coherent_and_unmap); +#endif + /* Get the size of the FDMA memory */ u32 fdma_get_size(struct fdma *fdma) { diff --git a/drivers/net/ethernet/microchip/fdma/fdma_api.h b/drivers/net/e= thernet/microchip/fdma/fdma_api.h index 94f1a6596097..0e0f8af7463f 100644 --- a/drivers/net/ethernet/microchip/fdma/fdma_api.h +++ b/drivers/net/ethernet/microchip/fdma/fdma_api.h @@ -7,6 +7,10 @@ #include #include =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +#include "fdma_pci.h" +#endif + /* This provides a common set of functions and data structures for interac= ting * with the Frame DMA engine on multiple Microchip switchcores. * @@ -109,6 +113,11 @@ struct fdma { u32 channel_id; =20 struct fdma_ops ops; + +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + /* PCI ATU region for this FDMA instance. */ + struct fdma_pci_atu_region *atu_region; +#endif }; =20 /* Advance the DCB index and wrap if required. */ @@ -234,9 +243,16 @@ int __fdma_dcb_add(struct fdma *fdma, int dcb_idx, u64= info, u64 status, =20 int fdma_alloc_coherent(struct device *dev, struct fdma *fdma); int fdma_alloc_phys(struct fdma *fdma); +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +int fdma_alloc_coherent_and_map(struct device *dev, struct fdma *fdma, + struct fdma_pci_atu *atu); +#endif =20 void fdma_free_coherent(struct device *dev, struct fdma *fdma); void fdma_free_phys(struct fdma *fdma); +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +void fdma_free_coherent_and_unmap(struct device *dev, struct fdma *fdma); +#endif =20 u32 fdma_get_size(struct fdma *fdma); u32 fdma_get_size_contiguous(struct fdma *fdma); diff --git a/drivers/net/ethernet/microchip/fdma/fdma_pci.c b/drivers/net/e= thernet/microchip/fdma/fdma_pci.c new file mode 100644 index 000000000000..d9d3b61a73ef --- /dev/null +++ b/drivers/net/ethernet/microchip/fdma/fdma_pci.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include +#include + +#include "fdma_pci.h" + +/* When the switch operates as a PCIe endpoint, the FDMA engine needs to + * DMA to/from host memory. The FDMA writes to addresses within the endpoi= nt's + * internal Outbound (OB) address space, and the PCIe ATU translates these= to + * DMA addresses on the PCIe bus, targeting host memory. + * + * The ATU supports up to six outbound regions. This implementation divides + * the OB address space into six equally sized chunks. + * + * +-------------+------------+------------+-----+------------+ + * | Index | Region 0 | Region 1 | ... | Region 5 | + * +-------------+------------+------------+-----+------------+ + * | Base addr | 0x10000000 | 0x12aa0000 | ... | 0x1d520000 | + * | Limit addr | 0x12a9ffff | 0x1553ffff | ... | 0x1ffbffff | + * | Target addr | host dma | host dma | ... | host dma | + * +-------------+------------+------------+-----+------------+ + * + * Base addr is the start address of the region within the OB address spac= e. + * Limit addr is the end address of the region within the OB address space. + * Target addr is the host DMA address that the base addr translates to. + */ + +#define FDMA_PCI_ATU_REGION_ALIGN BIT(16) /* 64KB */ +#define FDMA_PCI_ATU_OB_START 0x10000000 +#define FDMA_PCI_ATU_OB_END 0x1fffffff + +#define FDMA_PCI_ATU_ADDR 0x300000 +#define FDMA_PCI_ATU_IDX_SIZE 0x200 +#define FDMA_PCI_ATU_ENA_REG 0x4 +#define FDMA_PCI_ATU_ENA_BIT BIT(31) +#define FDMA_PCI_ATU_LWR_BASE_ADDR 0x8 +#define FDMA_PCI_ATU_UPP_BASE_ADDR 0xc +#define FDMA_PCI_ATU_LIMIT_ADDR 0x10 +#define FDMA_PCI_ATU_LWR_TARGET_ADDR 0x14 +#define FDMA_PCI_ATU_UPP_TARGET_ADDR 0x18 + +static u32 fdma_pci_atu_region_size(void) +{ + return round_down((FDMA_PCI_ATU_OB_END - FDMA_PCI_ATU_OB_START) / + FDMA_PCI_ATU_REGION_MAX, FDMA_PCI_ATU_REGION_ALIGN); +} + +static void __iomem *fdma_pci_atu_addr_get(void __iomem *addr, int offset, + int idx) +{ + return addr + FDMA_PCI_ATU_ADDR + FDMA_PCI_ATU_IDX_SIZE * idx + offset; +} + +static void fdma_pci_atu_region_enable(struct fdma_pci_atu_region *region) +{ + writel(FDMA_PCI_ATU_ENA_BIT, + fdma_pci_atu_addr_get(region->atu->addr, FDMA_PCI_ATU_ENA_REG, + region->idx)); +} + +static void fdma_pci_atu_region_disable(struct fdma_pci_atu_region *region) +{ + writel(0, fdma_pci_atu_addr_get(region->atu->addr, FDMA_PCI_ATU_ENA_REG, + region->idx)); +} + +/* Configure the address translation in the ATU. */ +static void +fdma_pci_atu_configure_translation(struct fdma_pci_atu_region *region) +{ + struct fdma_pci_atu *atu =3D region->atu; + int idx =3D region->idx; + + writel(lower_32_bits(region->base_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_LWR_BASE_ADDR, idx)); + + writel(upper_32_bits(region->base_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_UPP_BASE_ADDR, idx)); + + /* Upper limit register only needed with REGION_SIZE > 4GB. */ + writel(region->limit_addr, + fdma_pci_atu_addr_get(atu->addr, FDMA_PCI_ATU_LIMIT_ADDR, idx)); + + writel(lower_32_bits(region->target_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_LWR_TARGET_ADDR, idx)); + + writel(upper_32_bits(region->target_addr), + fdma_pci_atu_addr_get(atu->addr, + FDMA_PCI_ATU_UPP_TARGET_ADDR, idx)); +} + +/* Find an unused ATU region (target_addr =3D=3D 0). */ +static struct fdma_pci_atu_region * +fdma_pci_atu_region_get_free(struct fdma_pci_atu *atu) +{ + struct fdma_pci_atu_region *regions =3D atu->regions; + + for (int i =3D 0; i < FDMA_PCI_ATU_REGION_MAX; i++) { + if (regions[i].target_addr) + continue; + + return ®ions[i]; + } + + return ERR_PTR(-ENOMEM); +} + +/* Unmap an ATU region, clearing its translation and disabling it. */ +void fdma_pci_atu_region_unmap(struct fdma_pci_atu_region *region) +{ + region->target_addr =3D 0; + + fdma_pci_atu_configure_translation(region); + fdma_pci_atu_region_disable(region); +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_region_unmap); + +/* Map a host DMA address into a free outbound region. */ +struct fdma_pci_atu_region * +fdma_pci_atu_region_map(struct fdma_pci_atu *atu, u64 target_addr, int siz= e) +{ + struct fdma_pci_atu_region *region; + + if (!atu) + return ERR_PTR(-EINVAL); + + if (size > fdma_pci_atu_region_size()) + return ERR_PTR(-E2BIG); + + region =3D fdma_pci_atu_region_get_free(atu); + if (IS_ERR(region)) + return region; + + region->target_addr =3D target_addr; + + /* Enable first, according to datasheet section 3.24.7.4.1 */ + fdma_pci_atu_region_enable(region); + fdma_pci_atu_configure_translation(region); + + return region; +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_region_map); + +/* Translate a host DMA address to the corresponding OB address. */ +u64 fdma_pci_atu_translate_addr(struct fdma_pci_atu_region *region, u64 ad= dr) +{ + return region->base_addr + (addr - region->target_addr); +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_translate_addr); + +/* Initialize ATU, dividing the OB space into equally sized regions. */ +void fdma_pci_atu_init(struct fdma_pci_atu *atu, void __iomem *addr) +{ + struct fdma_pci_atu_region *regions =3D atu->regions; + u32 region_size =3D fdma_pci_atu_region_size(); + + atu->addr =3D addr; + + for (int i =3D 0; i < FDMA_PCI_ATU_REGION_MAX; i++) { + regions[i].base_addr =3D + FDMA_PCI_ATU_OB_START + (i * region_size); + regions[i].limit_addr =3D + regions[i].base_addr + region_size - 1; + regions[i].idx =3D i; + regions[i].atu =3D atu; + } +} +EXPORT_SYMBOL_GPL(fdma_pci_atu_init); diff --git a/drivers/net/ethernet/microchip/fdma/fdma_pci.h b/drivers/net/e= thernet/microchip/fdma/fdma_pci.h new file mode 100644 index 000000000000..359950ccabac --- /dev/null +++ b/drivers/net/ethernet/microchip/fdma/fdma_pci.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _FDMA_PCI_H_ +#define _FDMA_PCI_H_ + +#include + +#define FDMA_PCI_ATU_REGION_MAX 6 +#define FDMA_PCI_DB_ALIGN 128 +#define FDMA_PCI_DB_SIZE(mtu) ALIGN(mtu, FDMA_PCI_DB_ALIGN) + +struct fdma_pci_atu; + +struct fdma_pci_atu_region { + struct fdma_pci_atu *atu; + u64 base_addr; /* Base addr of the OB window */ + u64 limit_addr; /* Limit addr of the OB window */ + u64 target_addr; /* Host DMA address this region maps to */ + int idx; +}; + +struct fdma_pci_atu { + void __iomem *addr; + struct fdma_pci_atu_region regions[FDMA_PCI_ATU_REGION_MAX]; +}; + +/* Initialize ATU, dividing OB space into regions. */ +void fdma_pci_atu_init(struct fdma_pci_atu *atu, void __iomem *addr); + +/* Unmap an ATU region, clearing its translation and disabling it. */ +void fdma_pci_atu_region_unmap(struct fdma_pci_atu_region *region); + +/* Map a host DMA address into a free ATU region. */ +struct fdma_pci_atu_region *fdma_pci_atu_region_map(struct fdma_pci_atu *a= tu, + u64 target_addr, + int size); + +/* Translate a host DMA address to the OB address space. */ +u64 fdma_pci_atu_translate_addr(struct fdma_pci_atu_region *region, u64 ad= dr); + +#endif --=20 2.34.1 From nobody Sat Apr 4 07:50:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC0CE3C944E; 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X-CSE-ConnectionGUID: uoQg81OiQ1aIAKaIXuNqaA== X-CSE-MsgGUID: oMXLbz/jS1KFGfoA9ZicnA== X-IronPort-AV: E=Sophos;i="6.23,130,1770620400"; d="scan'208";a="54967828" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Mar 2026 08:01:48 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 20 Mar 2026 08:01:26 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:23 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:00:59 +0100 Subject: [PATCH net-next 03/10] net: lan966x: add FDMA LLP register write helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-3-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 The FDMA Link List Pointer (LLP) register points to the first DCB in the chain and must be written before the channel is activated. This tells the FDMA engine where to begin DMA transfers. Move the LLP register writes from the channel start/activate functions into the allocation functions and introduce a shared lan966x_fdma_llp_configure() helper. This is needed because the upcoming PCIe FDMA path writes ATU-translated addresses to the LLP registers instead of DMA addresses. Keeping the writes in the shared start/activate path would overwrite these translated addresses. Signed-off-by: Daniel Machon Tested-by: Herve Codina --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 29 ++++++++++--------= ---- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 7b6369e43451..5c5ae8b36058 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -107,6 +107,13 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan9= 66x_rx *rx) return PTR_ERR_OR_ZERO(rx->page_pool); } =20 +static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) +{ + lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); + lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); +} + static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; @@ -123,6 +130,9 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), FDMA_DCB_STATUS_INTR); =20 + lan966x_fdma_llp_configure(lan966x, (u64)fdma->dma, + fdma->channel_id); + return 0; } =20 @@ -132,14 +142,6 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *r= x) struct fdma *fdma =3D &rx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -210,6 +212,9 @@ static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx) =20 fdma_dcbs_init(fdma, 0, 0); =20 + lan966x_fdma_llp_configure(lan966x, (u64)fdma->dma, + fdma->channel_id); + return 0; =20 out: @@ -231,14 +236,6 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx= *tx) struct fdma *fdma =3D &tx->fdma; u32 mask; =20 - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | --=20 2.34.1 From nobody Sat Apr 4 07:50:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AFBC3CA4B3; Fri, 20 Mar 2026 15:01:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018912; cv=none; b=LqTilBI2p2r7knM0fjXJitj+W3PQ+1NtEDwSsIZPv25t/Y9DpOk+gKpQ+fG8+FuAJ1bece7pqwEpxcdTOqo3RGHNpkkuYDfAB6mcAOhCjKpKSF08DkI/StL2hM0kx0wfXAshCuJCW5fElAAadU8Hr0AaDhZMonj7jtnExRFpplw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018912; 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Fri, 20 Mar 2026 08:01:30 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:27 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:01:00 +0100 Subject: [PATCH net-next 04/10] net: lan966x: export FDMA helpers for reuse Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-4-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 Make shared FDMA helpers non-static, so they can be reused by the PCIe FDMA implementation. Signed-off-by: Daniel Machon Tested-by: Herve Codina --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 24 +++++++++++-------= ---- .../net/ethernet/microchip/lan966x/lan966x_main.h | 12 +++++++++++ 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 5c5ae8b36058..870f7d00d325 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -107,8 +107,8 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan96= 6x_rx *rx) return PTR_ERR_OR_ZERO(rx->page_pool); } =20 -static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, - u8 channel_id) +void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) { lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); @@ -136,7 +136,7 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) return 0; } =20 -static void lan966x_fdma_rx_start(struct lan966x_rx *rx) +void lan966x_fdma_rx_start(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -167,7 +167,7 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *rx) lan966x, FDMA_CH_ACTIVATE); } =20 -static void lan966x_fdma_rx_disable(struct lan966x_rx *rx) +void lan966x_fdma_rx_disable(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; @@ -187,7 +187,7 @@ static void lan966x_fdma_rx_disable(struct lan966x_rx *= rx) lan966x, FDMA_CH_DB_DISCARD); } =20 -static void lan966x_fdma_rx_reload(struct lan966x_rx *rx) +void lan966x_fdma_rx_reload(struct lan966x_rx *rx) { struct lan966x *lan966x =3D rx->lan966x; =20 @@ -261,7 +261,7 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx = *tx) lan966x, FDMA_CH_ACTIVATE); } =20 -static void lan966x_fdma_tx_disable(struct lan966x_tx *tx) +void lan966x_fdma_tx_disable(struct lan966x_tx *tx) { struct lan966x *lan966x =3D tx->lan966x; struct fdma *fdma =3D &tx->fdma; @@ -293,7 +293,7 @@ static void lan966x_fdma_tx_reload(struct lan966x_tx *t= x) lan966x, FDMA_CH_RELOAD); } =20 -static void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x) +void lan966x_fdma_wakeup_netdev(struct lan966x *lan966x) { struct lan966x_port *port; int i; @@ -308,7 +308,7 @@ static void lan966x_fdma_wakeup_netdev(struct lan966x *= lan966x) } } =20 -static void lan966x_fdma_stop_netdev(struct lan966x *lan966x) +void lan966x_fdma_stop_netdev(struct lan966x *lan966x) { struct lan966x_port *port; int i; @@ -467,7 +467,7 @@ static struct sk_buff *lan966x_fdma_rx_get_frame(struct= lan966x_rx *rx, return NULL; } =20 -static int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight) +int lan966x_fdma_napi_poll(struct napi_struct *napi, int weight) { struct lan966x *lan966x =3D container_of(napi, struct lan966x, napi); struct lan966x_rx *rx =3D &lan966x->rx; @@ -580,7 +580,7 @@ static int lan966x_fdma_get_next_dcb(struct lan966x_tx = *tx) return -1; } =20 -static void lan966x_fdma_tx_start(struct lan966x_tx *tx) +void lan966x_fdma_tx_start(struct lan966x_tx *tx) { struct lan966x *lan966x =3D tx->lan966x; =20 @@ -798,7 +798,7 @@ static int lan966x_fdma_get_max_mtu(struct lan966x *lan= 966x) return max_mtu; } =20 -static int lan966x_qsys_sw_status(struct lan966x *lan966x) +int lan966x_qsys_sw_status(struct lan966x *lan966x) { return lan_rd(lan966x, QSYS_SW_STATUS(CPU_PORT)); } @@ -842,7 +842,7 @@ static int lan966x_fdma_reload(struct lan966x *lan966x,= int new_mtu) return err; } =20 -static int lan966x_fdma_get_max_frame(struct lan966x *lan966x) +int lan966x_fdma_get_max_frame(struct lan966x *lan966x) { return lan966x_fdma_get_max_mtu(lan966x) + IFH_LEN_BYTES + diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index eea286c29474..a1f590f81cbb 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -561,6 +561,18 @@ int lan966x_fdma_init(struct lan966x *lan966x); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-5-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 Introduce lan966x_fdma_ops to support different FDMA implementations for platform and PCIe. Plumb fdma_init, fdma_deinit, fdma_xmit, fdma_poll and fdma_resize through the ops table, and select the implementation at probe time based on runtime PCI bus detection. Signed-off-by: Daniel Machon Tested-by: Herve Codina --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 2 +- .../net/ethernet/microchip/lan966x/lan966x_main.c | 25 +++++++++++++++++-= ---- .../net/ethernet/microchip/lan966x/lan966x_main.h | 13 +++++++++++ 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_fdma.c index 870f7d00d325..be6e4044d6f5 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -906,7 +906,7 @@ void lan966x_fdma_netdev_init(struct lan966x *lan966x, = struct net_device *dev) return; =20 lan966x->fdma_ndev =3D dev; - netif_napi_add(dev, &lan966x->napi, lan966x_fdma_napi_poll); + netif_napi_add(dev, &lan966x->napi, lan966x->ops->fdma_poll); napi_enable(&lan966x->napi); } =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 47752d3fde0b..9f69634ebb0a 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -26,6 +26,14 @@ =20 #define IO_RANGES 2 =20 +static const struct lan966x_fdma_ops lan966x_fdma_ops =3D { + .fdma_init =3D &lan966x_fdma_init, + .fdma_deinit =3D &lan966x_fdma_deinit, + .fdma_xmit =3D &lan966x_fdma_xmit, + .fdma_poll =3D &lan966x_fdma_napi_poll, + .fdma_resize =3D &lan966x_fdma_change_mtu, +}; + static const struct of_device_id lan966x_match[] =3D { { .compatible =3D "microchip,lan966x-switch" }, { } @@ -391,7 +399,7 @@ static netdev_tx_t lan966x_port_xmit(struct sk_buff *sk= b, =20 spin_lock(&lan966x->tx_lock); if (port->lan966x->fdma) - err =3D lan966x_fdma_xmit(skb, ifh, dev); + err =3D lan966x->ops->fdma_xmit(skb, ifh, dev); else err =3D lan966x_port_ifh_xmit(skb, ifh, dev); spin_unlock(&lan966x->tx_lock); @@ -413,7 +421,7 @@ static int lan966x_port_change_mtu(struct net_device *d= ev, int new_mtu) if (!lan966x->fdma) return 0; =20 - err =3D lan966x_fdma_change_mtu(lan966x); + err =3D lan966x->ops->fdma_resize(lan966x); if (err) { lan_wr(DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(LAN966X_HW_MTU(old_mtu)), lan966x, DEV_MAC_MAXLEN_CFG(port->chip_port)); @@ -1079,6 +1087,11 @@ static int lan966x_reset_switch(struct lan966x *lan9= 66x) return 0; } =20 +static const struct lan966x_fdma_ops *lan966x_get_fdma_ops(struct device *= dev) +{ + return &lan966x_fdma_ops; +} + static int lan966x_probe(struct platform_device *pdev) { struct fwnode_handle *ports, *portnp; @@ -1093,6 +1106,8 @@ static int lan966x_probe(struct platform_device *pdev) platform_set_drvdata(pdev, lan966x); lan966x->dev =3D &pdev->dev; =20 + lan966x->ops =3D lan966x_get_fdma_ops(&pdev->dev); + if (!device_get_mac_address(&pdev->dev, mac_addr)) { ether_addr_copy(lan966x->base_mac, mac_addr); } else { @@ -1232,7 +1247,7 @@ static int lan966x_probe(struct platform_device *pdev) if (err) goto cleanup_fdb; =20 - err =3D lan966x_fdma_init(lan966x); + err =3D lan966x->ops->fdma_init(lan966x); if (err) goto cleanup_ptp; =20 @@ -1245,7 +1260,7 @@ static int lan966x_probe(struct platform_device *pdev) return 0; =20 cleanup_fdma: - lan966x_fdma_deinit(lan966x); + lan966x->ops->fdma_deinit(lan966x); =20 cleanup_ptp: lan966x_ptp_deinit(lan966x); @@ -1273,7 +1288,7 @@ static void lan966x_remove(struct platform_device *pd= ev) =20 lan966x_taprio_deinit(lan966x); lan966x_vcap_deinit(lan966x); - lan966x_fdma_deinit(lan966x); + lan966x->ops->fdma_deinit(lan966x); lan966x_cleanup_ports(lan966x); =20 cancel_delayed_work_sync(&lan966x->stats_work); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index a1f590f81cbb..ed2707079d3e 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -193,6 +193,17 @@ enum vcap_is1_port_sel_rt { VCAP_IS1_PS_RT_FOLLOW_OTHER =3D 7, }; =20 +struct lan966x; + +struct lan966x_fdma_ops { + int (*fdma_init)(struct lan966x *lan966x); + void (*fdma_deinit)(struct lan966x *lan966x); + int (*fdma_xmit)(struct sk_buff *skb, __be32 *ifh, + struct net_device *dev); + int (*fdma_poll)(struct napi_struct *napi, int weight); + int (*fdma_resize)(struct lan966x *lan966x); +}; + struct lan966x_port; =20 struct lan966x_rx { @@ -270,6 +281,8 @@ struct lan966x_skb_cb { struct lan966x { struct device *dev; =20 + const struct lan966x_fdma_ops *ops; + u8 num_phys_ports; struct lan966x_port **ports; =20 --=20 2.34.1 From nobody Sat Apr 4 07:50:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C2093A6B77; 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X-CSE-ConnectionGUID: Pv4RbQ7sShqou4Z9GlxWPw== X-CSE-MsgGUID: USsnBhFgSaWZTqOXGPuHWQ== X-IronPort-AV: E=Sophos;i="6.23,130,1770620400"; d="scan'208";a="62637225" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Mar 2026 08:02:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 20 Mar 2026 08:01:37 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:34 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:01:02 +0100 Subject: [PATCH net-next 06/10] net: lan966x: add PCIe FDMA support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-6-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 Add PCIe FDMA support for lan966x. The PCIe FDMA path uses contiguous DMA buffers mapped through the endpoint's ATU, with memcpy-based frame transfer instead of per-page DMA mappings. With PCIe FDMA, throughput increases from ~33 Mbps (register-based I/O) to ~620 Mbps on an Intel x86 host with a lan966x PCIe card. Signed-off-by: Daniel Machon Tested-by: Herve Codina --- drivers/net/ethernet/microchip/lan966x/Makefile | 4 + .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 329 +++++++++++++++++= ++++ .../net/ethernet/microchip/lan966x/lan966x_main.c | 11 + .../net/ethernet/microchip/lan966x/lan966x_main.h | 11 + .../net/ethernet/microchip/lan966x/lan966x_regs.h | 1 + 5 files changed, 356 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/Makefile b/drivers/net/= ethernet/microchip/lan966x/Makefile index 4cdbe263502c..ac0beceb2a0d 100644 --- a/drivers/net/ethernet/microchip/lan966x/Makefile +++ b/drivers/net/ethernet/microchip/lan966x/Makefile @@ -18,6 +18,10 @@ lan966x-switch-objs :=3D lan966x_main.o lan966x_phylink= .o lan966x_port.o \ lan966x-switch-$(CONFIG_LAN966X_DCB) +=3D lan966x_dcb.o lan966x-switch-$(CONFIG_DEBUG_FS) +=3D lan966x_vcap_debugfs.o =20 +ifdef CONFIG_MCHP_LAN966X_PCI +lan966x-switch-y +=3D lan966x_fdma_pci.o +endif + # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/vcap ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/fdma diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c new file mode 100644 index 000000000000..a92862b386ab --- /dev/null +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "fdma_api.h" +#include "lan966x_main.h" + +static int lan966x_fdma_pci_dataptr_cb(struct fdma *fdma, int dcb, int db, + u64 *dataptr) +{ + u64 addr; + + addr =3D fdma_dataptr_dma_addr_contiguous(fdma, dcb, db); + + *dataptr =3D fdma_pci_atu_translate_addr(fdma->atu_region, addr); + + return 0; +} + +static int lan966x_fdma_pci_nextptr_cb(struct fdma *fdma, int dcb, u64 *ne= xtptr) +{ + u64 addr; + + fdma_nextptr_cb(fdma, dcb, &addr); + + *nextptr =3D fdma_pci_atu_translate_addr(fdma->atu_region, addr); + + return 0; +} + +static int lan966x_fdma_pci_rx_alloc(struct lan966x_rx *rx) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + int err; + + err =3D fdma_alloc_coherent_and_map(lan966x->dev, fdma, &lan966x->atu); + if (err) + return err; + + fdma_dcbs_init(fdma, + FDMA_DCB_INFO_DATAL(fdma->db_size), + FDMA_DCB_STATUS_INTR); + + lan966x_fdma_llp_configure(lan966x, + fdma->atu_region->base_addr, + fdma->channel_id); + + return 0; +} + +static int lan966x_fdma_pci_tx_alloc(struct lan966x_tx *tx) +{ + struct lan966x *lan966x =3D tx->lan966x; + struct fdma *fdma =3D &tx->fdma; + int err; + + err =3D fdma_alloc_coherent_and_map(lan966x->dev, fdma, &lan966x->atu); + if (err) + return err; + + fdma_dcbs_init(fdma, + FDMA_DCB_INFO_DATAL(fdma->db_size), + FDMA_DCB_STATUS_DONE); + + lan966x_fdma_llp_configure(lan966x, + fdma->atu_region->base_addr, + fdma->channel_id); + + return 0; +} + +static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + void *virt_addr; + + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, + fdma->dcb_index, + fdma->db_index); + + lan966x_ifh_get_src_port(virt_addr, src_port); + + if (WARN_ON(*src_port >=3D lan966x->num_phys_ports)) + return FDMA_ERROR; + + return FDMA_PASS; +} + +static struct sk_buff *lan966x_fdma_pci_rx_get_frame(struct lan966x_rx *rx, + u64 src_port) +{ + struct lan966x *lan966x =3D rx->lan966x; + struct fdma *fdma =3D &rx->fdma; + struct sk_buff *skb; + struct fdma_db *db; + u32 data_len; + + /* Get the received frame and create an SKB for it. */ + db =3D fdma_db_next_get(fdma); + data_len =3D FDMA_DCB_STATUS_BLOCKL(db->status); + + skb =3D napi_alloc_skb(&lan966x->napi, data_len); + if (unlikely(!skb)) + return NULL; + + memcpy(skb->data, + fdma_dataptr_virt_addr_contiguous(fdma, + fdma->dcb_index, + fdma->db_index), + data_len); + + skb_put(skb, data_len); + + skb->dev =3D lan966x->ports[src_port]->dev; + skb_pull(skb, IFH_LEN_BYTES); + + if (likely(!(skb->dev->features & NETIF_F_RXFCS))) + skb_trim(skb, skb->len - ETH_FCS_LEN); + + skb->protocol =3D eth_type_trans(skb, skb->dev); + + if (lan966x->bridge_mask & BIT(src_port)) { + skb->offload_fwd_mark =3D 1; + + skb_reset_network_header(skb); + if (!lan966x_hw_offload(lan966x, src_port, skb)) + skb->offload_fwd_mark =3D 0; + } + + skb->dev->stats.rx_bytes +=3D skb->len; + skb->dev->stats.rx_packets++; + + return skb; +} + +static int lan966x_fdma_pci_get_next_dcb(struct fdma *fdma) +{ + struct fdma_db *db; + + for (int i =3D 0; i < fdma->n_dcbs; i++) { + db =3D fdma_db_get(fdma, i, 0); + + if (!fdma_db_is_done(db)) + continue; + if (fdma_is_last(fdma, &fdma->dcbs[i])) + continue; + + return i; + } + + return -1; +} + +static int lan966x_fdma_pci_xmit(struct sk_buff *skb, __be32 *ifh, + struct net_device *dev) +{ + struct lan966x_port *port =3D netdev_priv(dev); + struct lan966x *lan966x =3D port->lan966x; + struct lan966x_tx *tx =3D &lan966x->tx; + struct fdma *fdma =3D &tx->fdma; + int next_to_use; + void *virt_addr; + + next_to_use =3D lan966x_fdma_pci_get_next_dcb(fdma); + + if (next_to_use < 0) { + netif_stop_queue(dev); + return NETDEV_TX_BUSY; + } + + if (skb_put_padto(skb, ETH_ZLEN)) { + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + + skb_tx_timestamp(skb); + + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, next_to_use, 0); + memcpy(virt_addr, ifh, IFH_LEN_BYTES); + memcpy((u8 *)virt_addr + IFH_LEN_BYTES, skb->data, skb->len); + + fdma_dcb_add(fdma, + next_to_use, + 0, + FDMA_DCB_STATUS_SOF | + FDMA_DCB_STATUS_EOF | + FDMA_DCB_STATUS_BLOCKO(0) | + FDMA_DCB_STATUS_BLOCKL(IFH_LEN_BYTES + skb->len + ETH_FCS_LEN)); + + /* Start the transmission. */ + lan966x_fdma_tx_start(tx); + + dev->stats.tx_bytes +=3D skb->len; + dev->stats.tx_packets++; + + dev_consume_skb_any(skb); + + return NETDEV_TX_OK; +} + +static int lan966x_fdma_pci_napi_poll(struct napi_struct *napi, int weight) +{ + struct lan966x *lan966x =3D container_of(napi, struct lan966x, napi); + struct lan966x_rx *rx =3D &lan966x->rx; + struct fdma *fdma =3D &rx->fdma; + int dcb_reload, old_dcb; + struct sk_buff *skb; + int counter =3D 0; + u64 src_port; + + /* Wake any stopped TX queues if a TX DCB is available. */ + if (lan966x_fdma_pci_get_next_dcb(&lan966x->tx.fdma) >=3D 0) + lan966x_fdma_wakeup_netdev(lan966x); + + dcb_reload =3D fdma->dcb_index; + + /* Get all received skbs. */ + while (counter < weight) { + if (!fdma_has_frames(fdma)) + break; + counter++; + switch (lan966x_fdma_pci_rx_check_frame(rx, &src_port)) { + case FDMA_PASS: + break; + case FDMA_ERROR: + fdma_dcb_advance(fdma); + goto allocate_new; + } + skb =3D lan966x_fdma_pci_rx_get_frame(rx, src_port); + fdma_dcb_advance(fdma); + if (!skb) + goto allocate_new; + + napi_gro_receive(&lan966x->napi, skb); + } +allocate_new: + while (dcb_reload !=3D fdma->dcb_index) { + old_dcb =3D dcb_reload; + dcb_reload++; + dcb_reload &=3D fdma->n_dcbs - 1; + + fdma_dcb_add(fdma, + old_dcb, + FDMA_DCB_INFO_DATAL(fdma->db_size), + FDMA_DCB_STATUS_INTR); + + lan966x_fdma_rx_reload(rx); + } + + if (counter < weight && napi_complete_done(napi, counter)) + lan_wr(0xff, lan966x, FDMA_INTR_DB_ENA); + + return counter; +} + +static int lan966x_fdma_pci_init(struct lan966x *lan966x) +{ + struct fdma *rx_fdma =3D &lan966x->rx.fdma; + struct fdma *tx_fdma =3D &lan966x->tx.fdma; + int err; + + if (!lan966x->fdma) + return 0; + + fdma_pci_atu_init(&lan966x->atu, lan966x->regs[TARGET_PCIE_DBI]); + + lan966x->rx.lan966x =3D lan966x; + lan966x->rx.max_mtu =3D lan966x_fdma_get_max_frame(lan966x); + rx_fdma->channel_id =3D FDMA_XTR_CHANNEL; + rx_fdma->n_dcbs =3D FDMA_DCB_MAX; + rx_fdma->n_dbs =3D FDMA_RX_DCB_MAX_DBS; + rx_fdma->priv =3D lan966x; + rx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + rx_fdma->size =3D fdma_get_size_contiguous(rx_fdma); + rx_fdma->ops.nextptr_cb =3D &lan966x_fdma_pci_nextptr_cb; + rx_fdma->ops.dataptr_cb =3D &lan966x_fdma_pci_dataptr_cb; + + lan966x->tx.lan966x =3D lan966x; + tx_fdma->channel_id =3D FDMA_INJ_CHANNEL; + tx_fdma->n_dcbs =3D FDMA_DCB_MAX; + tx_fdma->n_dbs =3D FDMA_TX_DCB_MAX_DBS; + tx_fdma->priv =3D lan966x; + tx_fdma->db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + tx_fdma->size =3D fdma_get_size_contiguous(tx_fdma); + tx_fdma->ops.nextptr_cb =3D &lan966x_fdma_pci_nextptr_cb; + tx_fdma->ops.dataptr_cb =3D &lan966x_fdma_pci_dataptr_cb; + + err =3D lan966x_fdma_pci_rx_alloc(&lan966x->rx); + if (err) + return err; + + err =3D lan966x_fdma_pci_tx_alloc(&lan966x->tx); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dev, rx_fdma); + return err; + } + + lan966x_fdma_rx_start(&lan966x->rx); + + return 0; +} + +static int lan966x_fdma_pci_resize(struct lan966x *lan966x) +{ + return -EOPNOTSUPP; +} + +static void lan966x_fdma_pci_deinit(struct lan966x *lan966x) +{ + if (!lan966x->fdma) + return; + + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + + napi_synchronize(&lan966x->napi); + napi_disable(&lan966x->napi); + + fdma_free_coherent_and_unmap(lan966x->dev, &lan966x->rx.fdma); + fdma_free_coherent_and_unmap(lan966x->dev, &lan966x->tx.fdma); +} + +const struct lan966x_fdma_ops lan966x_fdma_pci_ops =3D { + .fdma_init =3D &lan966x_fdma_pci_init, + .fdma_deinit =3D &lan966x_fdma_pci_deinit, + .fdma_xmit =3D &lan966x_fdma_pci_xmit, + .fdma_poll =3D &lan966x_fdma_pci_napi_poll, + .fdma_resize =3D &lan966x_fdma_pci_resize, +}; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index 9f69634ebb0a..fc14738774ec 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -49,6 +50,9 @@ struct lan966x_main_io_resource { static const struct lan966x_main_io_resource lan966x_main_iomap[] =3D { { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + { TARGET_PCIE_DBI, 0x400000, 0 }, /* 0xe0400000 */ +#endif { TARGET_ORG, 0, 1 }, /* 0xe2000000 */ { TARGET_GCB, 0x4000, 1 }, /* 0xe2004000 */ { TARGET_QS, 0x8000, 1 }, /* 0xe2008000 */ @@ -1089,6 +1093,13 @@ static int lan966x_reset_switch(struct lan966x *lan9= 66x) =20 static const struct lan966x_fdma_ops *lan966x_get_fdma_ops(struct device *= dev) { +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + struct device *parent =3D dev->parent; + + if (parent && parent->parent && dev_is_pci(parent->parent)) + return &lan966x_fdma_pci_ops; +#endif + return &lan966x_fdma_ops; } =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index ed2707079d3e..8fcc51133417 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -17,6 +17,9 @@ #include =20 #include +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +#include +#endif #include #include =20 @@ -288,6 +291,10 @@ struct lan966x { =20 void __iomem *regs[NUM_TARGETS]; =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) + struct fdma_pci_atu atu; +#endif + int shared_queue_sz; =20 u8 base_mac[ETH_ALEN]; @@ -587,6 +594,10 @@ void lan966x_fdma_stop_netdev(struct lan966x *lan966x); int lan966x_fdma_get_max_frame(struct lan966x *lan966x); int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 +#if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) +extern const struct lan966x_fdma_ops lan966x_fdma_pci_ops; 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d="scan'208";a="62637230" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Mar 2026 08:02:18 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 20 Mar 2026 08:01:40 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:37 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:01:03 +0100 Subject: [PATCH net-next 07/10] net: lan966x: add PCIe FDMA MTU change support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-7-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 Add MTU change support for the PCIe FDMA path. When the MTU changes, the contiguous ATU-mapped RX and TX buffers are reallocated with the new size. On allocation failure, the old buffers are restored. Signed-off-by: Daniel Machon Tested-by: Herve Codina --- .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 126 +++++++++++++++++= +++- 1 file changed, 125 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c index a92862b386ab..4d69beb41c0c 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -300,9 +300,133 @@ static int lan966x_fdma_pci_init(struct lan966x *lan9= 66x) return 0; } =20 +/* Reset existing rx and tx buffers. */ +static void lan966x_fdma_pci_reset_mem(struct lan966x *lan966x) +{ + struct lan966x_rx *rx =3D &lan966x->rx; + struct lan966x_tx *tx =3D &lan966x->tx; + + memset(rx->fdma.dcbs, 0, rx->fdma.size); + memset(tx->fdma.dcbs, 0, tx->fdma.size); + + fdma_dcbs_init(&rx->fdma, + FDMA_DCB_INFO_DATAL(rx->fdma.db_size), + FDMA_DCB_STATUS_INTR); + + fdma_dcbs_init(&tx->fdma, + FDMA_DCB_INFO_DATAL(tx->fdma.db_size), + FDMA_DCB_STATUS_DONE); + + lan966x_fdma_llp_configure(lan966x, + tx->fdma.atu_region->base_addr, + tx->fdma.channel_id); + lan966x_fdma_llp_configure(lan966x, + rx->fdma.atu_region->base_addr, + rx->fdma.channel_id); +} + +static int lan966x_fdma_pci_reload(struct lan966x *lan966x, int new_mtu) +{ + struct fdma tx_fdma_old =3D lan966x->tx.fdma; + struct fdma rx_fdma_old =3D lan966x->rx.fdma; + u32 old_mtu =3D lan966x->rx.max_mtu; + int err; + + napi_synchronize(&lan966x->napi); + napi_disable(&lan966x->napi); + lan966x_fdma_stop_netdev(lan966x); + lan966x_fdma_rx_disable(&lan966x->rx); + lan966x_fdma_tx_disable(&lan966x->tx); + lan966x->tx.activated =3D false; + + lan966x->rx.max_mtu =3D new_mtu; + + lan966x->tx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->tx.fdma.size =3D fdma_get_size_contiguous(&lan966x->tx.fdma); + lan966x->rx.fdma.db_size =3D FDMA_PCI_DB_SIZE(lan966x->rx.max_mtu); + lan966x->rx.fdma.size =3D fdma_get_size_contiguous(&lan966x->rx.fdma); + + err =3D lan966x_fdma_pci_rx_alloc(&lan966x->rx); + if (err) + goto restore; + + err =3D lan966x_fdma_pci_tx_alloc(&lan966x->tx); + if (err) { + fdma_free_coherent_and_unmap(lan966x->dev, &lan966x->rx.fdma); + goto restore; + } + + lan966x_fdma_rx_start(&lan966x->rx); + + /* Free and unmap old memory. */ + fdma_free_coherent_and_unmap(lan966x->dev, &rx_fdma_old); + fdma_free_coherent_and_unmap(lan966x->dev, &tx_fdma_old); + + lan966x_fdma_wakeup_netdev(lan966x); + napi_enable(&lan966x->napi); + + return err; +restore: + + /* No new buffers are allocated at this point. Use the old buffers, + * but reset them before starting the FDMA again. + */ + + memcpy(&lan966x->tx.fdma, &tx_fdma_old, sizeof(struct fdma)); + memcpy(&lan966x->rx.fdma, &rx_fdma_old, sizeof(struct fdma)); + + lan966x->rx.max_mtu =3D old_mtu; + + lan966x_fdma_pci_reset_mem(lan966x); + + lan966x_fdma_rx_start(&lan966x->rx); + lan966x_fdma_wakeup_netdev(lan966x); + napi_enable(&lan966x->napi); + + return err; +} + +static int __lan966x_fdma_pci_reload(struct lan966x *lan966x, int max_mtu) +{ + int err; + u32 val; + + /* Disable the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + /* Flush the CPU queues. */ + readx_poll_timeout(lan966x_qsys_sw_status, + lan966x, + val, + !(QSYS_SW_STATUS_EQ_AVAIL_GET(val)), + READL_SLEEP_US, READL_TIMEOUT_US); + + /* Add a sleep in case there are frames between the queues and the CPU + * port + */ + usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); + + err =3D lan966x_fdma_pci_reload(lan966x, max_mtu); + + /* Enable back the CPU port. */ + lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(1), + QSYS_SW_PORT_MODE_PORT_ENA, + lan966x, QSYS_SW_PORT_MODE(CPU_PORT)); + + return err; +} + static int lan966x_fdma_pci_resize(struct lan966x *lan966x) { - return -EOPNOTSUPP; + int max_mtu; + + max_mtu =3D lan966x_fdma_get_max_frame(lan966x); + if (max_mtu =3D=3D lan966x->rx.max_mtu) + return 0; + + return __lan966x_fdma_pci_reload(lan966x, max_mtu); } =20 static void lan966x_fdma_pci_deinit(struct lan966x *lan966x) --=20 2.34.1 From nobody Sat Apr 4 07:50:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F1503C2771; Fri, 20 Mar 2026 15:02:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018932; 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20 Mar 2026 08:02:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Fri, 20 Mar 2026 08:01:43 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:40 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:01:04 +0100 Subject: [PATCH net-next 08/10] net: lan966x: add PCIe FDMA XDP support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-8-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 Add XDP support for the PCIe FDMA path. The PCIe XDP implementation operates on contiguous ATU-mapped buffers with memcpy-based XDP_TX transmit, unlike the platform path which uses page_pool. Only XDP_ACT_BASIC (XDP_PASS, XDP_DROP, XDP_TX, XDP_ABORTED) is supported; XDP_REDIRECT and NDO_XMIT are not available on the PCIe path, as they, to my knowledge, require page_pool-backed buffers. Signed-off-by: Daniel Machon Tested-by: Herve Codina --- .../ethernet/microchip/lan966x/lan966x_fdma_pci.c | 136 +++++++++++++++++= +--- .../net/ethernet/microchip/lan966x/lan966x_main.c | 11 +- .../net/ethernet/microchip/lan966x/lan966x_main.h | 10 ++ .../net/ethernet/microchip/lan966x/lan966x_xdp.c | 6 + 4 files changed, 140 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c b/dr= ivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c index 4d69beb41c0c..f2c8c6aa3d4f 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma_pci.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ =20 +#include + #include "fdma_api.h" #include "lan966x_main.h" =20 @@ -68,10 +70,110 @@ static int lan966x_fdma_pci_tx_alloc(struct lan966x_tx= *tx) return 0; } =20 +static int lan966x_fdma_pci_get_next_dcb(struct fdma *fdma) +{ + struct fdma_db *db; + + for (int i =3D 0; i < fdma->n_dcbs; i++) { + db =3D fdma_db_get(fdma, i, 0); + + if (!fdma_db_is_done(db)) + continue; + if (fdma_is_last(fdma, &fdma->dcbs[i])) + continue; + + return i; + } + + return -1; +} + +static int lan966x_fdma_pci_xmit_xdpf(struct lan966x_port *port, + void *ptr, u32 len) +{ + struct lan966x *lan966x =3D port->lan966x; + struct lan966x_tx *tx =3D &lan966x->tx; + struct fdma *fdma =3D &tx->fdma; + int next_to_use, ret =3D 0; + void *virt_addr; + __be32 *ifh; + + spin_lock(&lan966x->tx_lock); + + next_to_use =3D lan966x_fdma_pci_get_next_dcb(fdma); + + if (next_to_use < 0) { + netif_stop_queue(port->dev); + ret =3D NETDEV_TX_BUSY; + goto out; + } + + ifh =3D ptr; + memset(ifh, 0, IFH_LEN_BYTES); + lan966x_ifh_set_bypass(ifh, 1); + lan966x_ifh_set_port(ifh, BIT_ULL(port->chip_port)); + + /* Get the virtual addr of the next DB and copy frame to it. */ + virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, next_to_use, 0); + memcpy(virt_addr, ptr, len); + + fdma_dcb_add(fdma, + next_to_use, + 0, + FDMA_DCB_STATUS_SOF | + FDMA_DCB_STATUS_EOF | + FDMA_DCB_STATUS_BLOCKO(0) | + FDMA_DCB_STATUS_BLOCKL(len)); + + /* Start the transmission. */ + lan966x_fdma_tx_start(tx); + +out: + spin_unlock(&lan966x->tx_lock); + + return ret; +} + +static int lan966x_xdp_pci_run(struct lan966x_port *port, void *data, + u32 data_len) +{ + struct bpf_prog *xdp_prog =3D port->xdp_prog; + struct lan966x *lan966x =3D port->lan966x; + struct xdp_buff xdp; + u32 act; + + xdp_init_buff(&xdp, lan966x->rx.max_mtu, &port->xdp_rxq); + + xdp_prepare_buff(&xdp, + data - XDP_PACKET_HEADROOM, + IFH_LEN_BYTES + XDP_PACKET_HEADROOM, + data_len - IFH_LEN_BYTES, + false); + + act =3D bpf_prog_run_xdp(xdp_prog, &xdp); + switch (act) { + case XDP_PASS: + return FDMA_PASS; + case XDP_TX: + return lan966x_fdma_pci_xmit_xdpf(port, data, data_len) ? + FDMA_DROP : FDMA_TX; + default: + bpf_warn_invalid_xdp_action(port->dev, xdp_prog, act); + fallthrough; + case XDP_ABORTED: + trace_xdp_exception(port->dev, xdp_prog, act); + fallthrough; + case XDP_DROP: + return FDMA_DROP; + } +} + static int lan966x_fdma_pci_rx_check_frame(struct lan966x_rx *rx, u64 *src= _port) { struct lan966x *lan966x =3D rx->lan966x; struct fdma *fdma =3D &rx->fdma; + struct lan966x_port *port; + struct fdma_db *db; void *virt_addr; =20 virt_addr =3D fdma_dataptr_virt_addr_contiguous(fdma, @@ -83,7 +185,15 @@ static int lan966x_fdma_pci_rx_check_frame(struct lan96= 6x_rx *rx, u64 *src_port) if (WARN_ON(*src_port >=3D lan966x->num_phys_ports)) return FDMA_ERROR; =20 - return FDMA_PASS; + port =3D lan966x->ports[*src_port]; + if (!lan966x_xdp_port_present(port)) + return FDMA_PASS; + + db =3D fdma_db_next_get(fdma); + + return lan966x_xdp_pci_run(port, + virt_addr, + FDMA_DCB_STATUS_BLOCKL(db->status)); } =20 static struct sk_buff *lan966x_fdma_pci_rx_get_frame(struct lan966x_rx *rx, @@ -133,24 +243,6 @@ static struct sk_buff *lan966x_fdma_pci_rx_get_frame(s= truct lan966x_rx *rx, return skb; } =20 -static int lan966x_fdma_pci_get_next_dcb(struct fdma *fdma) -{ - struct fdma_db *db; - - for (int i =3D 0; i < fdma->n_dcbs; i++) { - db =3D fdma_db_get(fdma, i, 0); - - if (!fdma_db_is_done(db)) - continue; - if (fdma_is_last(fdma, &fdma->dcbs[i])) - continue; - - return i; - } - - return -1; -} - static int lan966x_fdma_pci_xmit(struct sk_buff *skb, __be32 *ifh, struct net_device *dev) { @@ -225,6 +317,12 @@ static int lan966x_fdma_pci_napi_poll(struct napi_stru= ct *napi, int weight) case FDMA_ERROR: fdma_dcb_advance(fdma); goto allocate_new; + case FDMA_TX: + fdma_dcb_advance(fdma); + continue; + case FDMA_DROP: + fdma_dcb_advance(fdma); + continue; } skb =3D lan966x_fdma_pci_rx_get_frame(rx, src_port); fdma_dcb_advance(fdma); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.c index fc14738774ec..b42e044da735 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -877,10 +877,13 @@ static int lan966x_probe_port(struct lan966x *lan966x= , u32 p, =20 port->phylink =3D phylink; =20 - if (lan966x->fdma) - dev->xdp_features =3D NETDEV_XDP_ACT_BASIC | - NETDEV_XDP_ACT_REDIRECT | - NETDEV_XDP_ACT_NDO_XMIT; + if (lan966x->fdma) { + dev->xdp_features =3D NETDEV_XDP_ACT_BASIC; + + if (!lan966x_is_pci(lan966x)) + dev->xdp_features |=3D NETDEV_XDP_ACT_REDIRECT | + NETDEV_XDP_ACT_NDO_XMIT; + } =20 err =3D register_netdev(dev); if (err) { diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index 8fcc51133417..2491fe937e36 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -596,6 +596,16 @@ int lan966x_qsys_sw_status(struct lan966x *lan966x); =20 #if IS_ENABLED(CONFIG_MCHP_LAN966X_PCI) extern const struct lan966x_fdma_ops lan966x_fdma_pci_ops; + +static inline bool lan966x_is_pci(struct lan966x *lan966x) +{ + return lan966x->ops =3D=3D &lan966x_fdma_pci_ops; +} +#else +static inline bool lan966x_is_pci(struct lan966x *lan966x) +{ + return false; +} #endif =20 int lan966x_lag_port_join(struct lan966x_port *port, diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c b/drivers= /net/ethernet/microchip/lan966x/lan966x_xdp.c index 9ee61db8690b..9b3356ba6ba8 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_xdp.c @@ -27,6 +27,12 @@ static int lan966x_xdp_setup(struct net_device *dev, str= uct netdev_bpf *xdp) if (old_xdp =3D=3D new_xdp) goto out; =20 + /* PCIe FDMA uses contiguous buffers, so no page_pool reload + * is needed. + */ + if (lan966x_is_pci(lan966x)) + goto out; + err =3D lan966x_fdma_reload_page_pool(lan966x); if (err) { xchg(&port->xdp_prog, old_prog); --=20 2.34.1 From nobody Sat Apr 4 07:50:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C02123C7DE0; Fri, 20 Mar 2026 15:02:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018931; cv=none; b=QM4aDPSmvyz7QuG+xYjvxdYkBDFNphZXTyQCFOjrx9ISxda/s9xrrYr7aFd0H5m/cpTPOW6b5kK/CkhkO+3Tnuiahh1arpYJGIHgThyQiD2PJtt5hRyatQ7k0mIHuAYj4tdG9Y8HpQMMUNgJ1s5ecC6myGs+qebk7dqf8CnoXEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Fri, 20 Mar 2026 08:01:47 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:44 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:01:05 +0100 Subject: [PATCH net-next 09/10] misc: lan966x-pci: dts: extend cpu reg to cover PCIE DBI space Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-9-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 The ATU outbound windows used by the FDMA engine are programmed through registers at offset 0x400000+, which falls outside the current cpu reg mapping. Extend the cpu reg size from 0x100000 (1MB) to 0x800000 (8MB) to cover the full PCIE DBI and iATU register space. Signed-off-by: Daniel Machon Tested-by: Herve Codina --- drivers/misc/lan966x_pci.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7b196b0a0eb6..7bb726550caf 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -135,7 +135,7 @@ lan966x_phy1: ethernet-lan966x_phy@2 { =20 switch: switch@e0000000 { compatible =3D "microchip,lan966x-switch"; - reg =3D <0xe0000000 0x0100000>, + reg =3D <0xe0000000 0x0800000>, <0xe2000000 0x0800000>; reg-names =3D "cpu", "gcb"; =20 --=20 2.34.1 From nobody Sat Apr 4 07:50:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F1013CF67F; Fri, 20 Mar 2026 15:02:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018932; cv=none; b=UhslwNSpDOWRaZmplAe9WNxeCt2Aia/VrSm/iAxZ9UFeHatjCoJZZtfaY9YIyoE41sbmRy8GxV3F48AkJw1a71Sq/TDbce+p0/Bq86GQhHGXE9HINvh7923rV8qqUWzal1uOvOCnXllnggNaUV7kCVmaQh7JVr08nAFzr7yPYmU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774018932; c=relaxed/simple; bh=79+vPV9e+OqWLz3onwlm7PbN+48buNA31r4Z7PIHFhY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=B/NZAn7YiFVtNfmNe+ro/2doAMKrr1i7nlzqGTj7U2IJb4WHNFdg8uwu/yz2bZUF2EX6GujVzKHrPEaO1wvOaVgorok65+gmkzaeyAZQ1itClqktX7FSFlSRXSAICTMh3SGRUyk3dJ7kz8MnNkZCHfKGbhGcSBahM0TGFAS0ywI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=QDw7Gk2T; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="QDw7Gk2T" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1774018931; x=1805554931; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=79+vPV9e+OqWLz3onwlm7PbN+48buNA31r4Z7PIHFhY=; b=QDw7Gk2TQNVE1G4S0U3vZ0Ip50Zdrlf83SPE+XvL95we6HtO8bn9b2KJ 5z/XO7Wj1mGtVTepql+6rErwWENSiiZjrzzUo/PKx1IQlhooug7rKfEOT G/PwqGddoKE1Mvsa1icLPXXrv1xFQxwy9ovR5upvcOxPd7C//coPSc4ZI XH/qasj1yhFJ/4NyU4XQO4TYoKhepk7g8fM6KGOlR6wwDEkyn/3rtuEKJ fG5tPAavIsrj9DigmdWSrgFXI68LNIrYGnrcxUIkZ47ONGQsY3PcvnBhB 6aJ2KpPSmEb9pTOn8MwZauMTbPZzoIWqU9bTTRdR0NEEjt+t5Qijo2stB Q==; X-CSE-ConnectionGUID: PI7UURBMS4qqPJi2jv9mYA== X-CSE-MsgGUID: 0+Gqk1r+TmiOADuDEkGwnA== X-IronPort-AV: E=Sophos;i="6.23,130,1770620400"; d="scan'208";a="62637215" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2026 08:02:08 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Fri, 20 Mar 2026 08:01:50 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 20 Mar 2026 08:01:47 -0700 From: Daniel Machon Date: Fri, 20 Mar 2026 16:01:06 +0100 Subject: [PATCH net-next 10/10] misc: lan966x-pci: dts: add fdma interrupt to overlay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-lan966x-pci-fdma-v1-10-ef54cb9b0c4b@microchip.com> References: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> In-Reply-To: <20260320-lan966x-pci-fdma-v1-0-ef54cb9b0c4b@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman CC: , , X-Mailer: b4 0.14.3 Add the fdma interrupt (OIC interrupt 14) to the lan966x PCI device tree overlay, enabling FDMA-based frame injection/extraction when the switch is connected over PCIe. Signed-off-by: Daniel Machon Tested-by: Herve Codina --- drivers/misc/lan966x_pci.dtso | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7bb726550caf..5bb12dbc0843 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -141,8 +141,9 @@ switch: switch@e0000000 { =20 interrupt-parent =3D <&oic>; interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names =3D "xtr", "ana"; + interrupt-names =3D "xtr", "fdma", "ana"; =20 resets =3D <&reset 0>; reset-names =3D "switch"; --=20 2.34.1