From nobody Mon Apr 6 11:51:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A3F53D902B; Fri, 20 Mar 2026 16:47:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025260; cv=none; b=GchYv4uMib7s8Lcmc168+GjocKvsW97Zo5eX4IfEm0rjd8M1XFS23CB+mayrjsGa77Eq62/1mQ1zHT0lGMp00tJg3RDJkr0Iq6HvJ72y9XTe4+p984gXTS/1CU+7sHUaLvmkpAh0WmtJL+b7Ax515JHp/nTxLZORPSIyBQbcGeA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025260; c=relaxed/simple; bh=+jSC2BcOr5bTFiGTzqJGWVjWkhUc4jNiP7GFwpFjfWs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nG6l/2pT4GHgPE4WGuJbZJMb5G5SdpboFZlQH0qd+rGfSUBEIhDarbPKTUvv+fqOMhhLqqogkGfE1Oo01P7xIrUx+6clf48/oFoTQbZjkm9O5Blyc+kym6XnMF4hOunV8G+stp8bEDlHc2PV+6DblImbYs9GDCBDkeRbucEMyfw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E96bmnpf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E96bmnpf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8372C4CEF7; Fri, 20 Mar 2026 16:47:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774025260; bh=+jSC2BcOr5bTFiGTzqJGWVjWkhUc4jNiP7GFwpFjfWs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=E96bmnpfmHgxHqt2Jnj7OMb8dMAA7xDxsiR2OZLPBhUKCaJVA55ysug/aHl7DoFK9 4LgEqs4ZbThdc9M1y/zRpGMV4mumK7L4hmMtnS+RFJ2yWZpLAaRSrIs1aG3Wbrxls7 Flkb1fkPm4srpes/8FVDPN9yVja8QZSZ4+i6tancyVPg+wjDzbntznboIN6skpvxaj kZ7i8OEv3yZGGjd1IRFRNW9RBEXrlGH/uFYNylE2FVuICOKXyVNmSeQlXsaqkFWchZ UHkFmTuQv42HlT12WlLJaKr4GloKp+dVRMQ0zZ9z5Gq/p7GaOD8qP/w4e5z0OClH/U P3+qWdojv7/xQ== From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:18 -0500 Subject: [PATCH 5/5] arm64: dts: arm/corstone1000: Add corstone-1000-a320 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-dt-corstone1000-a320-v1-5-a549dfcfe8da@kernel.org> References: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> In-Reply-To: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: Frazer Carsley , Hugues Kamba Mpiana , Abdellatif El Khlifi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.15-dev The Corstone-1000-a320 is a Corstone-1000 derivative with Cortex-A320 cores, GIC-600, and Ethos-U85 NPU. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts | 15 ++++ arch/arm64/boot/dts/arm/corstone1000-a320.dtsi | 91 +++++++++++++++++++= ++++ 3 files changed, 107 insertions(+) diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index f30ee045dc95..fa035c68991a 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,4 +7,5 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-a320-fvp.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts b/arch/arm64= /boot/dts/arm/corstone1000-a320-fvp.dts new file mode 100644 index 000000000000..0f72af78b5e1 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000-a320.dtsi" +#include "corstone1000-fvp.dtsi" + +/ { + model =3D "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)"; + compatible =3D "arm,corstone1000-a320-fvp"; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi b/arch/arm64/bo= ot/dts/arm/corstone1000-a320.dtsi new file mode 100644 index 000000000000..f0937914350c --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + */ + +#include + +#include "corstone1000.dtsi" + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpus: cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a320"; + reg =3D <0 0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a320"; + reg =3D <0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a320"; + reg =3D <0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a320"; + reg =3D <0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + sram: sram@2400000 { + compatible =3D "mmio-sram"; + reg =3D <0x02400000 0x200000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + }; + + gic: interrupt-controller@1c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-controller; + reg =3D <0x1c000000 0x10000>, + <0x1c040000 0x80000>; + interrupts =3D ; + }; + + + soc { + npu@1a050000 { + compatible =3D "arm,corstone1000-ethos-u85", "arm,ethos-u85"; + reg =3D <0x1a050000 0x1400>; + interrupts =3D ; + clocks =3D <&refclk100mhz>, <&refclk100mhz>; + clock-names =3D "core", "apb"; + sram =3D <&sram>; + }; + }; +}; --=20 2.51.0