From nobody Mon Apr 6 11:51:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A1AA3D88FD; Fri, 20 Mar 2026 16:47:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025259; cv=none; b=MCxbAFn8SJmpNICiy/1CcuJoq0mpYJlHuwUCE+ntXOmkQk5h+JGflkFoRaIQGIHk179MDBiA8ltZShYG/8fyhG/hkxKoljmfI40nLXhNP+61arfzkYQI1v0XCD0sK4u0m0UccbfeATZyJVQ311r3ONLcDM2TcNSd2qRCSfoc8gU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025259; c=relaxed/simple; bh=Jfx0Fsvzz4Z6n6+m6jipZ+hJb8968gAtSbrKrHZMyAE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hjksHaR5a3kcAK9RVZD38vxXkwX8DsuvGaItxm39ujeqwmOW/pLaV0X0g6qvF9JKYIn9YePDjzN8Id124MXaemW3FgRujIKupBROJZTeUMwul1bQ9WuKH1xmGXOgJU/F5Z97NIb19+XiQIvGJ4L4rGzD+/ucxEOl3JzRnh/JlqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YBtnrY8L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YBtnrY8L" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DC151C4CEF7; Fri, 20 Mar 2026 16:47:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774025259; bh=Jfx0Fsvzz4Z6n6+m6jipZ+hJb8968gAtSbrKrHZMyAE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YBtnrY8L3oIHbXjfd01SOf8UaHSrAfFf7eZE/bKnS74AuwaZaWjx2oJKvX1DhJ9ej y+tHKPjx0/L7gyPe6jiJTSYW9ADdp/vQq7tFHSTuDkZbnHvG3voieqFz0j2t9UP7Um K18tGWBNnNqAHO9NqVuHGCSEVbWPfBTJa3kZ4FHXt+Iqz1a+dj4EVMXnAYjHG6P5Oh fD/iHAoFnz0sDuTyyyzjHNBCypHt3rZv00QUU7RqZj8vkAmGqLi5vcV8TCH1cJX9aQ 1bILUREgvCtt0AI6va+gDobtRmi+SaFF7x/8mwnEV9pkA93uZGJMycFdN4CGgukXDz MIlnJPggRZQvA== From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:17 -0500 Subject: [PATCH 4/5] arm64: dts: arm/corstone1000: Move FVP peripherals to separate .dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-dt-corstone1000-a320-v1-4-a549dfcfe8da@kernel.org> References: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> In-Reply-To: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: Frazer Carsley , Hugues Kamba Mpiana , Abdellatif El Khlifi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.15-dev The FVPs have a common set of peripherals specific to the FVP. Move these to a separate .dtsi so they can be shared across FVP platforms. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 36 +--------------------- arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi | 44 +++++++++++++++++++++++= ++++ 2 files changed, 45 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot= /dts/arm/corstone1000-fvp.dts index e479c79c1ea7..fac0999b1901 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -8,46 +8,12 @@ /dts-v1/; =20 #include "corstone1000.dtsi" +#include "corstone1000-fvp.dtsi" =20 / { model =3D "ARM Corstone1000 FVP (Fixed Virtual Platform)"; compatible =3D "arm,corstone1000-fvp"; =20 - smsc: ethernet@4010000 { - compatible =3D "smsc,lan91c111"; - reg =3D <0x40100000 0x10000>; - phy-mode =3D "mii"; - interrupts =3D ; - reg-io-width =3D <2>; - }; - - vmmc_v3_3d: regulator-vmmc { - compatible =3D "regulator-fixed"; - regulator-name =3D "vmmc_supply"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - }; - - sdmmc0: mmc@40300000 { - compatible =3D "arm,pl18x", "arm,primecell"; - reg =3D <0x40300000 0x1000>; - interrupts =3D ; - max-frequency =3D <12000000>; - vmmc-supply =3D <&vmmc_v3_3d>; - clocks =3D <&smbclk>, <&refclk100mhz>; - clock-names =3D "smclk", "apb_pclk"; - }; - - sdmmc1: mmc@50000000 { - compatible =3D "arm,pl18x", "arm,primecell"; - reg =3D <0x50000000 0x10000>; - interrupts =3D ; - max-frequency =3D <12000000>; - vmmc-supply =3D <&vmmc_v3_3d>; - clocks =3D <&smbclk>, <&refclk100mhz>; - clock-names =3D "smclk", "apb_pclk"; - }; cpus: cpus { #address-cells =3D <2>; #size-cells =3D <0>; diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi b/arch/arm64/boo= t/dts/arm/corstone1000-fvp.dtsi new file mode 100644 index 000000000000..dc6d77446e8f --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/ { + smsc: ethernet@4010000 { + compatible =3D "smsc,lan91c111"; + reg =3D <0x40100000 0x10000>; + phy-mode =3D "mii"; + interrupts =3D ; + reg-io-width =3D <2>; + }; + + vmmc_v3_3d: regulator-vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vmmc_supply"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible =3D "arm,pl18x", "arm,primecell"; + reg =3D <0x40300000 0x1000>; + interrupts =3D ; + max-frequency =3D <12000000>; + vmmc-supply =3D <&vmmc_v3_3d>; + clocks =3D <&smbclk>, <&refclk100mhz>; + clock-names =3D "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible =3D "arm,pl18x", "arm,primecell"; + reg =3D <0x50000000 0x10000>; + interrupts =3D ; + max-frequency =3D <12000000>; + vmmc-supply =3D <&vmmc_v3_3d>; + clocks =3D <&smbclk>, <&refclk100mhz>; + clock-names =3D "smclk", "apb_pclk"; + }; +}; --=20 2.51.0