From nobody Mon Apr 6 11:51:56 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9434B3D47CE; Fri, 20 Mar 2026 16:47:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025256; cv=none; b=L4oEgUjqb+Gkfidn5tHtC5l+pHPOsafc5sA01AMMwKfrd/Q/nEflvtU6VGAyzILfM6cVXoHPEHwEbqh8RAD77F8mWEz3Jx20fMbXL8W0TuRKell+YLbzr2LfqJI3c6HxUFrswFKKs8J0SW+/rXbcCvrzOwRuoBm++ECZmkCA8aQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025256; c=relaxed/simple; bh=MyZDEC4YA2XUVdCFPz/d1D9B38/FSwdqJVLDQRdEA5o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FRGnkWlFT8jihnoR4G96m5Ilvmz5AZpj+6vWARhPGTRrrSfgdvDTs0docEaPJpgaSl5g4xWwiblc4s9U6CglbIt93Jofr2Vqb+PjcIPEijIgEuBQdbHs3c0FodNwav1XzEAtzMKLiQtIFCG4PKzRs++pv19iiCnUtaIdXnB0vCc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OISUcGy1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OISUcGy1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF44AC4CEF7; Fri, 20 Mar 2026 16:47:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774025256; bh=MyZDEC4YA2XUVdCFPz/d1D9B38/FSwdqJVLDQRdEA5o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=OISUcGy1sFHRTsHjircV7QmS8szmkxU1QAwSH7YXs41U4R2Hhz9H4YK1G8YVmSAnR BJySdaPPw31dEuF3cmEDdSxIvu7ojrwOHn0bKgeV1xUD3AZ4VDDVlzg8NaqkAxbFzD CDHPvS9ciB3Kx36J+STgqedpS9pL9aqIjsvnhjdFM+y3gBLfzpT0PsE2lDpbC79lY3 hoPjTVMgonxxyTqMMsFXepGWLNQSTO3RPMcVniHOzBjqwPfemZ60jRJOEQbdIKOw4t NkYktN8FVXWdQ914SrrEOpINGmbH/57DrSFMUV7Wf/yjm6nMX/3Gf+AgtJCRf4hClj NQG/vGqF28snQ== From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:14 -0500 Subject: [PATCH 1/5] dt-bindings: arm,corstone1000: Add "arm,corstone1000-a320-fvp" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-dt-corstone1000-a320-v1-1-a549dfcfe8da@kernel.org> References: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> In-Reply-To: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: Frazer Carsley , Hugues Kamba Mpiana , Abdellatif El Khlifi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.15-dev The Arm Corstone1000-A320 is a variation of the Corstone1000 with Cortex-A320 cores and an Ethos-U85 NPU. An FVP for the platform is available here[1]. [1] https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Plat= forms/IoT%20FVPs Signed-off-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/arm,corstone1000.yaml | 15 ++++++++++-= ---- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/= Documentation/devicetree/bindings/arm/arm,corstone1000.yaml index cff1cdaadb13..48ab3356e383 100644 --- a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -15,11 +15,11 @@ description: |+ provides a flexible compute architecture that combines Cortex=E2=80=91A = and Cortex=E2=80=91M processors. =20 - Support for Cortex=E2=80=91A32, Cortex=E2=80=91A35 and Cortex=E2=80=91A5= 3 processors. Two expansion - systems for M-Class (or other) processors for adding sensors, connectivi= ty, - video, audio and machine learning at the edge System and security IPs to= build - a secure SoC for a range of rich IoT applications, for example gateways,= smart - cameras and embedded systems. + Support for Cortex=E2=80=91A32, Cortex=E2=80=91A35, Cortex=E2=80=91A53 a= nd Cortex-A320 processors. + Two expansion systems for M-Class (or other) processors for adding senso= rs, + connectivity, video, audio and machine learning at the edge System and + security IPs to build a secure SoC for a range of rich IoT applications,= for + example gateways, smart cameras and embedded systems. =20 Integrated Secure Enclave providing hardware Root of Trust and supporting seamless integration of the optional CryptoCell=E2=84=A2-312 cryptograph= ic @@ -39,6 +39,11 @@ properties: implementation of this system. See ARM ecosystems FVP's. items: - const: arm,corstone1000-fvp + - description: Corstone1000-A320 FVP is the Fixed Virtual Platform + implementation of this system with Cortex-A320 cores and Ethos-U= 85 + NPU. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-a320-fvp =20 additionalProperties: true =20 --=20 2.51.0