From nobody Mon Apr 6 10:32:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9434B3D47CE; Fri, 20 Mar 2026 16:47:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025256; cv=none; b=L4oEgUjqb+Gkfidn5tHtC5l+pHPOsafc5sA01AMMwKfrd/Q/nEflvtU6VGAyzILfM6cVXoHPEHwEbqh8RAD77F8mWEz3Jx20fMbXL8W0TuRKell+YLbzr2LfqJI3c6HxUFrswFKKs8J0SW+/rXbcCvrzOwRuoBm++ECZmkCA8aQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025256; c=relaxed/simple; bh=MyZDEC4YA2XUVdCFPz/d1D9B38/FSwdqJVLDQRdEA5o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FRGnkWlFT8jihnoR4G96m5Ilvmz5AZpj+6vWARhPGTRrrSfgdvDTs0docEaPJpgaSl5g4xWwiblc4s9U6CglbIt93Jofr2Vqb+PjcIPEijIgEuBQdbHs3c0FodNwav1XzEAtzMKLiQtIFCG4PKzRs++pv19iiCnUtaIdXnB0vCc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OISUcGy1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OISUcGy1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF44AC4CEF7; Fri, 20 Mar 2026 16:47:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774025256; bh=MyZDEC4YA2XUVdCFPz/d1D9B38/FSwdqJVLDQRdEA5o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=OISUcGy1sFHRTsHjircV7QmS8szmkxU1QAwSH7YXs41U4R2Hhz9H4YK1G8YVmSAnR BJySdaPPw31dEuF3cmEDdSxIvu7ojrwOHn0bKgeV1xUD3AZ4VDDVlzg8NaqkAxbFzD CDHPvS9ciB3Kx36J+STgqedpS9pL9aqIjsvnhjdFM+y3gBLfzpT0PsE2lDpbC79lY3 hoPjTVMgonxxyTqMMsFXepGWLNQSTO3RPMcVniHOzBjqwPfemZ60jRJOEQbdIKOw4t NkYktN8FVXWdQ914SrrEOpINGmbH/57DrSFMUV7Wf/yjm6nMX/3Gf+AgtJCRf4hClj NQG/vGqF28snQ== From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:14 -0500 Subject: [PATCH 1/5] dt-bindings: arm,corstone1000: Add "arm,corstone1000-a320-fvp" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-dt-corstone1000-a320-v1-1-a549dfcfe8da@kernel.org> References: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> In-Reply-To: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: Frazer Carsley , Hugues Kamba Mpiana , Abdellatif El Khlifi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.15-dev The Arm Corstone1000-A320 is a variation of the Corstone1000 with Cortex-A320 cores and an Ethos-U85 NPU. An FVP for the platform is available here[1]. [1] https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Plat= forms/IoT%20FVPs Signed-off-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/arm,corstone1000.yaml | 15 ++++++++++-= ---- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/= Documentation/devicetree/bindings/arm/arm,corstone1000.yaml index cff1cdaadb13..48ab3356e383 100644 --- a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -15,11 +15,11 @@ description: |+ provides a flexible compute architecture that combines Cortex=E2=80=91A = and Cortex=E2=80=91M processors. =20 - Support for Cortex=E2=80=91A32, Cortex=E2=80=91A35 and Cortex=E2=80=91A5= 3 processors. Two expansion - systems for M-Class (or other) processors for adding sensors, connectivi= ty, - video, audio and machine learning at the edge System and security IPs to= build - a secure SoC for a range of rich IoT applications, for example gateways,= smart - cameras and embedded systems. + Support for Cortex=E2=80=91A32, Cortex=E2=80=91A35, Cortex=E2=80=91A53 a= nd Cortex-A320 processors. + Two expansion systems for M-Class (or other) processors for adding senso= rs, + connectivity, video, audio and machine learning at the edge System and + security IPs to build a secure SoC for a range of rich IoT applications,= for + example gateways, smart cameras and embedded systems. =20 Integrated Secure Enclave providing hardware Root of Trust and supporting seamless integration of the optional CryptoCell=E2=84=A2-312 cryptograph= ic @@ -39,6 +39,11 @@ properties: implementation of this system. See ARM ecosystems FVP's. items: - const: arm,corstone1000-fvp + - description: Corstone1000-A320 FVP is the Fixed Virtual Platform + implementation of this system with Cortex-A320 cores and Ethos-U= 85 + NPU. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-a320-fvp =20 additionalProperties: true =20 --=20 2.51.0 From nobody Mon Apr 6 10:32:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40DA83D522C; Fri, 20 Mar 2026 16:47:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025257; cv=none; b=oSTWJrZR0epsu4+i9MqQ4uOn2UpFgcRmg2hQZ1xqtQ0FvMsH/7RGUtJr01QKdyDasSHojY92k1ItPG+hMgImf98gzPpa2oJXRnbcasrVul8S09TzSXlusm0iA6p0BE32iAY9mTUWXxQSFbAdoZzqa1//Cw1i3fJXXF4r943/sWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025257; c=relaxed/simple; bh=WdWA2hrSgUxDYtn4CcB4fFRlpQtCztod+x049Hswyq8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F9FQqXIIcELLR2OWQcZ7la1QHi851Fy/Al2WNmeKtjAl4qPq1ncN/0+my3qU1G7HdinGsWOv7aWE5O1a9FZgJeSy5v7DcUiHuCJi2XsVIIkI78WBZ3GPQTvhs2sQQiJkuEd9V9/9sCWzanBNYF5OhFrGMo/0FRrJVexvlvF0apc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=htEpj31a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="htEpj31a" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DEC66C4CEF7; Fri, 20 Mar 2026 16:47:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774025257; bh=WdWA2hrSgUxDYtn4CcB4fFRlpQtCztod+x049Hswyq8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=htEpj31aiKAuapJGqKm/+82sWRo93k2qQvg6dk23Id2j0YXbzHjbKKYAOH4410OAi jYQ/FJqdrZbmGkeBhFB1fcHNPpBu4rkQaBf/F3t5+DNhFtxfH/GZTuXihRWeVPDMd2 R+2SvqgC1xd5YiAc6BUwr+7wOGfC1joW1Ug6ghdNWsPMn33JXc57OPBf0GlWN3M5Wu Wk9nE/3B9tuCor7kl+LYZXh0JC6XGOPjIlLFvx1cQNMj8BZDBWhSIndcf/5dLRhSCQ I5tlmEYTnOEvkkaMUXZRqnFrsSfqc0gbl6DYl3dUJqONJfHEFshubD51S+O4xg7zJf yTPhKB/0r/mMg== From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:15 -0500 Subject: [PATCH 2/5] dt-bindings: npu: arm,ethos: Add "arm,corstone1000-ethos-u85" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-dt-corstone1000-a320-v1-2-a549dfcfe8da@kernel.org> References: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> In-Reply-To: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: Frazer Carsley , Hugues Kamba Mpiana , Abdellatif El Khlifi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.15-dev The Corstone-1000-A320 platform contains an Ethos-U85 NPU. Add a specific compatible for it. Signed-off-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/npu/arm,ethos.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/npu/arm,ethos.yaml b/Documen= tation/devicetree/bindings/npu/arm,ethos.yaml index 716c4997f976..d5a1fae4db9d 100644 --- a/Documentation/devicetree/bindings/npu/arm,ethos.yaml +++ b/Documentation/devicetree/bindings/npu/arm,ethos.yaml @@ -30,7 +30,7 @@ properties: - fsl,imx93-npu - const: arm,ethos-u65 - items: - - {} + - const: arm,corstone1000-ethos-u85 - const: arm,ethos-u85 =20 reg: --=20 2.51.0 From nobody Mon Apr 6 10:32:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0CF53D88EA; Fri, 20 Mar 2026 16:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025258; cv=none; b=tls8++V/bz27NhuVi511NkzwKIDzJBVbFlCbMHhMzk3uIyl6ny1UhHg+kz3JK1o2ld2sAR505l9pQayIslQ6629w8XNF8ZR6TG/KMKed6L9Nn9VL0AhHven8DZHeKQapuUnAp9sRSExgG0Yq1Z3vQ+9pUFi08ydrvr9WyXq88Zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025258; c=relaxed/simple; bh=sK9Je7eEOHO0wb9I2WtylwKv1pOI57lliw+dQ40lnJo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lzYQF0Dei8Llp2ERLaZtjfKAMOoHsjkSBhMfYsfwMiALNXxrFqaTUQpsMO8jEllX95EPFxOj9VZEHHM5ImJ2YTKRpfwG+8W2EGCIDQtJN77qaqb1iolpnoQCw67Bppd/WYsuqv8UK3xML3CKrA/GdP2tNenVsFVn99BAAMzzDcY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O/zzqxqk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O/zzqxqk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0B59C4CEF7; Fri, 20 Mar 2026 16:47:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774025258; bh=sK9Je7eEOHO0wb9I2WtylwKv1pOI57lliw+dQ40lnJo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=O/zzqxqk9VqjAANVq7YDdiaokLbu44P5/67s5HUnm/t8DTYF3xkcrspcDP2VXspvp o3+lHsw326285W/ymwngxI1IszpKN5dgfSCmvWQRruAqMauEH12zK4oz3Qvvv0VPGk p0eYTW2Ha7L4nPsqNqQpj4ibJfgQM6n/IjD0PotT+Jyi+uZu5xK/7EGiNCv96oEESs 27Hqm6XrZSCWcm4L/HZ8ZHnDR4BCFZO0R/yolmi2IjQY4RH8os2TPMGpDbg5udvDMZ fb08XC5LBsQw7YxYzA7bozLDJ43h7bAI9wn7jeisuw+bAspHfpZ64ycwQWQHpJG9f7 uRtu+aevcJ/Eg== From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:16 -0500 Subject: [PATCH 3/5] arm64: dts: arm/corstone1000: Move cpu nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-dt-corstone1000-a320-v1-3-a549dfcfe8da@kernel.org> References: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> In-Reply-To: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: Frazer Carsley , Hugues Kamba Mpiana , Abdellatif El Khlifi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.15-dev In preparation to add a new Corstone-1000 variation with different CPUs, move the CPU nodes into the specific platforms and out of the common corstone1000.dtsi. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 54 ++++++++++++++++-------= ---- arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 13 +++++++ arch/arm64/boot/dts/arm/corstone1000.dtsi | 13 ------- 3 files changed, 45 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot= /dts/arm/corstone1000-fvp.dts index 66ba6b027193..e479c79c1ea7 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -48,30 +48,40 @@ sdmmc1: mmc@50000000 { clocks =3D <&smbclk>, <&refclk100mhz>; clock-names =3D "smclk", "apb_pclk"; }; -}; + cpus: cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; =20 -&cpus { - cpu1: cpu@1 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a35"; - reg =3D <0x1>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - }; + cpu: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0 0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; =20 - cpu2: cpu@2 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a35"; - reg =3D <0x2>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - }; + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0 0x1>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0 0x2>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; =20 - cpu3: cpu@3 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a35"; - reg =3D <0x3>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0 0x3>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; }; }; diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boo= t/dts/arm/corstone1000-mps3.dts index 10d265be0c02..adcfaf7c55b8 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts @@ -13,6 +13,19 @@ / { model =3D "ARM Corstone1000 FPGA MPS3 board"; compatible =3D "arm,corstone1000-mps3"; =20 + cpus: cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0 0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + }; + smsc: ethernet@4010000 { compatible =3D "smsc,lan9220", "smsc,lan9115"; reg =3D <0x40100000 0x10000>; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dt= s/arm/corstone1000.dtsi index f35a5c96f3da..4d57dc197918 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -21,19 +21,6 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 - cpus: cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - - cpu: cpu@0 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a35"; - reg =3D <0>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - }; - }; - memory@88200000 { device_type =3D "memory"; reg =3D <0x88200000 0x77e00000>; --=20 2.51.0 From nobody Mon Apr 6 10:32:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A1AA3D88FD; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YBtnrY8L" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DC151C4CEF7; Fri, 20 Mar 2026 16:47:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774025259; bh=Jfx0Fsvzz4Z6n6+m6jipZ+hJb8968gAtSbrKrHZMyAE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YBtnrY8L3oIHbXjfd01SOf8UaHSrAfFf7eZE/bKnS74AuwaZaWjx2oJKvX1DhJ9ej y+tHKPjx0/L7gyPe6jiJTSYW9ADdp/vQq7tFHSTuDkZbnHvG3voieqFz0j2t9UP7Um K18tGWBNnNqAHO9NqVuHGCSEVbWPfBTJa3kZ4FHXt+Iqz1a+dj4EVMXnAYjHG6P5Oh fD/iHAoFnz0sDuTyyyzjHNBCypHt3rZv00QUU7RqZj8vkAmGqLi5vcV8TCH1cJX9aQ 1bILUREgvCtt0AI6va+gDobtRmi+SaFF7x/8mwnEV9pkA93uZGJMycFdN4CGgukXDz MIlnJPggRZQvA== From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:17 -0500 Subject: [PATCH 4/5] arm64: dts: arm/corstone1000: Move FVP peripherals to separate .dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-dt-corstone1000-a320-v1-4-a549dfcfe8da@kernel.org> References: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> In-Reply-To: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: Frazer Carsley , Hugues Kamba Mpiana , Abdellatif El Khlifi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.15-dev The FVPs have a common set of peripherals specific to the FVP. Move these to a separate .dtsi so they can be shared across FVP platforms. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 36 +--------------------- arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi | 44 +++++++++++++++++++++++= ++++ 2 files changed, 45 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot= /dts/arm/corstone1000-fvp.dts index e479c79c1ea7..fac0999b1901 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -8,46 +8,12 @@ /dts-v1/; =20 #include "corstone1000.dtsi" +#include "corstone1000-fvp.dtsi" =20 / { model =3D "ARM Corstone1000 FVP (Fixed Virtual Platform)"; compatible =3D "arm,corstone1000-fvp"; =20 - smsc: ethernet@4010000 { - compatible =3D "smsc,lan91c111"; - reg =3D <0x40100000 0x10000>; - phy-mode =3D "mii"; - interrupts =3D ; - reg-io-width =3D <2>; - }; - - vmmc_v3_3d: regulator-vmmc { - compatible =3D "regulator-fixed"; - regulator-name =3D "vmmc_supply"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - }; - - sdmmc0: mmc@40300000 { - compatible =3D "arm,pl18x", "arm,primecell"; - reg =3D <0x40300000 0x1000>; - interrupts =3D ; - max-frequency =3D <12000000>; - vmmc-supply =3D <&vmmc_v3_3d>; - clocks =3D <&smbclk>, <&refclk100mhz>; - clock-names =3D "smclk", "apb_pclk"; - }; - - sdmmc1: mmc@50000000 { - compatible =3D "arm,pl18x", "arm,primecell"; - reg =3D <0x50000000 0x10000>; - interrupts =3D ; - max-frequency =3D <12000000>; - vmmc-supply =3D <&vmmc_v3_3d>; - clocks =3D <&smbclk>, <&refclk100mhz>; - clock-names =3D "smclk", "apb_pclk"; - }; cpus: cpus { #address-cells =3D <2>; #size-cells =3D <0>; diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi b/arch/arm64/boo= t/dts/arm/corstone1000-fvp.dtsi new file mode 100644 index 000000000000..dc6d77446e8f --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/ { + smsc: ethernet@4010000 { + compatible =3D "smsc,lan91c111"; + reg =3D <0x40100000 0x10000>; + phy-mode =3D "mii"; + interrupts =3D ; + reg-io-width =3D <2>; + }; + + vmmc_v3_3d: regulator-vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vmmc_supply"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible =3D "arm,pl18x", "arm,primecell"; + reg =3D <0x40300000 0x1000>; + interrupts =3D ; + max-frequency =3D <12000000>; + vmmc-supply =3D <&vmmc_v3_3d>; + clocks =3D <&smbclk>, <&refclk100mhz>; + clock-names =3D "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible =3D "arm,pl18x", "arm,primecell"; + reg =3D <0x50000000 0x10000>; + interrupts =3D ; + max-frequency =3D <12000000>; + vmmc-supply =3D <&vmmc_v3_3d>; + clocks =3D <&smbclk>, <&refclk100mhz>; + clock-names =3D "smclk", "apb_pclk"; + }; +}; --=20 2.51.0 From nobody Mon Apr 6 10:32:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A3F53D902B; Fri, 20 Mar 2026 16:47:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025260; cv=none; b=GchYv4uMib7s8Lcmc168+GjocKvsW97Zo5eX4IfEm0rjd8M1XFS23CB+mayrjsGa77Eq62/1mQ1zHT0lGMp00tJg3RDJkr0Iq6HvJ72y9XTe4+p984gXTS/1CU+7sHUaLvmkpAh0WmtJL+b7Ax515JHp/nTxLZORPSIyBQbcGeA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774025260; c=relaxed/simple; bh=+jSC2BcOr5bTFiGTzqJGWVjWkhUc4jNiP7GFwpFjfWs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nG6l/2pT4GHgPE4WGuJbZJMb5G5SdpboFZlQH0qd+rGfSUBEIhDarbPKTUvv+fqOMhhLqqogkGfE1Oo01P7xIrUx+6clf48/oFoTQbZjkm9O5Blyc+kym6XnMF4hOunV8G+stp8bEDlHc2PV+6DblImbYs9GDCBDkeRbucEMyfw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E96bmnpf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E96bmnpf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8372C4CEF7; Fri, 20 Mar 2026 16:47:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774025260; bh=+jSC2BcOr5bTFiGTzqJGWVjWkhUc4jNiP7GFwpFjfWs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=E96bmnpfmHgxHqt2Jnj7OMb8dMAA7xDxsiR2OZLPBhUKCaJVA55ysug/aHl7DoFK9 4LgEqs4ZbThdc9M1y/zRpGMV4mumK7L4hmMtnS+RFJ2yWZpLAaRSrIs1aG3Wbrxls7 Flkb1fkPm4srpes/8FVDPN9yVja8QZSZ4+i6tancyVPg+wjDzbntznboIN6skpvxaj kZ7i8OEv3yZGGjd1IRFRNW9RBEXrlGH/uFYNylE2FVuICOKXyVNmSeQlXsaqkFWchZ UHkFmTuQv42HlT12WlLJaKr4GloKp+dVRMQ0zZ9z5Gq/p7GaOD8qP/w4e5z0OClH/U P3+qWdojv7/xQ== From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:18 -0500 Subject: [PATCH 5/5] arm64: dts: arm/corstone1000: Add corstone-1000-a320 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-dt-corstone1000-a320-v1-5-a549dfcfe8da@kernel.org> References: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> In-Reply-To: <20260320-dt-corstone1000-a320-v1-0-a549dfcfe8da@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: Frazer Carsley , Hugues Kamba Mpiana , Abdellatif El Khlifi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.15-dev The Corstone-1000-a320 is a Corstone-1000 derivative with Cortex-A320 cores, GIC-600, and Ethos-U85 NPU. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts | 15 ++++ arch/arm64/boot/dts/arm/corstone1000-a320.dtsi | 91 +++++++++++++++++++= ++++ 3 files changed, 107 insertions(+) diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index f30ee045dc95..fa035c68991a 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,4 +7,5 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-a320-fvp.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts b/arch/arm64= /boot/dts/arm/corstone1000-a320-fvp.dts new file mode 100644 index 000000000000..0f72af78b5e1 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000-a320.dtsi" +#include "corstone1000-fvp.dtsi" + +/ { + model =3D "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)"; + compatible =3D "arm,corstone1000-a320-fvp"; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi b/arch/arm64/bo= ot/dts/arm/corstone1000-a320.dtsi new file mode 100644 index 000000000000..f0937914350c --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + */ + +#include + +#include "corstone1000.dtsi" + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpus: cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a320"; + reg =3D <0 0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a320"; + reg =3D <0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a320"; + reg =3D <0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a320"; + reg =3D <0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + sram: sram@2400000 { + compatible =3D "mmio-sram"; + reg =3D <0x02400000 0x200000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + }; + + gic: interrupt-controller@1c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-controller; + reg =3D <0x1c000000 0x10000>, + <0x1c040000 0x80000>; + interrupts =3D ; + }; + + + soc { + npu@1a050000 { + compatible =3D "arm,corstone1000-ethos-u85", "arm,ethos-u85"; + reg =3D <0x1a050000 0x1400>; + interrupts =3D ; + clocks =3D <&refclk100mhz>, <&refclk100mhz>; + clock-names =3D "core", "apb"; + sram =3D <&sram>; + }; + }; +}; --=20 2.51.0