From nobody Mon Apr 6 10:43:22 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68D1D3CD8C9 for ; Fri, 20 Mar 2026 15:47:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774021654; cv=none; b=rQBs4BhpwHehm9VpTbygExbPrhwJ4qFNdcuJAOIe+MRC06cnqeXG/XumnW/K5WUp2mqpLOKE6CxqHbaV8YxLx+5C61NYKy1AXkl4n28gDfL0IzCZCaWU/WKwApu+v7lydoEOR23AIvcZzpqICATUf7vSz8FbOQyCRsUnElcqOik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774021654; c=relaxed/simple; bh=1YCIRlzvccz0o7Yp+gHCS/xf6jY6fB4+9eaW9ZuF5O4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qHQaG7HWkf89IBrv6EDQuWqCbxjufrtBYN5/Y5WXR7dKSrDtzB1dwXJujenMUdp+LryagBbgsnka5zFRJtHHLLjubf+X6byTZ4zU47CzyVKBVmjWFih7bbqZpoSAUVsyy6HR7ZCyPuQ6yL+o+BPDdnd8hXUTln0p97Pek5xF+2M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fw7pKAYb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fw7pKAYb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A0843C4CEF7; Fri, 20 Mar 2026 15:47:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774021653; bh=1YCIRlzvccz0o7Yp+gHCS/xf6jY6fB4+9eaW9ZuF5O4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fw7pKAYbdzdWgsBoGLn/pE6Ky0mApfADe597sxloct0VOLhkI6uh0fFrtmAFtzsvI HzFWVHbS57a07mg68mDVkUrtYJuHVqb1LOtP0FG5BibtgDa+Hv6ycW7NqQPYQ4PplY KjQ/chDNGqFnJxnXbZhXnpAAk1MOHP3VsB7gTyTEty6k/vNpKMM/STuF536sGo4p67 vmlDJvA+z9Ivh/EtHR+/Nyi6A1oUQUEs2EoGYzVSqv/iKwV679D7u4xGvPzYfFzk/N PRBVcGvsZOl1dblC0NMrCOfsaGZk61pZ9dA1is8mEWLWVf9h+lJeWiv4pZTNkstELp HqZL2Du4kc4iw== From: Mark Brown Date: Fri, 20 Mar 2026 15:44:15 +0000 Subject: [PATCH v8 2/2] arm64/sve: Disable TIF_SVE on syscall once per second Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260320-arm64-sve-trap-mitigation-v8-2-8bf116c8e360@kernel.org> References: <20260320-arm64-sve-trap-mitigation-v8-0-8bf116c8e360@kernel.org> In-Reply-To: <20260320-arm64-sve-trap-mitigation-v8-0-8bf116c8e360@kernel.org> To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Ryan Roberts , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-db13a X-Developer-Signature: v=1; a=openpgp-sha256; l=2697; i=broonie@kernel.org; h=from:subject:message-id; bh=1YCIRlzvccz0o7Yp+gHCS/xf6jY6fB4+9eaW9ZuF5O4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpvWwQk8La/rwzGdEW7tZNW+j6qERjnRYi476yP rk1yBlp0FWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCab1sEAAKCRAk1otyXVSH 0MnwB/9dJOh5WieStSHuudcz4Jesfz699a5guOYhmjrXqQQ+enriUxPl9v2T2rcWwGUeqpym4rJ SkERTDGcBtrXGlZZDIrZGc4lnJozjkF9qgfizi9lonA2GzedSsmnk3T3QW2mv9Zi1vVwAFItsA4 bBSjfAPof/llpQcZVf66CoPSDzhf9frhTDaq7vK/iJotuqhO52UpEcF22nktMuHXOWH0hdUEaVW UYyOmT2JnfRAoHCI25c6GjI5vCvbfvmRcs1D+c/SgxeIc5WecZOh2AQc7tNeQqq6nPXpE+maPHA 8AXtLJ/MF9EB115m/dk6p48f8w1XYCeDKNMP7WN66TARLEI8 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Our syscall ABI requires that when performing a syscall the portions of the Z registers not shared with the V registers, the P and FFR registers are reset to 0. Since we have no way of monitoring EL0 SVE usage this is implemented by changing the in register values on every syscall for tasks which have SVE enabled, for systems with 128 bit SVE vector lengths this has been benchmarked as a 6% overhead. We currently support disabling SVE for userspace tasks when loading the floating point state from memory during a syscall, allowing tasks that use SVE infrequently to avoid this overhead, but this may not help CPU bound tasks if they are not fortunate enough to block or be scheduled during a syscall. This is done whenever the state is loaded from a second after the last time the task generate a SVE access trap. Extend this mechanism to also apply during syscall entry, disabling SVE instead of flushing the live registers when we perform a syscall a second after the last time a SVE access trap was taken. This adds an additional memory access and branch for tasks using SVE and means that CPU bound tasks actively using SVE will take extra SVE access traps (at most one per second) but will allows CPU bound tasks that infrequently use SVE to avoid the overhead of flushing the registers on syscall. On a system with 128 bit SVE vectors fp-pidbench shows a roughly 4.5% improvement compared to baseline after having used SVE, for a roughly 0.4% overhead when SVE is used between each syscall. Obviously this is very much a microbenchmark. This is purely a performance optimisation, there should be no functional change. Signed-off-by: Mark Brown --- arch/arm64/kernel/entry-common.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-com= mon.c index 3625797e9ee8..a7b7ec66f084 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -234,8 +234,18 @@ static inline void fpsimd_syscall_enter(void) if (test_thread_flag(TIF_SVE)) { unsigned int sve_vq_minus_one; =20 - sve_vq_minus_one =3D sve_vq_from_vl(task_get_sve_vl(current)) - 1; - sve_flush_live(true, sve_vq_minus_one); + /* + * Ensure that tasks that don't block in a syscall + * also get a chance to drop TIF_SVE. + */ + if (unlikely(time_after(jiffies, + current->thread.sve_timeout))) { + clear_thread_flag(TIF_SVE); + sve_user_disable(); + } else { + sve_vq_minus_one =3D sve_vq_from_vl(task_get_sve_vl(current)) - 1; + sve_flush_live(true, sve_vq_minus_one); + } } =20 /* --=20 2.47.3