From nobody Mon Apr 6 10:42:04 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D35A3195FB; Fri, 20 Mar 2026 05:46:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985613; cv=none; b=T0jjoxf5Y65iFOVeEymx7Jq/H3gjbZKl4OFjUcYE0tIamutCbVWgEiUjSpFm0h2Dgt2toUD6RyyAoT7Z2pBtS3AqpeIYXX4Br8gbtuKcXYmOLyQ0Ix7e0feh/ljDBgn2OGUM2ntIQ69aisnY0YOfYVrL6PIaqHAAjkDm1E4XRgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773985613; c=relaxed/simple; bh=NmmhJK7uvUVre1uvvr5Vjz5lKqP/DkupFhrPhytp+BM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=qZCW/y0io2H5xfQQ6JYNnV1/iwTZgSYtg0+P8/LQhMCtYrZ2wfk0UUAZ3RHJg7mJFnBHBH0tSjoLmH/RwZ3P4KZDexVYnzuFObcniMTwVVTK70sZD7yWbhx5Pm//T6iVY4kLxSdSuGNkjSV/z10RkyZPUNsU1S4qA3IZU86ViIg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 20 Mar 2026 13:46:40 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 20 Mar 2026 13:46:40 +0800 From: Billy Tsai Date: Fri, 20 Mar 2026 13:46:36 +0800 Subject: [PATCH v3 2/4] iio: adc: Enable multiple consecutive channels based on model data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260320-adc-v3-2-bc0eac04ef7c@aspeedtech.com> References: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> In-Reply-To: <20260320-adc-v3-0-bc0eac04ef7c@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773985600; l=1731; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=NmmhJK7uvUVre1uvvr5Vjz5lKqP/DkupFhrPhytp+BM=; b=gjpKlIm9OA6WHPNLApb+1XgFzo7WUdGq9UT4iOA2UGLsak9TbZYPWpTilmInbAtps5oQztHh0 5xUT1/v5ZAlDgV06+pcVwoPjla6BPWGia5EpXe9BoSVfqmeYFm13uVZ X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Add helpers to generate channel masks and enable multiple ADC channels according to the device model's channel count. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 8eebaa3dc534..3ff24474f394 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -123,6 +123,24 @@ struct aspeed_adc_data { struct adc_gain battery_mode_gain; }; =20 +/* + * Enable multiple consecutive channels starting from channel 0. + * This creates a bitmask for channels 0 to (num_channels - 1). + * For example: num_channels=3D3 creates mask 0x0007 (channels 0,1,2) + */ +static inline u32 aspeed_adc_channels_mask(unsigned int num_channels) +{ + if (num_channels > 16) + return GENMASK(15, 0); + + return BIT(num_channels) - 1; +} + +static inline unsigned int aspeed_adc_get_active_channels(const struct asp= eed_adc_data *data) +{ + return data->model_data->num_channels; +} + #define ASPEED_CHAN(_idx, _data_reg_addr) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -612,7 +630,9 @@ static int aspeed_adc_probe(struct platform_device *pde= v) /* Start all channels in normal mode. */ adc_engine_control_reg_val =3D readl(data->base + ASPEED_REG_ENGINE_CONTROL); - adc_engine_control_reg_val |=3D ASPEED_ADC_CTRL_CHANNEL; + FIELD_MODIFY(ASPEED_ADC_CTRL_CHANNEL, &adc_engine_control_reg_val, + aspeed_adc_channels_mask(aspeed_adc_get_active_channels(data))); + writel(adc_engine_control_reg_val, data->base + ASPEED_REG_ENGINE_CONTROL); =20 --=20 2.34.1